1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
4 * <angelogioacchino.delregno@collabora.com>
5 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
6 * Copyright (c) 2022, Marijn Suijten <marijn.suijten@somainline.org>
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
25 compatible = "fixed-clock";
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 cpu-idle-states = <&little_cpu_sleep_0>;
40 capacity-dmips-mhz = <573>;
41 next-level-cache = <&l2_0>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 cpu-idle-states = <&little_cpu_sleep_0>;
51 capacity-dmips-mhz = <573>;
52 next-level-cache = <&l2_0>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 cpu-idle-states = <&little_cpu_sleep_0>;
62 capacity-dmips-mhz = <573>;
63 next-level-cache = <&l2_0>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&little_cpu_sleep_0>;
73 capacity-dmips-mhz = <573>;
74 next-level-cache = <&l2_0>;
80 compatible = "arm,cortex-a72";
82 enable-method = "psci";
83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
84 capacity-dmips-mhz = <1024>;
85 next-level-cache = <&l2_1>;
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
95 capacity-dmips-mhz = <1024>;
96 next-level-cache = <&l2_1>;
102 compatible = "arm,cortex-a72";
104 enable-method = "psci";
105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a72";
115 enable-method = "psci";
116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
117 capacity-dmips-mhz = <1024>;
118 next-level-cache = <&l2_1>;
119 #cooling-cells = <2>;
161 entry-method = "psci";
163 little_cpu_sleep_0: cpu-sleep-0-0 {
164 compatible = "arm,idle-state";
165 idle-state-name = "little-power-collapse";
166 arm,psci-suspend-param = <0x40000003>;
167 entry-latency-us = <181>;
168 exit-latency-us = <149>;
169 min-residency-us = <703>;
173 big_cpu_sleep_0: cpu-sleep-1-0 {
174 compatible = "arm,idle-state";
175 idle-state-name = "big-retention";
176 arm,psci-suspend-param = <0x00000002>;
177 entry-latency-us = <142>;
178 exit-latency-us = <99>;
179 min-residency-us = <242>;
182 big_cpu_sleep_1: cpu-sleep-1-1 {
183 compatible = "arm,idle-state";
184 idle-state-name = "big-power-collapse";
185 arm,psci-suspend-param = <0x40000003>;
186 entry-latency-us = <158>;
187 exit-latency-us = <144>;
188 min-residency-us = <863>;
194 compatible = "cache";
200 compatible = "cache";
208 compatible = "qcom,scm-msm8976", "qcom,scm";
209 clocks = <&gcc GCC_CRYPTO_CLK>,
210 <&gcc GCC_CRYPTO_AXI_CLK>,
211 <&gcc GCC_CRYPTO_AHB_CLK>;
212 clock-names = "core", "bus", "iface";
215 qcom,dload-mode = <&tcsr 0x6100>;
220 device_type = "memory";
221 /* We expect the bootloader to fill in the size */
222 reg = <0x0 0x80000000 0x0 0x0>;
226 compatible = "arm,armv8-pmuv3";
227 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
231 compatible = "arm,psci-1.0";
236 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
239 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
240 qcom,ipc = <&apcs 8 0>;
241 qcom,smd-edge = <15>;
243 rpm_requests: rpm-requests {
244 compatible = "qcom,rpm-msm8976";
245 qcom,smd-channels = "rpm_requests";
247 rpmcc: clock-controller {
248 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
249 clocks = <&xo_board>;
254 rpmpd: power-controller {
255 compatible = "qcom,msm8976-rpmpd";
256 #power-domain-cells = <1>;
257 operating-points-v2 = <&rpmpd_opp_table>;
259 rpmpd_opp_table: opp-table {
260 compatible = "operating-points-v2";
262 rpmpd_opp_ret: opp1 {
263 opp-level = <RPM_SMD_LEVEL_RETENTION>;
266 rpmpd_opp_ret_plus: opp2 {
267 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
270 rpmpd_opp_min_svs: opp3 {
271 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
274 rpmpd_opp_low_svs: opp4 {
275 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
278 rpmpd_opp_svs: opp5 {
279 opp-level = <RPM_SMD_LEVEL_SVS>;
282 rpmpd_opp_svs_plus: opp6 {
283 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
286 rpmpd_opp_nom: opp7 {
287 opp-level = <RPM_SMD_LEVEL_NOM>;
290 rpmpd_opp_nom_plus: opp8 {
291 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
294 rpmpd_opp_turbo: opp9 {
295 opp-level = <RPM_SMD_LEVEL_TURBO>;
298 rpmpd_opp_turbo_no_cpr: opp10 {
299 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
302 rpmpd_opp_turbo_high: opp111 {
303 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
312 #address-cells = <2>;
316 ext-region@85b00000 {
317 reg = <0x0 0x85b00000 0x0 0x500000>;
322 compatible = "qcom,smem";
323 reg = <0x0 0x86300000 0x0 0x100000>;
326 hwlocks = <&tcsr_mutex 3>;
327 qcom,rpm-msg-ram = <&rpm_msg_ram>;
331 reg = <0x0 0x86400000 0x0 0x800000>;
335 mpss_mem: mpss@86c00000 {
336 reg = <0x0 0x86c00000 0x0 0x5600000>;
340 lpass_mem: lpass@8c200000 {
341 reg = <0x0 0x8c200000 0x0 0x1000000>;
345 wcnss_fw_mem: wcnss@8d200000 {
346 reg = <0x0 0x8d200000 0x0 0x800000>;
350 venus_mem: memory@8da00000 {
351 reg = <0x0 0x8da00000 0x0 0x2600000>;
356 reg = <0x0 0x8dd00000 0x0 0x1400000>;
362 compatible = "qcom,smp2p";
363 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
364 qcom,ipc = <&apcs 8 10>;
366 qcom,local-pid = <0>;
367 qcom,remote-pid = <2>;
368 qcom,smem = <443>, <429>;
370 adsp_smp2p_out: master-kernel {
371 qcom,entry-name = "master-kernel";
373 #qcom,smem-state-cells = <1>;
376 adsp_smp2p_in: slave-kernel {
377 qcom,entry-name = "slave-kernel";
379 interrupt-controller;
380 #interrupt-cells = <2>;
385 compatible = "qcom,smp2p";
386 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
387 qcom,ipc = <&apcs 8 14>;
389 qcom,local-pid = <0>;
390 qcom,remote-pid = <1>;
391 qcom,smem = <435>, <428>;
393 modem_smp2p_out: master-kernel {
394 qcom,entry-name = "master-kernel";
396 #qcom,smem-state-cells = <1>;
399 modem_smp2p_in: slave-kernel {
400 qcom,entry-name = "slave-kernel";
402 interrupt-controller;
403 #interrupt-cells = <2>;
408 compatible = "qcom,smp2p";
409 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
410 qcom,ipc = <&apcs 8 18>;
412 qcom,local-pid = <0>;
413 qcom,remote-pid = <4>;
414 qcom,smem = <451>, <431>;
416 wcnss_smp2p_out: master-kernel {
417 qcom,entry-name = "master-kernel";
419 #qcom,smem-state-cells = <1>;
422 wcnss_smp2p_in: slave-kernel {
423 qcom,entry-name = "slave-kernel";
425 interrupt-controller;
426 #interrupt-cells = <2>;
431 compatible = "qcom,smsm";
433 #address-cells = <1>;
436 qcom,ipc-1 = <&apcs 8 13>;
437 qcom,ipc-2 = <&apcs 8 9>;
438 qcom,ipc-3 = <&apcs 8 19>;
442 #qcom,smem-state-cells = <1>;
445 hexagon_smsm: hexagon@1 {
447 interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>;
449 interrupt-controller;
450 #interrupt-cells = <2>;
453 wcnss_smsm: wcnss@6 {
455 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
457 interrupt-controller;
458 #interrupt-cells = <2>;
463 #address-cells = <1>;
465 ranges = <0 0 0 0xffffffff>;
466 compatible = "simple-bus";
469 compatible = "qcom,prng";
470 reg = <0x00022000 0x140>;
471 clocks = <&gcc GCC_PRNG_AHB_CLK>;
472 clock-names = "core";
475 rpm_msg_ram: sram@60000 {
476 compatible = "qcom,rpm-msg-ram";
477 reg = <0x00060000 0x8000>;
480 usb_hs_phy: phy@6c000 {
481 compatible = "qcom,usb-hs-28nm-femtophy";
482 reg = <0x0006c000 0x200>;
484 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
485 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
486 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
487 clock-names = "ref", "ahb", "sleep";
488 resets = <&gcc RST_QUSB2_PHY_BCR>,
489 <&gcc RST_USB2_HS_PHY_ONLY_BCR>;
490 reset-names = "phy", "por";
494 qfprom: qfprom@a4000 {
495 compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
496 reg = <0x000a4000 0x1000>;
497 #address-cells = <1>;
500 tsens_base1: base1@218 {
505 tsens_s0_p1: s0-p1@219 {
510 tsens_s0_p2: s0-p2@219 {
515 tsens_s1_p1: s1-p1@21a {
520 tsens_s1_p2: s1-p2@21b {
525 tsens_s2_p1: s2-p1@21c {
530 tsens_s2_p2: s2-p2@21c {
535 tsens_s3_p1: s3-p1@21d {
540 tsens_s3_p2: s3-p2@21e {
545 tsens_base2: base2@220 {
550 tsens_s4_p1: s4-p1@221 {
555 tsens_s4_p2: s4-p2@221 {
560 tsens_s5_p1: s5-p1@222 {
565 tsens_s5_p2: s5-p2@223 {
570 tsens_s6_p1: s6-p1@224 {
575 tsens_s6_p2: s6-p2@224 {
580 tsens_s7_p1: s7-p1@225 {
585 tsens_s7_p2: s7-p2@226 {
590 tsens_mode: mode@228 {
595 tsens_s8_p1: s8-p1@228 {
600 tsens_s8_p2: s8-p2@229 {
605 tsens_s9_p1: s9-p1@229 {
610 tsens_s9_p2: s9-p2@22a {
615 tsens_s10_p1: s10-p1@22b {
620 tsens_s10_p2: s10-p2@22c {
626 tsens: thermal-sensor@4a9000 {
627 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
628 reg = <0x004a9000 0x1000>, /* TM */
629 <0x004a8000 0x1000>; /* SROT */
630 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
631 interrupt-names = "uplow";
632 nvmem-cells = <&tsens_mode>,
633 <&tsens_base1>, <&tsens_base2>,
634 <&tsens_s0_p1>, <&tsens_s0_p2>,
635 <&tsens_s1_p1>, <&tsens_s1_p2>,
636 <&tsens_s2_p1>, <&tsens_s2_p2>,
637 <&tsens_s3_p1>, <&tsens_s3_p2>,
638 <&tsens_s4_p1>, <&tsens_s4_p2>,
639 <&tsens_s5_p1>, <&tsens_s5_p2>,
640 <&tsens_s6_p1>, <&tsens_s6_p2>,
641 <&tsens_s7_p1>, <&tsens_s7_p2>,
642 <&tsens_s8_p1>, <&tsens_s8_p2>,
643 <&tsens_s9_p1>, <&tsens_s9_p2>,
644 <&tsens_s10_p1>, <&tsens_s10_p2>;
645 nvmem-cell-names = "mode",
658 #qcom,sensors = <11>;
659 #thermal-sensor-cells = <1>;
662 tlmm: pinctrl@1000000 {
663 compatible = "qcom,msm8976-pinctrl";
664 reg = <0x01000000 0x300000>;
665 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
668 gpio-ranges = <&tlmm 0 0 145>;
669 interrupt-controller;
670 #interrupt-cells = <2>;
672 spi1_default: spi0-default-state {
674 pins = "gpio0", "gpio1", "gpio3";
675 function = "blsp_spi1";
676 drive-strength = <12>;
682 function = "blsp_spi1";
683 drive-strength = <2>;
688 spi1_sleep: spi0-sleep-state {
690 pins = "gpio0", "gpio1", "gpio3";
692 drive-strength = <2>;
699 drive-strength = <2>;
704 blsp1_i2c2_default: blsp1-i2c2-default-state {
705 pins = "gpio6", "gpio7";
706 function = "blsp_i2c2";
707 drive-strength = <2>;
711 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
712 pins = "gpio6", "gpio7";
714 drive-strength = <2>;
718 blsp1_i2c4_default: blsp1-i2c4-default-state {
719 pins = "gpio14", "gpio15";
720 function = "blsp_i2c4";
721 drive-strength = <2>;
725 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
726 pins = "gpio14", "gpio15";
728 drive-strength = <2>;
732 blsp2_uart2_active: blsp2-uart2-active-state {
733 pins = "gpio20", "gpio21";
734 function = "blsp_uart6";
735 drive-strength = <4>;
739 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
740 pins = "gpio20", "gpio21";
742 drive-strength = <2>;
746 /* 4 (not 6!) interfaces per QUP, BLSP2 indexes are numbered (n)+4 */
747 blsp2_i2c2_default: blsp2-i2c2-default-state {
748 pins = "gpio22", "gpio23";
749 function = "blsp_i2c6";
750 drive-strength = <2>;
754 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
755 pins = "gpio22", "gpio23";
757 drive-strength = <2>;
761 blsp2_i2c4_default: blsp2-i2c4-default-state {
762 pins = "gpio18", "gpio19";
763 function = "blsp_i2c8";
764 drive-strength = <2>;
768 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
769 pins = "gpio18", "gpio19";
771 drive-strength = <2>;
776 gcc: clock-controller@1800000 {
777 compatible = "qcom,gcc-msm8976";
778 reg = <0x01800000 0x80000>;
781 #power-domain-cells = <1>;
783 assigned-clocks = <&gcc GPLL3>;
784 assigned-clock-rates = <1100000000>;
786 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
787 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
800 tcsr_mutex: hwlock@1905000 {
801 compatible = "qcom,tcsr-mutex";
802 reg = <0x01905000 0x20000>;
806 tcsr: syscon@1937000 {
807 compatible = "qcom,msm8976-tcsr", "syscon";
808 reg = <0x01937000 0x30000>;
811 spmi_bus: spmi@200f000 {
812 compatible = "qcom,spmi-pmic-arb";
813 reg = <0x0200f000 0x1000>,
814 <0x02400000 0x800000>,
815 <0x02c00000 0x800000>,
816 <0x03800000 0x200000>,
818 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
819 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
820 interrupt-names = "periph_irq";
824 #address-cells = <2>;
826 interrupt-controller;
827 #interrupt-cells = <4>;
830 sdhc_1: mmc@7824900 {
831 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
832 reg = <0x07824900 0x500>, <0x07824000 0x800>;
833 reg-names = "hc", "core";
835 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
837 interrupt-names = "hc_irq", "pwr_irq";
839 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
840 <&gcc GCC_SDCC1_APPS_CLK>,
841 <&rpmcc RPM_SMD_XO_CLK_SRC>;
842 clock-names = "iface", "core", "xo";
846 sdhc_2: mmc@7864900 {
847 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
848 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
849 reg-names = "hc", "core";
851 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
853 interrupt-names = "hc_irq", "pwr_irq";
855 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
856 <&gcc GCC_SDCC2_APPS_CLK>,
857 <&rpmcc RPM_SMD_XO_CLK_SRC>;
858 clock-names = "iface", "core", "xo";
862 blsp1_dma: dma-controller@7884000 {
863 compatible = "qcom,bam-v1.7.0";
864 reg = <0x07884000 0x1f000>;
865 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
867 clock-names = "bam_clk";
872 blsp1_uart1: serial@78af000 {
873 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
874 reg = <0x078af000 0x200>;
875 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
877 clock-names = "core", "iface";
878 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
879 dma-names = "tx", "rx";
883 blsp1_uart2: serial@78b0000 {
884 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
885 reg = <0x078b0000 0x200>;
886 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
888 clock-names = "core", "iface";
889 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
890 dma-names = "tx", "rx";
894 blsp1_spi1: spi@78b5000 {
895 compatible = "qcom,spi-qup-v2.2.1";
896 reg = <0x078b5000 0x500>;
897 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
899 clock-names = "core", "iface";
900 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
901 dma-names = "tx", "rx";
902 pinctrl-names = "default", "sleep";
903 pinctrl-0 = <&spi1_default>;
904 pinctrl-1 = <&spi1_sleep>;
905 #address-cells = <1>;
910 blsp1_i2c2: i2c@78b6000 {
911 compatible = "qcom,i2c-qup-v2.2.1";
912 reg = <0x078b6000 0x500>;
913 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
915 clock-names = "core", "iface";
916 clock-frequency = <400000>;
917 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
918 dma-names = "tx", "rx";
919 pinctrl-names = "default", "sleep";
920 pinctrl-0 = <&blsp1_i2c2_default>;
921 pinctrl-1 = <&blsp1_i2c2_default>;
922 #address-cells = <1>;
927 blsp1_i2c4: i2c@78b8000 {
928 compatible = "qcom,i2c-qup-v2.2.1";
929 reg = <0x078b8000 0x500>;
930 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
932 clock-names = "core", "iface";
933 clock-frequency = <400000>;
934 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
935 dma-names = "tx", "rx";
936 pinctrl-names = "default", "sleep";
937 pinctrl-0 = <&blsp1_i2c4_default>;
938 pinctrl-1 = <&blsp1_i2c4_sleep>;
939 #address-cells = <1>;
945 compatible = "qcom,ci-hdrc";
946 reg = <0x078db000 0x200>,
948 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&gcc GCC_USB_HS_AHB_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>;
951 clock-names = "iface", "core";
952 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
953 assigned-clock-rates = <80000000>;
954 resets = <&gcc RST_USB_HS_BCR>;
955 reset-names = "core";
956 ahb-burst-config = <0>;
957 dr_mode = "peripheral";
959 phy-names = "usb-phy";
960 phys = <&usb_hs_phy>;
965 sdhc_3: mmc@7a24900 {
966 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
967 reg = <0x07a24900 0x11c>, <0x07a24000 0x800>;
968 reg-names = "hc", "core";
970 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
972 interrupt-names = "hc_irq", "pwr_irq";
974 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
975 <&gcc GCC_SDCC3_APPS_CLK>,
976 <&rpmcc RPM_SMD_XO_CLK_SRC>;
977 clock-names = "iface", "core", "xo";
982 blsp2_dma: dma-controller@7ac4000 {
983 compatible = "qcom,bam-v1.7.0";
984 reg = <0x07ac4000 0x1f000>;
985 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
987 clock-names = "bam_clk";
992 blsp2_uart2: serial@7af0000 {
993 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
994 reg = <0x07af0000 0x200>;
995 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
997 clock-names = "core", "iface";
998 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
999 dma-names = "tx", "rx";
1000 status = "disabled";
1003 blsp2_i2c2: i2c@7af6000 {
1004 compatible = "qcom,i2c-qup-v2.2.1";
1005 reg = <0x07af6000 0x600>;
1006 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1008 clock-names = "core", "iface";
1009 clock-frequency = <400000>;
1010 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1011 dma-names = "tx", "rx";
1012 pinctrl-names = "default", "sleep";
1013 pinctrl-0 = <&blsp2_i2c2_default>;
1014 pinctrl-1 = <&blsp2_i2c2_sleep>;
1015 #address-cells = <1>;
1017 status = "disabled";
1020 blsp2_i2c4: i2c@7af8000 {
1021 compatible = "qcom,i2c-qup-v2.2.1";
1022 reg = <0x07af8000 0x600>;
1023 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1025 clock-names = "core", "iface";
1026 clock-frequency = <400000>;
1027 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1028 dma-names = "tx", "rx";
1029 pinctrl-names = "default", "sleep";
1030 pinctrl-0 = <&blsp2_i2c4_default>;
1031 pinctrl-1 = <&blsp2_i2c4_sleep>;
1032 #address-cells = <1>;
1034 status = "disabled";
1037 intc: interrupt-controller@b000000 {
1038 compatible = "qcom,msm-qgic2";
1039 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1040 interrupt-controller;
1041 #interrupt-cells = <3>;
1044 apcs: mailbox@b011000 {
1045 compatible = "qcom,msm8976-apcs-kpss-global",
1046 "qcom,msm8994-apcs-kpss-global", "syscon";
1047 reg = <0x0b011000 0x1000>;
1052 compatible = "arm,armv7-timer-mem";
1053 reg = <0x0b120000 0x1000>;
1054 #address-cells = <1>;
1057 clock-frequency = <19200000>;
1060 reg = <0x0b121000 0x1000>, <0x0b122000 0x1000>;
1061 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1067 reg = <0x0b123000 0x1000>;
1068 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1070 status = "disabled";
1074 reg = <0x0b124000 0x1000>;
1075 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1077 status = "disabled";
1081 reg = <0x0b125000 0x1000>;
1082 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1084 status = "disabled";
1088 reg = <0x0b126000 0x1000>;
1089 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1091 status = "disabled";
1095 reg = <0x0b127000 0x1000>;
1096 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1098 status = "disabled";
1102 reg = <0x0b128000 0x1000>;
1103 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1105 status = "disabled";
1109 imem: sram@8600000 {
1110 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
1111 reg = <0x08600000 0x1000>;
1112 #address-cells = <1>;
1115 ranges = <0 0x08600000 0x1000>;
1118 compatible = "qcom,pil-reloc-info";
1126 polling-delay-passive = <250>;
1127 polling-delay = <1000>;
1129 thermal-sensors = <&tsens 0>;
1132 aoss0_alert0: trip-point0 {
1133 temperature = <75000>;
1134 hysteresis = <2000>;
1141 polling-delay-passive = <250>;
1142 polling-delay = <1000>;
1144 thermal-sensors = <&tsens 1>;
1146 modem_alert0: trip-point0 {
1147 temperature = <75000>;
1148 hysteresis = <2000>;
1155 polling-delay-passive = <250>;
1156 polling-delay = <1000>;
1158 thermal-sensors = <&tsens 2>;
1160 qdsp_alert0: trip-point0 {
1161 temperature = <75000>;
1162 hysteresis = <2000>;
1169 polling-delay-passive = <250>;
1170 polling-delay = <1000>;
1172 thermal-sensors = <&tsens 3>;
1174 cam_isp_alert0: trip-point0 {
1175 temperature = <75000>;
1176 hysteresis = <2000>;
1183 polling-delay-passive = <250>;
1184 polling-delay = <1000>;
1185 thermal-sensors = <&tsens 4>;
1188 cpu4_alert0: trip-point0 {
1189 temperature = <50000>;
1190 hysteresis = <2000>;
1193 cpu4_alert1: trip-point1 {
1194 temperature = <55000>;
1195 hysteresis = <2000>;
1198 cpu4_crit: cpu-crit {
1199 temperature = <75000>;
1200 hysteresis = <2000>;
1207 polling-delay-passive = <250>;
1208 polling-delay = <1000>;
1209 thermal-sensors = <&tsens 5>;
1212 cpu5_alert0: trip-point0 {
1213 temperature = <50000>;
1214 hysteresis = <2000>;
1217 cpu5_alert1: trip-point1 {
1218 temperature = <55000>;
1219 hysteresis = <2000>;
1222 cpu5_crit: cpu-crit {
1223 temperature = <75000>;
1224 hysteresis = <2000>;
1231 polling-delay-passive = <250>;
1232 polling-delay = <1000>;
1233 thermal-sensors = <&tsens 6>;
1236 cpu6_alert0: trip-point0 {
1237 temperature = <50000>;
1238 hysteresis = <2000>;
1241 cpu6_alert1: trip-point1 {
1242 temperature = <55000>;
1243 hysteresis = <2000>;
1246 cpu6_crit: cpu-crit {
1247 temperature = <75000>;
1248 hysteresis = <2000>;
1255 polling-delay-passive = <250>;
1256 polling-delay = <1000>;
1257 thermal-sensors = <&tsens 7>;
1260 cpu7_alert0: trip-point0 {
1261 temperature = <50000>;
1262 hysteresis = <2000>;
1265 cpu7_alert1: trip-point1 {
1266 temperature = <55000>;
1267 hysteresis = <2000>;
1270 cpu7_crit: cpu-crit {
1271 temperature = <75000>;
1272 hysteresis = <2000>;
1279 polling-delay-passive = <250>;
1280 polling-delay = <1000>;
1281 thermal-sensors = <&tsens 8>;
1284 l2_alert0: trip-point0 {
1285 temperature = <50000>;
1286 hysteresis = <2000>;
1289 l2_alert1: trip-point1 {
1290 temperature = <55000>;
1291 hysteresis = <2000>;
1295 temperature = <75000>;
1296 hysteresis = <2000>;
1303 polling-delay-passive = <250>;
1304 polling-delay = <1000>;
1305 thermal-sensors = <&tsens 9>;
1308 cpu0_alert0: trip-point0 {
1309 temperature = <50000>;
1310 hysteresis = <2000>;
1313 cpu0_alert1: trip-point1 {
1314 temperature = <55000>;
1315 hysteresis = <2000>;
1318 cpu0_crit: cpu-crit {
1319 temperature = <75000>;
1320 hysteresis = <2000>;
1327 polling-delay-passive = <250>;
1328 polling-delay = <1000>;
1329 thermal-sensors = <&tsens 10>;
1332 gpu_alert0: trip-point0 {
1333 temperature = <50000>;
1334 hysteresis = <2000>;
1337 gpu_alert1: trip-point1 {
1338 temperature = <55000>;
1339 hysteresis = <2000>;
1342 gpu_crit: gpu-crit {
1343 temperature = <75000>;
1344 hysteresis = <2000>;
1352 compatible = "arm,armv8-timer";
1353 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1354 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1355 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1356 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1357 clock-frequency = <19200000>;