arch/arm64/boot/dts/qcom/msm8939.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2020-2023, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8939.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         /*
  19          * Stock LK wants address-cells/size-cells = 2
  20          * A number of our drivers want address/size cells = 1
  21          * hence the disparity between top-level and /soc below.
  22          */
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <19200000>;
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <32768>;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <1>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@100 {
  45                         compatible = "arm,cortex-a53";
  46                         device_type = "cpu";
  47                         enable-method = "spin-table";
  48                         reg = <0x100>;
  49                         next-level-cache = <&L2_1>;
  50                         qcom,acc = <&acc0>;
  51                         qcom,saw = <&saw0>;
  52                         cpu-idle-states = <&CPU_SLEEP_0>;
  53                         clocks = <&apcs1_mbox>;
  54                         #cooling-cells = <2>;
  55                         L2_1: l2-cache {
  56                                 compatible = "cache";
  57                                 cache-level = <2>;
  58                                 cache-unified;
  59                         };
  60                 };
  61
  62                 CPU1: cpu@101 {
  63                         compatible = "arm,cortex-a53";
  64                         device_type = "cpu";
  65                         enable-method = "spin-table";
  66                         reg = <0x101>;
  67                         next-level-cache = <&L2_1>;
  68                         qcom,acc = <&acc1>;
  69                         qcom,saw = <&saw1>;
  70                         cpu-idle-states = <&CPU_SLEEP_0>;
  71                         clocks = <&apcs1_mbox>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 CPU2: cpu@102 {
  76                         compatible = "arm,cortex-a53";
  77                         device_type = "cpu";
  78                         enable-method = "spin-table";
  79                         reg = <0x102>;
  80                         next-level-cache = <&L2_1>;
  81                         qcom,acc = <&acc2>;
  82                         qcom,saw = <&saw2>;
  83                         cpu-idle-states = <&CPU_SLEEP_0>;
  84                         clocks = <&apcs1_mbox>;
  85                         #cooling-cells = <2>;
  86                 };
  87
  88                 CPU3: cpu@103 {
  89                         compatible = "arm,cortex-a53";
  90                         device_type = "cpu";
  91                         enable-method = "spin-table";
  92                         reg = <0x103>;
  93                         next-level-cache = <&L2_1>;
  94                         qcom,acc = <&acc3>;
  95                         qcom,saw = <&saw3>;
  96                         cpu-idle-states = <&CPU_SLEEP_0>;
  97                         clocks = <&apcs1_mbox>;
  98                         #cooling-cells = <2>;
  99                 };
 100
 101                 CPU4: cpu@0 {
 102                         compatible = "arm,cortex-a53";
 103                         device_type = "cpu";
 104                         enable-method = "spin-table";
 105                         reg = <0x0>;
 106                         qcom,acc = <&acc4>;
 107                         qcom,saw = <&saw4>;
 108                         cpu-idle-states = <&CPU_SLEEP_0>;
 109                         clocks = <&apcs0_mbox>;
 110                         #cooling-cells = <2>;
 111                         next-level-cache = <&L2_0>;
 112                         L2_0: l2-cache {
 113                                 compatible = "cache";
 114                                 cache-level = <2>;
 115                                 cache-unified;
 116                         };
 117                 };
 118
 119                 CPU5: cpu@1 {
 120                         compatible = "arm,cortex-a53";
 121                         device_type = "cpu";
 122                         enable-method = "spin-table";
 123                         reg = <0x1>;
 124                         next-level-cache = <&L2_0>;
 125                         qcom,acc = <&acc5>;
 126                         qcom,saw = <&saw5>;
 127                         cpu-idle-states = <&CPU_SLEEP_0>;
 128                         clocks = <&apcs0_mbox>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 CPU6: cpu@2 {
 133                         compatible = "arm,cortex-a53";
 134                         device_type = "cpu";
 135                         enable-method = "spin-table";
 136                         reg = <0x2>;
 137                         next-level-cache = <&L2_0>;
 138                         qcom,acc = <&acc6>;
 139                         qcom,saw = <&saw6>;
 140                         cpu-idle-states = <&CPU_SLEEP_0>;
 141                         clocks = <&apcs0_mbox>;
 142                         #cooling-cells = <2>;
 143                 };
 144
 145                 CPU7: cpu@3 {
 146                         compatible = "arm,cortex-a53";
 147                         device_type = "cpu";
 148                         enable-method = "spin-table";
 149                         reg = <0x3>;
 150                         next-level-cache = <&L2_0>;
 151                         qcom,acc = <&acc7>;
 152                         qcom,saw = <&saw7>;
 153                         cpu-idle-states = <&CPU_SLEEP_0>;
 154                         clocks = <&apcs0_mbox>;
 155                         #cooling-cells = <2>;
 156                 };
 157
 158                 idle-states {
 159                         CPU_SLEEP_0: cpu-sleep-0 {
 160                                 compatible = "arm,idle-state";
 161                                 entry-latency-us = <130>;
 162                                 exit-latency-us = <150>;
 163                                 min-residency-us = <2000>;
 164                                 local-timer-stop;
 165                         };
 166                 };
 167         };
 168
 169         /*
 170          * MSM8939 has a big.LITTLE heterogeneous computing architecture,
 171          * consisting of two clusters of four ARM Cortex-A53s each. The
 172          * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
 173          * at 1.5-1.7GHz.
 174          *
 175          * The enable method used here is spin-table which presupposes use
 176          * of a 2nd stage boot shim such as lk2nd to have installed a
 177          * spin-table, the downstream non-psci/non-spin-table method that
 178          * default msm8916/msm8936/msm8939 will not be supported upstream.
 179          */
 180         cpu-map {
 181                 /* LITTLE (efficiency) cluster */
 182                 cluster0 {
 183                         core0 {
 184                                 cpu = <&CPU4>;
 185                         };
 186
 187                         core1 {
 188                                 cpu = <&CPU5>;
 189                         };
 190
 191                         core2 {
 192                                 cpu = <&CPU6>;
 193                         };
 194
 195                         core3 {
 196                                 cpu = <&CPU7>;
 197                         };
 198                 };
 199
 200                 /* big (performance) cluster */
 201                 /* Boot CPU is cluster 1 core 0 */
 202                 cluster1 {
 203                         core0 {
 204                                 cpu = <&CPU0>;
 205                         };
 206
 207                         core1 {
 208                                 cpu = <&CPU1>;
 209                         };
 210
 211                         core2 {
 212                                 cpu = <&CPU2>;
 213                         };
 214
 215                         core3 {
 216                                 cpu = <&CPU3>;
 217                         };
 218                 };
 219         };
 220
 221         firmware {
 222                 scm: scm {
 223                         compatible = "qcom,scm-msm8916", "qcom,scm";
 224                         clocks = <&gcc GCC_CRYPTO_CLK>,
 225                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 226                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 227                         clock-names = "core", "bus", "iface";
 228                         #reset-cells = <1>;
 229
 230                         qcom,dload-mode = <&tcsr 0x6100>;
 231                 };
 232         };
 233
 234         memory@80000000 {
 235                 device_type = "memory";
 236                 /* We expect the bootloader to fill in the reg */
 237                 reg = <0x0 0x80000000 0x0 0x0>;
 238         };
 239
 240         pmu {
 241                 compatible = "arm,cortex-a53-pmu";
 242                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 243         };
 244
 245         rpm: remoteproc {
 246                 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc";
 247
 248                 smd-edge {
 249                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 250                         qcom,ipc = <&apcs1_mbox 8 0>;
 251                         qcom,smd-edge = <15>;
 252
 253                         rpm_requests: rpm-requests {
 254                                 compatible = "qcom,rpm-msm8936";
 255                                 qcom,smd-channels = "rpm_requests";
 256
 257                                 rpmcc: clock-controller {
 258                                         compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
 259                                         #clock-cells = <1>;
 260                                         clock-names = "xo";
 261                                         clocks = <&xo_board>;
 262                                 };
 263
 264                                 rpmpd: power-controller {
 265                                         compatible = "qcom,msm8939-rpmpd";
 266                                         #power-domain-cells = <1>;
 267                                         operating-points-v2 = <&rpmpd_opp_table>;
 268
 269                                         rpmpd_opp_table: opp-table {
 270                                                 compatible = "operating-points-v2";
 271
 272                                                 rpmpd_opp_ret: opp1 {
 273                                                         opp-level = <1>;
 274                                                 };
 275
 276                                                 rpmpd_opp_svs_krait: opp2 {
 277                                                         opp-level = <2>;
 278                                                 };
 279
 280                                                 rpmpd_opp_svs_soc: opp3 {
 281                                                         opp-level = <3>;
 282                                                 };
 283
 284                                                 rpmpd_opp_nom: opp4 {
 285                                                         opp-level = <4>;
 286                                                 };
 287
 288                                                 rpmpd_opp_turbo: opp5 {
 289                                                         opp-level = <5>;
 290                                                 };
 291
 292                                                 rpmpd_opp_super_turbo: opp6 {
 293                                                         opp-level = <6>;
 294                                                 };
 295                                         };
 296                                 };
 297                         };
 298                 };
 299         };
 300
 301         reserved-memory {
 302                 #address-cells = <2>;
 303                 #size-cells = <2>;
 304                 ranges;
 305
 306                 tz-apps@86000000 {
 307                         reg = <0x0 0x86000000 0x0 0x300000>;
 308                         no-map;
 309                 };
 310
 311                 smem@86300000 {
 312                         compatible = "qcom,smem";
 313                         reg = <0x0 0x86300000 0x0 0x100000>;
 314                         no-map;
 315
 316                         hwlocks = <&tcsr_mutex 3>;
 317                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 318                 };
 319
 320                 hypervisor@86400000 {
 321                         reg = <0x0 0x86400000 0x0 0x100000>;
 322                         no-map;
 323                 };
 324
 325                 tz@86500000 {
 326                         reg = <0x0 0x86500000 0x0 0x180000>;
 327                         no-map;
 328                 };
 329
 330                 reserved@86680000 {
 331                         reg = <0x0 0x86680000 0x0 0x80000>;
 332                         no-map;
 333                 };
 334
 335                 rmtfs@86700000 {
 336                         compatible = "qcom,rmtfs-mem";
 337                         reg = <0x0 0x86700000 0x0 0xe0000>;
 338                         no-map;
 339
 340                         qcom,client-id = <1>;
 341                 };
 342
 343                 rfsa@867e0000 {
 344                         reg = <0x0 0x867e0000 0x0 0x20000>;
 345                         no-map;
 346                 };
 347
 348                 mpss_mem: mpss@86800000 {
 349                         /*
 350                          * The memory region for the mpss firmware is generally
 351                          * relocatable and could be allocated dynamically.
 352                          * However, many firmware versions tend to fail when
 353                          * loaded to some special addresses, so it is hard to
 354                          * define reliable alloc-ranges.
 355                          *
 356                          * alignment = <0x0 0x400000>;
 357                          * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 358                          */
 359                         reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
 360                         no-map;
 361                         status = "disabled";
 362                 };
 363
 364                 wcnss_mem: wcnss {
 365                         size = <0x0 0x600000>;
 366                         alignment = <0x0 0x100000>;
 367                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 368                         no-map;
 369                         status = "disabled";
 370                 };
 371
 372                 venus_mem: venus {
 373                         size = <0x0 0x500000>;
 374                         alignment = <0x0 0x100000>;
 375                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 376                         no-map;
 377                         status = "disabled";
 378                 };
 379
 380                 mba_mem: mba {
 381                         size = <0x0 0x100000>;
 382                         alignment = <0x0 0x100000>;
 383                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 384                         no-map;
 385                         status = "disabled";
 386                 };
 387         };
 388
 389         smp2p-hexagon {
 390                 compatible = "qcom,smp2p";
 391                 qcom,smem = <435>, <428>;
 392
 393                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 394
 395                 mboxes = <&apcs1_mbox 14>;
 396
 397                 qcom,local-pid = <0>;
 398                 qcom,remote-pid = <1>;
 399
 400                 hexagon_smp2p_out: master-kernel {
 401                         qcom,entry-name = "master-kernel";
 402
 403                         #qcom,smem-state-cells = <1>;
 404                 };
 405
 406                 hexagon_smp2p_in: slave-kernel {
 407                         qcom,entry-name = "slave-kernel";
 408
 409                         interrupt-controller;
 410                         #interrupt-cells = <2>;
 411                 };
 412         };
 413
 414         smp2p-wcnss {
 415                 compatible = "qcom,smp2p";
 416                 qcom,smem = <451>, <431>;
 417
 418                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 419
 420                 mboxes = <&apcs1_mbox 18>;
 421
 422                 qcom,local-pid = <0>;
 423                 qcom,remote-pid = <4>;
 424
 425                 wcnss_smp2p_in: slave-kernel {
 426                         qcom,entry-name = "slave-kernel";
 427
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                 };
 431
 432                 wcnss_smp2p_out: master-kernel {
 433                         qcom,entry-name = "master-kernel";
 434
 435                         #qcom,smem-state-cells = <1>;
 436                 };
 437         };
 438
 439         smsm {
 440                 compatible = "qcom,smsm";
 441
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444
 445                 qcom,ipc-1 = <&apcs1_mbox 8 13>;
 446                 qcom,ipc-3 = <&apcs1_mbox 8 19>;
 447
 448                 apps_smsm: apps@0 {
 449                         reg = <0>;
 450
 451                         #qcom,smem-state-cells = <1>;
 452                 };
 453
 454                 hexagon_smsm: hexagon@1 {
 455                         reg = <1>;
 456                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 457
 458                         interrupt-controller;
 459                         #interrupt-cells = <2>;
 460                 };
 461
 462                 wcnss_smsm: wcnss@6 {
 463                         reg = <6>;
 464                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 465
 466                         interrupt-controller;
 467                         #interrupt-cells = <2>;
 468                 };
 469         };
 470
 471         soc: soc@0 {
 472                 compatible = "simple-bus";
 473                 #address-cells = <1>;
 474                 #size-cells = <1>;
 475                 ranges = <0 0 0 0xffffffff>;
 476
 477                 rng@22000 {
 478                         compatible = "qcom,prng";
 479                         reg = <0x00022000 0x200>;
 480                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 481                         clock-names = "core";
 482                 };
 483
 484                 qfprom: qfprom@5c000 {
 485                         compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
 486                         reg = <0x0005c000 0x1000>;
 487                         #address-cells = <1>;
 488                         #size-cells = <1>;
 489
 490                         tsens_base1: base1@a0 {
 491                                 reg = <0xa0 0x1>;
 492                                 bits = <0 8>;
 493                         };
 494
 495                         tsens_s6_p1: s6-p1@a1 {
 496                                 reg = <0xa1 0x1>;
 497                                 bits = <0 6>;
 498                         };
 499
 500                         tsens_s6_p2: s6-p2@a1 {
 501                                 reg = <0xa1 0x2>;
 502                                 bits = <6 6>;
 503                         };
 504
 505                         tsens_s7_p1: s7-p1@a2 {
 506                                 reg = <0xa2 0x2>;
 507                                 bits = <4 6>;
 508                         };
 509
 510                         tsens_s7_p2: s7-p2@a3 {
 511                                 reg = <0xa3 0x1>;
 512                                 bits = <2 6>;
 513                         };
 514
 515                         tsens_s8_p1: s8-p1@a4 {
 516                                 reg = <0xa4 0x1>;
 517                                 bits = <0 6>;
 518                         };
 519
 520                         tsens_s8_p2: s8-p2@a4 {
 521                                 reg = <0xa4 0x2>;
 522                                 bits = <6 6>;
 523                         };
 524
 525                         tsens_s9_p1: s9-p1@a5 {
 526                                 reg = <0xa5 0x2>;
 527                                 bits = <4 6>;
 528                         };
 529
 530                         tsens_s9_p2: s9-p2@a6 {
 531                                 reg = <0xa6 0x1>;
 532                                 bits = <2 6>;
 533                         };
 534
 535                         tsens_base2: base2@a7 {
 536                                 reg = <0xa7 0x1>;
 537                                 bits = <0 8>;
 538                         };
 539
 540                         tsens_mode: mode@d0 {
 541                                 reg = <0xd0 0x1>;
 542                                 bits = <0 3>;
 543                         };
 544
 545                         tsens_s0_p1: s0-p1@d0 {
 546                                 reg = <0xd0 0x2>;
 547                                 bits = <3 6>;
 548                         };
 549
 550                         tsens_s0_p2: s0-p1@d1 {
 551                                 reg = <0xd1 0x1>;
 552                                 bits = <1 6>;
 553                         };
 554
 555                         tsens_s1_p1: s1-p1@d1 {
 556                                 reg = <0xd1 0x2>;
 557                                 bits = <7 6>;
 558                         };
 559
 560                         tsens_s1_p2: s1-p2@d2 {
 561                                 reg = <0xd2 0x2>;
 562                                 bits = <5 6>;
 563                         };
 564
 565                         tsens_s2_p1: s2-p1@d3 {
 566                                 reg = <0xd3 0x2>;
 567                                 bits = <3 6>;
 568                         };
 569
 570                         tsens_s2_p2: s2-p2@d4 {
 571                                 reg = <0xd4 0x1>;
 572                                 bits = <1 6>;
 573                         };
 574
 575                         tsens_s3_p1: s3-p1@d4 {
 576                                 reg = <0xd4 0x2>;
 577                                 bits = <7 6>;
 578                         };
 579
 580                         tsens_s3_p2: s3-p2@d5 {
 581                                 reg = <0xd5 0x2>;
 582                                 bits = <5 6>;
 583                         };
 584
 585                         tsens_s5_p1: s5-p1@d6 {
 586                                 reg = <0xd6 0x2>;
 587                                 bits = <3 6>;
 588                         };
 589
 590                         tsens_s5_p2: s5-p2@d7 {
 591                                 reg = <0xd7 0x1>;
 592                                 bits = <1 6>;
 593                         };
 594                 };
 595
 596                 rpm_msg_ram: sram@60000 {
 597                         compatible = "qcom,rpm-msg-ram";
 598                         reg = <0x00060000 0x8000>;
 599                 };
 600
 601                 bimc: interconnect@400000 {
 602                         compatible = "qcom,msm8939-bimc";
 603                         reg = <0x00400000 0x62000>;
 604                         clock-names = "bus", "bus_a";
 605                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 606                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 607                         #interconnect-cells = <1>;
 608                 };
 609
 610                 tsens: thermal-sensor@4a9000 {
 611                         compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
 612                         reg = <0x004a9000 0x1000>, /* TM */
 613                               <0x004a8000 0x1000>; /* SROT */
 614                         nvmem-cells = <&tsens_mode>,
 615                                       <&tsens_base1>, <&tsens_base2>,
 616                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
 617                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
 618                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
 619                                       <&tsens_s3_p1>, <&tsens_s3_p2>,
 620                                       <&tsens_s5_p1>, <&tsens_s5_p2>,
 621                                       <&tsens_s6_p1>, <&tsens_s6_p2>,
 622                                       <&tsens_s7_p1>, <&tsens_s7_p2>,
 623                                       <&tsens_s8_p1>, <&tsens_s8_p2>,
 624                                       <&tsens_s9_p1>, <&tsens_s9_p2>;
 625                         nvmem-cell-names = "mode",
 626                                            "base1", "base2",
 627                                            "s0_p1", "s0_p2",
 628                                            "s1_p1", "s1_p2",
 629                                            "s2_p1", "s2_p2",
 630                                            "s3_p1", "s3_p2",
 631                                            "s5_p1", "s5_p2",
 632                                            "s6_p1", "s6_p2",
 633                                            "s7_p1", "s7_p2",
 634                                            "s8_p1", "s8_p2",
 635                                            "s9_p1", "s9_p2";
 636                         #qcom,sensors = <9>;
 637                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 638                         interrupt-names = "uplow";
 639                         #thermal-sensor-cells = <1>;
 640                 };
 641
 642                 restart@4ab000 {
 643                         compatible = "qcom,pshold";
 644                         reg = <0x004ab000 0x4>;
 645                 };
 646
 647                 pcnoc: interconnect@500000 {
 648                         compatible = "qcom,msm8939-pcnoc";
 649                         reg = <0x00500000 0x11000>;
 650                         clock-names = "bus", "bus_a";
 651                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
 652                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
 653                         #interconnect-cells = <1>;
 654                 };
 655
 656                 snoc: interconnect@580000 {
 657                         compatible = "qcom,msm8939-snoc";
 658                         reg = <0x00580000 0x14080>;
 659                         clock-names = "bus", "bus_a";
 660                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 661                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 662                         #interconnect-cells = <1>;
 663
 664                         snoc_mm: interconnect-snoc {
 665                                 compatible = "qcom,msm8939-snoc-mm";
 666                                 clock-names = "bus", "bus_a";
 667                                 clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>,
 668                                          <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>;
 669                                 #interconnect-cells = <1>;
 670                         };
 671                 };
 672
 673                 tlmm: pinctrl@1000000 {
 674                         compatible = "qcom,msm8916-pinctrl";
 675                         reg = <0x01000000 0x300000>;
 676                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 677                         gpio-controller;
 678                         gpio-ranges = <&tlmm 0 0 122>;
 679                         #gpio-cells = <2>;
 680                         interrupt-controller;
 681                         #interrupt-cells = <2>;
 682
 683                         blsp_i2c1_default: blsp-i2c1-default-state {
 684                                 pins = "gpio2", "gpio3";
 685                                 function = "blsp_i2c1";
 686                                 drive-strength = <2>;
 687                                 bias-disable;
 688                         };
 689
 690                         blsp_i2c1_sleep: blsp-i2c1-sleep-state {
 691                                 pins = "gpio2", "gpio3";
 692                                 function = "gpio";
 693                                 drive-strength = <2>;
 694                                 bias-disable;
 695                         };
 696
 697                         blsp_i2c2_default: blsp-i2c2-default-state {
 698                                 pins = "gpio6", "gpio7";
 699                                 function = "blsp_i2c2";
 700                                 drive-strength = <2>;
 701                                 bias-disable;
 702                         };
 703
 704                         blsp_i2c2_sleep: blsp-i2c2-sleep-state {
 705                                 pins = "gpio6", "gpio7";
 706                                 function = "gpio";
 707                                 drive-strength = <2>;
 708                                 bias-disable;
 709                         };
 710
 711                         blsp_i2c3_default: blsp-i2c3-default-state {
 712                                 pins = "gpio10", "gpio11";
 713                                 function = "blsp_i2c3";
 714                                 drive-strength = <2>;
 715                                 bias-disable;
 716                         };
 717
 718                         blsp_i2c3_sleep: blsp-i2c3-sleep-state {
 719                                 pins = "gpio10", "gpio11";
 720                                 function = "gpio";
 721                                 drive-strength = <2>;
 722                                 bias-disable;
 723                         };
 724
 725                         blsp_i2c4_default: blsp-i2c4-default-state {
 726                                 pins = "gpio14", "gpio15";
 727                                 function = "blsp_i2c4";
 728                                 drive-strength = <2>;
 729                                 bias-disable;
 730                         };
 731
 732                         blsp_i2c4_sleep: blsp-i2c4-sleep-state {
 733                                 pins = "gpio14", "gpio15";
 734                                 function = "gpio";
 735                                 drive-strength = <2>;
 736                                 bias-disable;
 737                         };
 738
 739                         blsp_i2c5_default: blsp-i2c5-default-state {
 740                                 pins = "gpio18", "gpio19";
 741                                 function = "blsp_i2c5";
 742                                 drive-strength = <2>;
 743                                 bias-disable;
 744                         };
 745
 746                         blsp_i2c5_sleep: blsp-i2c5-sleep-state {
 747                                 pins = "gpio18", "gpio19";
 748                                 function = "gpio";
 749                                 drive-strength = <2>;
 750                                 bias-disable;
 751                         };
 752
 753                         blsp_i2c6_default: blsp-i2c6-default-state {
 754                                 pins = "gpio22", "gpio23";
 755                                 function = "blsp_i2c6";
 756                                 drive-strength = <2>;
 757                                 bias-disable;
 758                         };
 759
 760                         blsp_i2c6_sleep: blsp-i2c6-sleep-state {
 761                                 pins = "gpio22", "gpio23";
 762                                 function = "gpio";
 763                                 drive-strength = <2>;
 764                                 bias-disable;
 765                         };
 766
 767                         blsp_spi1_default: blsp-spi1-default-state {
 768                                 spi-pins {
 769                                         pins = "gpio0", "gpio1", "gpio3";
 770                                         function = "blsp_spi1";
 771                                         drive-strength = <12>;
 772                                         bias-disable;
 773                                 };
 774
 775                                 cs-pins {
 776                                         pins = "gpio2";
 777                                         function = "gpio";
 778                                         drive-strength = <16>;
 779                                         bias-disable;
 780                                         output-high;
 781                                 };
 782                         };
 783
 784                         blsp_spi1_sleep: blsp-spi1-sleep-state {
 785                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 786                                 function = "gpio";
 787                                 drive-strength = <2>;
 788                                 bias-pull-down;
 789                         };
 790
 791                         blsp_spi2_default: blsp-spi2-default-state {
 792                                 spi-pins {
 793                                         pins = "gpio4", "gpio5", "gpio7";
 794                                         function = "blsp_spi2";
 795                                         drive-strength = <12>;
 796                                         bias-disable;
 797                                 };
 798
 799                                 cs-pins {
 800                                         pins = "gpio6";
 801                                         function = "gpio";
 802                                         drive-strength = <16>;
 803                                         bias-disable;
 804                                         output-high;
 805                                 };
 806                         };
 807
 808                         blsp_spi2_sleep: blsp-spi2-sleep-state {
 809                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
 810                                 function = "gpio";
 811                                 drive-strength = <2>;
 812                                 bias-pull-down;
 813                         };
 814
 815                         blsp_spi3_default: blsp-spi3-default-state {
 816                                 spi-pins {
 817                                         pins = "gpio8", "gpio9", "gpio11";
 818                                         function = "blsp_spi3";
 819                                         drive-strength = <12>;
 820                                         bias-disable;
 821                                 };
 822
 823                                 cs-pins {
 824                                         pins = "gpio10";
 825                                         function = "gpio";
 826                                         drive-strength = <16>;
 827                                         bias-disable;
 828                                         output-high;
 829                                 };
 830                         };
 831
 832                         blsp_spi3_sleep: blsp-spi3-sleep-state {
 833                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
 834                                 function = "gpio";
 835                                 drive-strength = <2>;
 836                                 bias-pull-down;
 837                         };
 838
 839                         blsp_spi4_default: blsp-spi4-default-state {
 840                                 spi-pins {
 841                                         pins = "gpio12", "gpio13", "gpio15";
 842                                         function = "blsp_spi4";
 843                                         drive-strength = <12>;
 844                                         bias-disable;
 845                                 };
 846
 847                                 cs-pins {
 848                                         pins = "gpio14";
 849                                         function = "gpio";
 850                                         drive-strength = <16>;
 851                                         bias-disable;
 852                                         output-high;
 853                                 };
 854                         };
 855
 856                         blsp_spi4_sleep: blsp-spi4-sleep-state {
 857                                 pins = "gpio12", "gpio13", "gpio14", "gpio15";
 858                                 function = "gpio";
 859                                 drive-strength = <2>;
 860                                 bias-pull-down;
 861                         };
 862
 863                         blsp_spi5_default: blsp-spi5-default-state {
 864                                 spi-pins {
 865                                         pins = "gpio16", "gpio17", "gpio19";
 866                                         function = "blsp_spi5";
 867                                         drive-strength = <12>;
 868                                         bias-disable;
 869                                 };
 870
 871                                 cs-pins {
 872                                         pins = "gpio18";
 873                                         function = "gpio";
 874                                         drive-strength = <16>;
 875                                         bias-disable;
 876                                         output-high;
 877                                 };
 878                         };
 879
 880                         blsp_spi5_sleep: blsp-spi5-sleep-state {
 881                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
 882                                 function = "gpio";
 883                                 drive-strength = <2>;
 884                                 bias-pull-down;
 885                         };
 886
 887                         blsp_spi6_default: blsp-spi6-default-state {
 888                                 spi-pins {
 889                                         pins = "gpio20", "gpio21", "gpio23";
 890                                         function = "blsp_spi6";
 891                                         drive-strength = <12>;
 892                                         bias-disable;
 893                                 };
 894
 895                                 cs-pins {
 896                                         pins = "gpio22";
 897                                         function = "gpio";
 898                                         drive-strength = <16>;
 899                                         bias-disable;
 900                                         output-high;
 901                                 };
 902                         };
 903
 904                         blsp_spi6_sleep: blsp-spi6-sleep-state {
 905                                 pins = "gpio20", "gpio21", "gpio22", "gpio23";
 906                                 function = "gpio";
 907                                 drive-strength = <2>;
 908                                 bias-pull-down;
 909                         };
 910
 911                         blsp_uart1_default: blsp-uart1-default-state {
 912                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 913                                 function = "blsp_uart1";
 914                                 drive-strength = <16>;
 915                                 bias-disable;
 916                         };
 917
 918                         blsp_uart1_sleep: blsp-uart1-sleep-state {
 919                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 920                                 function = "gpio";
 921                                 drive-strength = <2>;
 922                                 bias-pull-down;
 923                         };
 924
 925                         blsp_uart2_default: blsp-uart2-default-state {
 926                                 pins = "gpio4", "gpio5";
 927                                 function = "blsp_uart2";
 928                                 drive-strength = <16>;
 929                                 bias-disable;
 930                         };
 931
 932                         blsp_uart2_sleep: blsp-uart2-sleep-state {
 933                                 pins = "gpio4", "gpio5";
 934                                 function = "gpio";
 935                                 drive-strength = <2>;
 936                                 bias-pull-down;
 937                         };
 938
 939                         camera_front_default: camera-front-default-state {
 940                                 pwdn-pins {
 941                                         pins = "gpio33";
 942                                         function = "gpio";
 943                                         drive-strength = <16>;
 944                                         bias-disable;
 945                                 };
 946
 947                                 rst-pins {
 948                                         pins = "gpio28";
 949                                         function = "gpio";
 950                                         drive-strength = <16>;
 951                                         bias-disable;
 952                                 };
 953
 954                                 mclk1-pins {
 955                                         pins = "gpio27";
 956                                         function = "cam_mclk1";
 957                                         drive-strength = <16>;
 958                                         bias-disable;
 959                                 };
 960                         };
 961
 962                         camera_rear_default: camera-rear-default-state {
 963                                 pwdn-pins {
 964                                         pins = "gpio34";
 965                                         function = "gpio";
 966                                         drive-strength = <16>;
 967                                         bias-disable;
 968                                 };
 969
 970                                 rst-pins {
 971                                         pins = "gpio35";
 972                                         function = "gpio";
 973                                         drive-strength = <16>;
 974                                         bias-disable;
 975                                 };
 976
 977                                 mclk0-pins {
 978                                         pins = "gpio26";
 979                                         function = "cam_mclk0";
 980                                         drive-strength = <16>;
 981                                         bias-disable;
 982                                 };
 983                         };
 984
 985                         cci0_default: cci0-default-state {
 986                                 pins = "gpio29", "gpio30";
 987                                 function = "cci_i2c";
 988                                 drive-strength = <16>;
 989                                 bias-disable;
 990                         };
 991
 992                         cdc_dmic_default: cdc-dmic-default-state {
 993                                 clk-pins {
 994                                         pins = "gpio0";
 995                                         function = "dmic0_clk";
 996                                         drive-strength = <8>;
 997                                 };
 998
 999                                 data-pins {
1000                                         pins = "gpio1";
1001                                         function = "dmic0_data";
1002                                         drive-strength = <8>;
1003                                 };
1004                         };
1005
1006                         cdc_dmic_sleep: cdc-dmic-sleep-state {
1007                                 clk-pins {
1008                                         pins = "gpio0";
1009                                         function = "dmic0_clk";
1010                                         drive-strength = <2>;
1011                                         bias-disable;
1012                                 };
1013
1014                                 data-pins {
1015                                         pins = "gpio1";
1016                                         function = "dmic0_data";
1017                                         drive-strength = <2>;
1018                                         bias-disable;
1019                                 };
1020                         };
1021
1022                         cdc_pdm_default: cdc-pdm-default-state {
1023                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1024                                        "gpio67", "gpio68";
1025                                 function = "cdc_pdm0";
1026                                 drive-strength = <8>;
1027                                 bias-disable;
1028                         };
1029
1030                         cdc_pdm_sleep: cdc-pdm-sleep-state {
1031                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1032                                        "gpio67", "gpio68";
1033                                 function = "cdc_pdm0";
1034                                 drive-strength = <2>;
1035                                 bias-pull-down;
1036                         };
1037
1038                         pri_mi2s_default: mi2s-pri-default-state {
1039                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1040                                 function = "pri_mi2s";
1041                                 drive-strength = <8>;
1042                                 bias-disable;
1043                         };
1044
1045                         pri_mi2s_sleep: mi2s-pri-sleep-state {
1046                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1047                                 function = "pri_mi2s";
1048                                 drive-strength = <2>;
1049                                 bias-disable;
1050                         };
1051
1052                         pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1053                                 pins = "gpio116";
1054                                 function = "pri_mi2s";
1055                                 drive-strength = <8>;
1056                                 bias-disable;
1057                         };
1058
1059                         pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1060                                 pins = "gpio116";
1061                                 function = "pri_mi2s";
1062                                 drive-strength = <2>;
1063                                 bias-disable;
1064                         };
1065
1066                         pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1067                                 pins = "gpio110";
1068                                 function = "pri_mi2s_ws";
1069                                 drive-strength = <8>;
1070                                 bias-disable;
1071                         };
1072
1073                         pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1074                                 pins = "gpio110";
1075                                 function = "pri_mi2s_ws";
1076                                 drive-strength = <2>;
1077                                 bias-disable;
1078                         };
1079
1080                         sec_mi2s_default: mi2s-sec-default-state {
1081                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1082                                 function = "sec_mi2s";
1083                                 drive-strength = <8>;
1084                                 bias-disable;
1085                         };
1086
1087                         sec_mi2s_sleep: mi2s-sec-sleep-state {
1088                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1089                                 function = "sec_mi2s";
1090                                 drive-strength = <2>;
1091                                 bias-disable;
1092                         };
1093
1094                         sdc1_default: sdc1-default-state {
1095                                 clk-pins {
1096                                         pins = "sdc1_clk";
1097                                         bias-disable;
1098                                         drive-strength = <16>;
1099                                 };
1100
1101                                 cmd-pins {
1102                                         pins = "sdc1_cmd";
1103                                         bias-pull-up;
1104                                         drive-strength = <10>;
1105                                 };
1106
1107                                 data-pins {
1108                                         pins = "sdc1_data";
1109                                         bias-pull-up;
1110                                         drive-strength = <10>;
1111                                 };
1112                         };
1113
1114                         sdc1_sleep: sdc1-sleep-state {
1115                                 clk-pins {
1116                                         pins = "sdc1_clk";
1117                                         bias-disable;
1118                                         drive-strength = <2>;
1119                                 };
1120
1121                                 cmd-pins {
1122                                         pins = "sdc1_cmd";
1123                                         bias-pull-up;
1124                                         drive-strength = <2>;
1125                                 };
1126
1127                                 data-pins {
1128                                         pins = "sdc1_data";
1129                                         bias-pull-up;
1130                                         drive-strength = <2>;
1131                                 };
1132                         };
1133
1134                         sdc2_default: sdc2-default-state {
1135                                 clk-pins {
1136                                         pins = "sdc2_clk";
1137                                         bias-disable;
1138                                         drive-strength = <16>;
1139                                 };
1140
1141                                 cmd-pins {
1142                                         pins = "sdc2_cmd";
1143                                         bias-pull-up;
1144                                         drive-strength = <10>;
1145                                 };
1146
1147                                 data-pins {
1148                                         pins = "sdc2_data";
1149                                         bias-pull-up;
1150                                         drive-strength = <10>;
1151                                 };
1152                         };
1153
1154                         sdc2_sleep: sdc2-sleep-state {
1155                                 clk-pins {
1156                                         pins = "sdc2_clk";
1157                                         bias-disable;
1158                                         drive-strength = <2>;
1159                                 };
1160
1161                                 cmd-pins {
1162                                         pins = "sdc2_cmd";
1163                                         bias-pull-up;
1164                                         drive-strength = <2>;
1165                                 };
1166
1167                                 data-pins {
1168                                         pins = "sdc2_data";
1169                                         bias-pull-up;
1170                                         drive-strength = <2>;
1171                                 };
1172                         };
1173
1174                         wcss_wlan_default: wcss-wlan-default-state {
1175                                 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1176                                 function = "wcss_wlan";
1177                                 drive-strength = <6>;
1178                                 bias-pull-up;
1179                         };
1180                 };
1181
1182                 gcc: clock-controller@1800000 {
1183                         compatible = "qcom,gcc-msm8939";
1184                         reg = <0x01800000 0x80000>;
1185                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1186                                  <&sleep_clk>,
1187                                  <&mdss_dsi0_phy 1>,
1188                                  <&mdss_dsi0_phy 0>,
1189                                  <0>,
1190                                  <0>,
1191                                  <0>;
1192                         clock-names = "xo",
1193                                       "sleep_clk",
1194                                       "dsi0pll",
1195                                       "dsi0pllbyte",
1196                                       "ext_mclk",
1197                                       "ext_pri_i2s",
1198                                       "ext_sec_i2s";
1199                         #clock-cells = <1>;
1200                         #reset-cells = <1>;
1201                         #power-domain-cells = <1>;
1202                 };
1203
1204                 tcsr_mutex: hwlock@1905000 {
1205                         compatible = "qcom,tcsr-mutex";
1206                         reg = <0x01905000 0x20000>;
1207                         #hwlock-cells = <1>;
1208                 };
1209
1210                 tcsr: syscon@1937000 {
1211                         compatible = "qcom,tcsr-msm8916", "syscon";
1212                         reg = <0x01937000 0x30000>;
1213                 };
1214
1215                 mdss: display-subsystem@1a00000 {
1216                         compatible = "qcom,mdss";
1217                         reg = <0x01a00000 0x1000>,
1218                               <0x01ac8000 0x3000>;
1219                         reg-names = "mdss_phys", "vbif_phys";
1220
1221                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1222                         interrupt-controller;
1223
1224                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
1225                                  <&gcc GCC_MDSS_AXI_CLK>,
1226                                  <&gcc GCC_MDSS_VSYNC_CLK>;
1227                         clock-names = "iface",
1228                                       "bus",
1229                                       "vsync";
1230
1231                         power-domains = <&gcc MDSS_GDSC>;
1232
1233                         #address-cells = <1>;
1234                         #size-cells = <1>;
1235                         #interrupt-cells = <1>;
1236                         ranges;
1237
1238                         status = "disabled";
1239
1240                         mdss_mdp: display-controller@1a01000 {
1241                                 compatible = "qcom,mdp5";
1242                                 reg = <0x01a01000 0x89000>;
1243                                 reg-names = "mdp_phys";
1244
1245                                 interrupt-parent = <&mdss>;
1246                                 interrupts = <0>;
1247
1248                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1249                                          <&gcc GCC_MDSS_AXI_CLK>,
1250                                          <&gcc GCC_MDSS_MDP_CLK>,
1251                                          <&gcc GCC_MDSS_VSYNC_CLK>;
1252                                 clock-names = "iface",
1253                                               "bus",
1254                                               "core",
1255                                               "vsync";
1256
1257                                 iommus = <&apps_iommu 4>;
1258
1259                                 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1260                                                 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
1261                                 interconnect-names = "mdp0-mem", "mdp1-mem";
1262
1263                                 ports {
1264                                         #address-cells = <1>;
1265                                         #size-cells = <0>;
1266
1267                                         port@0 {
1268                                                 reg = <0>;
1269                                                 mdss_mdp_intf1_out: endpoint {
1270                                                         remote-endpoint = <&mdss_dsi0_in>;
1271                                                 };
1272                                         };
1273
1274                                         port@1 {
1275                                                 reg = <1>;
1276                                                 mdss_mdp_intf2_out: endpoint {
1277                                                         remote-endpoint = <&mdss_dsi1_in>;
1278                                                 };
1279                                         };
1280                                 };
1281                         };
1282
1283                         mdss_dsi0: dsi@1a98000 {
1284                                 compatible = "qcom,msm8916-dsi-ctrl",
1285                                              "qcom,mdss-dsi-ctrl";
1286                                 reg = <0x01a98000 0x25c>;
1287                                 reg-names = "dsi_ctrl";
1288
1289                                 interrupt-parent = <&mdss>;
1290                                 interrupts = <4>;
1291
1292                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1293                                          <&gcc GCC_MDSS_AHB_CLK>,
1294                                          <&gcc GCC_MDSS_AXI_CLK>,
1295                                          <&gcc GCC_MDSS_BYTE0_CLK>,
1296                                          <&gcc GCC_MDSS_PCLK0_CLK>,
1297                                          <&gcc GCC_MDSS_ESC0_CLK>;
1298                                 clock-names = "mdp_core",
1299                                               "iface",
1300                                               "bus",
1301                                               "byte",
1302                                               "pixel",
1303                                               "core";
1304                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1305                                                   <&gcc PCLK0_CLK_SRC>;
1306                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1307                                                          <&mdss_dsi0_phy 1>;
1308
1309                                 phys = <&mdss_dsi0_phy>;
1310                                 status = "disabled";
1311
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314
1315                                 ports {
1316                                         #address-cells = <1>;
1317                                         #size-cells = <0>;
1318
1319                                         port@0 {
1320                                                 reg = <0>;
1321                                                 mdss_dsi0_in: endpoint {
1322                                                         remote-endpoint = <&mdss_mdp_intf1_out>;
1323                                                 };
1324                                         };
1325
1326                                         port@1 {
1327                                                 reg = <1>;
1328                                                 mdss_dsi0_out: endpoint {
1329                                                 };
1330                                         };
1331                                 };
1332                         };
1333
1334                         mdss_dsi0_phy: phy@1a98300 {
1335                                 compatible = "qcom,dsi-phy-28nm-lp";
1336                                 reg = <0x01a98300 0xd4>,
1337                                       <0x01a98500 0x280>,
1338                                       <0x01a98780 0x30>;
1339                                 reg-names = "dsi_pll",
1340                                             "dsi_phy",
1341                                             "dsi_phy_regulator";
1342
1343                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1344                                          <&rpmcc RPM_SMD_XO_CLK_SRC>;
1345                                 clock-names = "iface", "ref";
1346
1347                                 #clock-cells = <1>;
1348                                 #phy-cells = <0>;
1349                                 status = "disabled";
1350                         };
1351
1352                         mdss_dsi1: dsi@1aa0000 {
1353                                 compatible = "qcom,msm8916-dsi-ctrl",
1354                                              "qcom,mdss-dsi-ctrl";
1355                                 reg = <0x01aa0000 0x25c>;
1356                                 reg-names = "dsi_ctrl";
1357
1358                                 interrupt-parent = <&mdss>;
1359                                 interrupts = <5>;
1360
1361                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1362                                          <&gcc GCC_MDSS_AHB_CLK>,
1363                                          <&gcc GCC_MDSS_AXI_CLK>,
1364                                          <&gcc GCC_MDSS_BYTE1_CLK>,
1365                                          <&gcc GCC_MDSS_PCLK1_CLK>,
1366                                          <&gcc GCC_MDSS_ESC1_CLK>;
1367                                 clock-names = "mdp_core",
1368                                               "iface",
1369                                               "bus",
1370                                               "byte",
1371                                               "pixel",
1372                                               "core";
1373                                 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
1374                                                   <&gcc PCLK1_CLK_SRC>;
1375                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1376                                                          <&mdss_dsi0_phy 1>;
1377                                 phys = <&mdss_dsi1_phy>;
1378                                 status = "disabled";
1379
1380                                 ports {
1381                                         #address-cells = <1>;
1382                                         #size-cells = <0>;
1383
1384                                         port@0 {
1385                                                 reg = <0>;
1386                                                 mdss_dsi1_in: endpoint {
1387                                                         remote-endpoint = <&mdss_mdp_intf2_out>;
1388                                                 };
1389                                         };
1390
1391                                         port@1 {
1392                                                 reg = <1>;
1393                                                 mdss_dsi1_out: endpoint {
1394                                                 };
1395                                         };
1396                                 };
1397                         };
1398
1399                         mdss_dsi1_phy: phy@1aa0300 {
1400                                 compatible = "qcom,dsi-phy-28nm-lp";
1401                                 reg = <0x01aa0300 0xd4>,
1402                                       <0x01aa0500 0x280>,
1403                                       <0x01aa0780 0x30>;
1404                                 reg-names = "dsi_pll",
1405                                             "dsi_phy",
1406                                             "dsi_phy_regulator";
1407
1408                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1409                                          <&rpmcc RPM_SMD_XO_CLK_SRC>;
1410                                 clock-names = "iface", "ref";
1411
1412                                 #clock-cells = <1>;
1413                                 #phy-cells = <0>;
1414                                 status = "disabled";
1415                         };
1416                 };
1417
1418                 gpu: gpu@1c00000 {
1419                         compatible = "qcom,adreno-405.0", "qcom,adreno";
1420                         reg = <0x01c00000 0x10000>;
1421                         reg-names = "kgsl_3d0_reg_memory";
1422                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1423                         interrupt-names = "kgsl_3d0_irq";
1424                         clock-names = "core",
1425                                       "iface",
1426                                       "mem",
1427                                       "mem_iface",
1428                                       "alt_mem_iface",
1429                                       "gfx3d",
1430                                       "rbbmtimer";
1431                         clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1432                                  <&gcc GCC_OXILI_AHB_CLK>,
1433                                  <&gcc GCC_OXILI_GMEM_CLK>,
1434                                  <&gcc GCC_BIMC_GFX_CLK>,
1435                                  <&gcc GCC_BIMC_GPU_CLK>,
1436                                  <&gcc GFX3D_CLK_SRC>,
1437                                  <&gcc GCC_OXILI_TIMER_CLK>;
1438                         power-domains = <&gcc OXILI_GDSC>;
1439                         operating-points-v2 = <&opp_table>;
1440                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1441                         status = "disabled";
1442
1443                         opp_table: opp-table {
1444                                 compatible = "operating-points-v2";
1445
1446                                 opp-550000000 {
1447                                         opp-hz = /bits/ 64 <550000000>;
1448                                 };
1449
1450                                 opp-465000000 {
1451                                         opp-hz = /bits/ 64 <465000000>;
1452                                 };
1453
1454                                 opp-400000000 {
1455                                         opp-hz = /bits/ 64 <400000000>;
1456                                 };
1457
1458                                 opp-220000000 {
1459                                         opp-hz = /bits/ 64 <220000000>;
1460                                 };
1461
1462                                 opp-19200000 {
1463                                         opp-hz = /bits/ 64 <19200000>;
1464                                 };
1465                         };
1466                 };
1467
1468                 apps_iommu: iommu@1ef0000 {
1469                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1470                         reg = <0x01ef0000 0x3000>;
1471                         ranges = <0 0x01e20000 0x20000>;
1472                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1473                                  <&gcc GCC_APSS_TCU_CLK>;
1474                         clock-names = "iface", "bus";
1475                         #address-cells = <1>;
1476                         #size-cells = <1>;
1477                         #iommu-cells = <1>;
1478                         qcom,iommu-secure-id = <17>;
1479
1480                         /* mdp_0: */
1481                         iommu-ctx@4000 {
1482                                 compatible = "qcom,msm-iommu-v1-ns";
1483                                 reg = <0x4000 0x1000>;
1484                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1485                         };
1486
1487                         /* venus_ns: */
1488                         iommu-ctx@5000 {
1489                                 compatible = "qcom,msm-iommu-v1-sec";
1490                                 reg = <0x5000 0x1000>;
1491                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1492                         };
1493                 };
1494
1495                 gpu_iommu: iommu@1f08000 {
1496                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1497                         ranges = <0 0x1f08000 0x10000>;
1498                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1499                                  <&gcc GCC_GFX_TCU_CLK>,
1500                                  <&gcc GCC_GFX_TBU_CLK>;
1501                         clock-names = "iface", "bus", "tbu";
1502                         #address-cells = <1>;
1503                         #size-cells = <1>;
1504                         #iommu-cells = <1>;
1505                         qcom,iommu-secure-id = <18>;
1506
1507                         /* gfx3d_user: */
1508                         iommu-ctx@1000 {
1509                                 compatible = "qcom,msm-iommu-v1-ns";
1510                                 reg = <0x1000 0x1000>;
1511                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1512                         };
1513
1514                         /* gfx3d_priv: */
1515                         iommu-ctx@2000 {
1516                                 compatible = "qcom,msm-iommu-v1-ns";
1517                                 reg = <0x2000 0x1000>;
1518                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1519                         };
1520                 };
1521
1522                 spmi_bus: spmi@200f000 {
1523                         compatible = "qcom,spmi-pmic-arb";
1524                         reg = <0x0200f000 0x001000>,
1525                               <0x02400000 0x400000>,
1526                               <0x02c00000 0x400000>,
1527                               <0x03800000 0x200000>,
1528                               <0x0200a000 0x002100>;
1529                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1530                         interrupt-names = "periph_irq";
1531                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1532                         qcom,ee = <0>;
1533                         qcom,channel = <0>;
1534                         #address-cells = <2>;
1535                         #size-cells = <0>;
1536                         interrupt-controller;
1537                         #interrupt-cells = <4>;
1538                 };
1539
1540                 mpss: remoteproc@4080000 {
1541                         compatible = "qcom,msm8916-mss-pil";
1542                         reg = <0x04080000 0x100>, <0x04020000 0x040>;
1543                         reg-names = "qdsp6", "rmb";
1544                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1545                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1546                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1547                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1548                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1549                         interrupt-names = "wdog",
1550                                           "fatal",
1551                                           "ready",
1552                                           "handover",
1553                                           "stop-ack";
1554                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1555                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1556                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1557                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1558                         clock-names = "iface",
1559                                       "bus",
1560                                       "mem",
1561                                       "xo";
1562                         power-domains = <&rpmpd MSM8939_VDDMDCX>,
1563                                         <&rpmpd MSM8939_VDDMX>;
1564                         power-domain-names = "cx", "mx";
1565                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1566                         qcom,smem-state-names = "stop";
1567                         resets = <&scm 0>;
1568                         reset-names = "mss_restart";
1569                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1570                         status = "disabled";
1571
1572                         mba {
1573                                 memory-region = <&mba_mem>;
1574                         };
1575
1576                         mpss {
1577                                 memory-region = <&mpss_mem>;
1578                         };
1579
1580                         smd-edge {
1581                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1582
1583                                 qcom,smd-edge = <0>;
1584                                 mboxes = <&apcs1_mbox 12>;
1585                                 qcom,remote-pid = <1>;
1586
1587                                 label = "hexagon";
1588                         };
1589                 };
1590
1591                 sound: sound@7702000 {
1592                         compatible = "qcom,apq8016-sbc-sndcard";
1593                         reg = <0x07702000 0x4>,
1594                               <0x07702004 0x4>;
1595                         reg-names = "mic-iomux", "spkr-iomux";
1596                         status = "disabled";
1597                 };
1598
1599                 lpass: audio-controller@7708000 {
1600                         compatible = "qcom,apq8016-lpass-cpu";
1601                         reg = <0x07708000 0x10000>;
1602                         reg-names = "lpass-lpaif";
1603                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1604                         interrupt-names = "lpass-irq-lpaif";
1605                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1606                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1607                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1608                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1609                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
1610                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1611                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
1612                         clock-names = "ahbix-clk",
1613                                       "mi2s-bit-clk0",
1614                                       "mi2s-bit-clk1",
1615                                       "mi2s-bit-clk2",
1616                                       "mi2s-bit-clk3",
1617                                       "pcnoc-mport-clk",
1618                                       "pcnoc-sway-clk";
1619                         #sound-dai-cells = <1>;
1620                         #address-cells = <1>;
1621                         #size-cells = <0>;
1622                         status = "disabled";
1623                 };
1624
1625                 lpass_codec: audio-codec@771c000 {
1626                         compatible = "qcom,msm8916-wcd-digital-codec";
1627                         reg = <0x0771c000 0x400>;
1628                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1629                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
1630                         clock-names = "ahbix-clk", "mclk";
1631                         #sound-dai-cells = <1>;
1632                         status = "disabled";
1633                 };
1634
1635                 sdhc_1: mmc@7824900 {
1636                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1637                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1638                         reg-names = "hc", "core";
1639
1640                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1641                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1642                         interrupt-names = "hc_irq", "pwr_irq";
1643                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1644                                  <&gcc GCC_SDCC1_APPS_CLK>,
1645                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1646                         clock-names = "iface", "core", "xo";
1647                         resets = <&gcc GCC_SDCC1_BCR>;
1648                         pinctrl-0 = <&sdc1_default>;
1649                         pinctrl-1 = <&sdc1_sleep>;
1650                         pinctrl-names = "default", "sleep";
1651                         mmc-ddr-1_8v;
1652                         bus-width = <8>;
1653                         non-removable;
1654                         status = "disabled";
1655                 };
1656
1657                 sdhc_2: mmc@7864900 {
1658                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1659                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1660                         reg-names = "hc", "core";
1661
1662                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1663                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1664                         interrupt-names = "hc_irq", "pwr_irq";
1665                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1666                                  <&gcc GCC_SDCC2_APPS_CLK>,
1667                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1668                         clock-names = "iface", "core", "xo";
1669                         resets = <&gcc GCC_SDCC2_BCR>;
1670                         pinctrl-0 = <&sdc2_default>;
1671                         pinctrl-1 = <&sdc2_sleep>;
1672                         pinctrl-names = "default", "sleep";
1673                         bus-width = <4>;
1674                         status = "disabled";
1675                 };
1676
1677                 blsp_dma: dma-controller@7884000 {
1678                         compatible = "qcom,bam-v1.7.0";
1679                         reg = <0x07884000 0x23000>;
1680                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1681                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1682                         clock-names = "bam_clk";
1683                         #dma-cells = <1>;
1684                         qcom,ee = <0>;
1685                 };
1686
1687                 blsp_uart1: serial@78af000 {
1688                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1689                         reg = <0x078af000 0x200>;
1690                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1691                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1692                         clock-names = "core", "iface";
1693                         dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1694                         dma-names = "tx", "rx";
1695                         pinctrl-0 = <&blsp_uart1_default>;
1696                         pinctrl-1 = <&blsp_uart1_sleep>;
1697                         pinctrl-names = "default", "sleep";
1698                         status = "disabled";
1699                 };
1700
1701                 blsp_uart2: serial@78b0000 {
1702                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1703                         reg = <0x078b0000 0x200>;
1704                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1705                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1706                         clock-names = "core", "iface";
1707                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1708                         dma-names = "tx", "rx";
1709                         pinctrl-0 = <&blsp_uart2_default>;
1710                         pinctrl-1 = <&blsp_uart2_sleep>;
1711                         pinctrl-names = "default", "sleep";
1712                         status = "disabled";
1713                 };
1714
1715                 blsp_i2c1: i2c@78b5000 {
1716                         compatible = "qcom,i2c-qup-v2.2.1";
1717                         reg = <0x078b5000 0x500>;
1718                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1719                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1720                                  <&gcc GCC_BLSP1_AHB_CLK>;
1721                         clock-names = "core", "iface";
1722                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1723                         dma-names = "tx", "rx";
1724                         pinctrl-0 = <&blsp_i2c1_default>;
1725                         pinctrl-1 = <&blsp_i2c1_sleep>;
1726                         pinctrl-names = "default", "sleep";
1727                         #address-cells = <1>;
1728                         #size-cells = <0>;
1729                         status = "disabled";
1730                 };
1731
1732                 blsp_spi1: spi@78b5000 {
1733                         compatible = "qcom,spi-qup-v2.2.1";
1734                         reg = <0x078b5000 0x500>;
1735                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1736                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1737                                  <&gcc GCC_BLSP1_AHB_CLK>;
1738                         clock-names = "core", "iface";
1739                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1740                         dma-names = "tx", "rx";
1741                         pinctrl-0 = <&blsp_spi1_default>;
1742                         pinctrl-1 = <&blsp_spi1_sleep>;
1743                         pinctrl-names = "default", "sleep";
1744                         #address-cells = <1>;
1745                         #size-cells = <0>;
1746                         status = "disabled";
1747                 };
1748
1749                 blsp_i2c2: i2c@78b6000 {
1750                         compatible = "qcom,i2c-qup-v2.2.1";
1751                         reg = <0x078b6000 0x500>;
1752                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1753                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1754                                  <&gcc GCC_BLSP1_AHB_CLK>;
1755                         clock-names = "core", "iface";
1756                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1757                         dma-names = "tx", "rx";
1758                         pinctrl-0 = <&blsp_i2c2_default>;
1759                         pinctrl-1 = <&blsp_i2c2_sleep>;
1760                         pinctrl-names = "default", "sleep";
1761                         #address-cells = <1>;
1762                         #size-cells = <0>;
1763                         status = "disabled";
1764                 };
1765
1766                 blsp_spi2: spi@78b6000 {
1767                         compatible = "qcom,spi-qup-v2.2.1";
1768                         reg = <0x078b6000 0x500>;
1769                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1770                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1771                                  <&gcc GCC_BLSP1_AHB_CLK>;
1772                         clock-names = "core", "iface";
1773                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1774                         dma-names = "tx", "rx";
1775                         pinctrl-0 = <&blsp_spi2_default>;
1776                         pinctrl-1 = <&blsp_spi2_sleep>;
1777                         pinctrl-names = "default", "sleep";
1778                         #address-cells = <1>;
1779                         #size-cells = <0>;
1780                         status = "disabled";
1781                 };
1782
1783                 blsp_i2c3: i2c@78b7000 {
1784                         compatible = "qcom,i2c-qup-v2.2.1";
1785                         reg = <0x078b7000 0x500>;
1786                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1787                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1788                                  <&gcc GCC_BLSP1_AHB_CLK>;
1789                         clock-names = "core", "iface";
1790                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1791                         dma-names = "tx", "rx";
1792                         pinctrl-0 = <&blsp_i2c3_default>;
1793                         pinctrl-1 = <&blsp_i2c3_sleep>;
1794                         pinctrl-names = "default", "sleep";
1795                         #address-cells = <1>;
1796                         #size-cells = <0>;
1797                         status = "disabled";
1798                 };
1799
1800                 blsp_spi3: spi@78b7000 {
1801                         compatible = "qcom,spi-qup-v2.2.1";
1802                         reg = <0x078b7000 0x500>;
1803                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1804                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1805                                  <&gcc GCC_BLSP1_AHB_CLK>;
1806                         clock-names = "core", "iface";
1807                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1808                         dma-names = "tx", "rx";
1809                         pinctrl-0 = <&blsp_spi3_default>;
1810                         pinctrl-1 = <&blsp_spi3_sleep>;
1811                         pinctrl-names = "default", "sleep";
1812                         #address-cells = <1>;
1813                         #size-cells = <0>;
1814                         status = "disabled";
1815                 };
1816
1817                 blsp_i2c4: i2c@78b8000 {
1818                         compatible = "qcom,i2c-qup-v2.2.1";
1819                         reg = <0x078b8000 0x500>;
1820                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1821                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1822                                  <&gcc GCC_BLSP1_AHB_CLK>;
1823                         clock-names = "core", "iface";
1824                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1825                         dma-names = "tx", "rx";
1826                         pinctrl-0 = <&blsp_i2c4_default>;
1827                         pinctrl-1 = <&blsp_i2c4_sleep>;
1828                         pinctrl-names = "default", "sleep";
1829                         #address-cells = <1>;
1830                         #size-cells = <0>;
1831                         status = "disabled";
1832                 };
1833
1834                 blsp_spi4: spi@78b8000 {
1835                         compatible = "qcom,spi-qup-v2.2.1";
1836                         reg = <0x078b8000 0x500>;
1837                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1838                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1839                                  <&gcc GCC_BLSP1_AHB_CLK>;
1840                         clock-names = "core", "iface";
1841                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1842                         dma-names = "tx", "rx";
1843                         pinctrl-0 = <&blsp_spi4_default>;
1844                         pinctrl-1 = <&blsp_spi4_sleep>;
1845                         pinctrl-names = "default", "sleep";
1846                         #address-cells = <1>;
1847                         #size-cells = <0>;
1848                         status = "disabled";
1849                 };
1850
1851                 blsp_i2c5: i2c@78b9000 {
1852                         compatible = "qcom,i2c-qup-v2.2.1";
1853                         reg = <0x078b9000 0x500>;
1854                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1855                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1856                                  <&gcc GCC_BLSP1_AHB_CLK>;
1857                         clock-names = "core", "iface";
1858                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1859                         dma-names = "tx", "rx";
1860                         pinctrl-0 = <&blsp_i2c5_default>;
1861                         pinctrl-1 = <&blsp_i2c5_sleep>;
1862                         pinctrl-names = "default", "sleep";
1863                         #address-cells = <1>;
1864                         #size-cells = <0>;
1865                         status = "disabled";
1866                 };
1867
1868                 blsp_spi5: spi@78b9000 {
1869                         compatible = "qcom,spi-qup-v2.2.1";
1870                         reg = <0x078b9000 0x500>;
1871                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1872                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1873                                  <&gcc GCC_BLSP1_AHB_CLK>;
1874                         clock-names = "core", "iface";
1875                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1876                         dma-names = "tx", "rx";
1877                         pinctrl-0 = <&blsp_spi5_default>;
1878                         pinctrl-1 = <&blsp_spi5_sleep>;
1879                         pinctrl-names = "default", "sleep";
1880                         #address-cells = <1>;
1881                         #size-cells = <0>;
1882                         status = "disabled";
1883                 };
1884
1885                 blsp_i2c6: i2c@78ba000 {
1886                         compatible = "qcom,i2c-qup-v2.2.1";
1887                         reg = <0x078ba000 0x500>;
1888                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1889                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1890                                  <&gcc GCC_BLSP1_AHB_CLK>;
1891                         clock-names = "core", "iface";
1892                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1893                         dma-names = "tx", "rx";
1894                         pinctrl-0 = <&blsp_i2c6_default>;
1895                         pinctrl-1 = <&blsp_i2c6_sleep>;
1896                         pinctrl-names = "default", "sleep";
1897                         #address-cells = <1>;
1898                         #size-cells = <0>;
1899                         status = "disabled";
1900                 };
1901
1902                 blsp_spi6: spi@78ba000 {
1903                         compatible = "qcom,spi-qup-v2.2.1";
1904                         reg = <0x078ba000 0x500>;
1905                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1906                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1907                                  <&gcc GCC_BLSP1_AHB_CLK>;
1908                         clock-names = "core", "iface";
1909                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1910                         dma-names = "tx", "rx";
1911                         pinctrl-0 = <&blsp_spi6_default>;
1912                         pinctrl-1 = <&blsp_spi6_sleep>;
1913                         pinctrl-names = "default", "sleep";
1914                         #address-cells = <1>;
1915                         #size-cells = <0>;
1916                         status = "disabled";
1917                 };
1918
1919                 usb: usb@78d9000 {
1920                         compatible = "qcom,ci-hdrc";
1921                         reg = <0x078d9000 0x200>,
1922                               <0x078d9200 0x200>;
1923                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1924                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1925                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1926                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
1927                         clock-names = "iface", "core";
1928                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1929                         assigned-clock-rates = <80000000>;
1930                         resets = <&gcc GCC_USB_HS_BCR>;
1931                         reset-names = "core";
1932                         #reset-cells = <1>;
1933                         phy_type = "ulpi";
1934                         dr_mode = "otg";
1935                         adp-disable;
1936                         hnp-disable;
1937                         srp-disable;
1938                         ahb-burst-config = <0>;
1939                         phy-names = "usb-phy";
1940                         phys = <&usb_hs_phy>;
1941                         status = "disabled";
1942
1943                         ulpi {
1944                                 usb_hs_phy: phy {
1945                                         compatible = "qcom,usb-hs-phy-msm8916",
1946                                                      "qcom,usb-hs-phy";
1947                                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1948                                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1949                                         clock-names = "ref", "sleep";
1950                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1951                                         reset-names = "phy", "por";
1952                                         #phy-cells = <0>;
1953                                         qcom,init-seq = /bits/ 8 <0x0 0x44>,
1954                                                                  <0x1 0x6b>,
1955                                                                  <0x2 0x24>,
1956                                                                  <0x3 0x13>;
1957                                 };
1958                         };
1959                 };
1960
1961                 wcnss: remoteproc@a204000 {
1962                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1963                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1964                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1965                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1966                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1967                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1968                         interrupt-names = "wdog",
1969                                           "fatal",
1970                                           "ready",
1971                                           "handover",
1972                                           "stop-ack";
1973                         reg = <0x0a204000 0x2000>,
1974                               <0x0a202000 0x1000>,
1975                               <0x0a21b000 0x3000>;
1976                         reg-names = "ccu", "dxe", "pmu";
1977
1978                         memory-region = <&wcnss_mem>;
1979
1980                         power-domains = <&rpmpd MSM8939_VDDCX>,
1981                                         <&rpmpd MSM8939_VDDMX>;
1982                         power-domain-names = "cx", "mx";
1983
1984                         qcom,smem-states = <&wcnss_smp2p_out 0>;
1985                         qcom,smem-state-names = "stop";
1986
1987                         pinctrl-names = "default";
1988                         pinctrl-0 = <&wcss_wlan_default>;
1989
1990                         status = "disabled";
1991
1992                         wcnss_iris: iris {
1993                                 /* Separate chip, compatible is board-specific */
1994                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1995                                 clock-names = "xo";
1996                         };
1997
1998                         smd-edge {
1999                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2000                                 qcom,ipc = <&apcs1_mbox 8 17>;
2001                                 qcom,smd-edge = <6>;
2002                                 qcom,remote-pid = <4>;
2003
2004                                 label = "pronto";
2005
2006                                 wcnss {
2007                                         compatible = "qcom,wcnss";
2008                                         qcom,smd-channels = "WCNSS_CTRL";
2009
2010                                         qcom,mmio = <&wcnss>;
2011
2012                                         wcnss_bt: bluetooth {
2013                                                 compatible = "qcom,wcnss-bt";
2014                                         };
2015
2016                                         wcnss_wifi: wifi {
2017                                                 compatible = "qcom,wcnss-wlan";
2018
2019                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2020                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2021                                                 interrupt-names = "tx", "rx";
2022
2023                                                 qcom,smem-states = <&apps_smsm 10>,
2024                                                                    <&apps_smsm 9>;
2025                                                 qcom,smem-state-names = "tx-enable",
2026                                                                         "tx-rings-empty";
2027                                         };
2028                                 };
2029                         };
2030                 };
2031
2032                 intc: interrupt-controller@b000000 {
2033                         compatible = "qcom,msm-qgic2";
2034                         reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2035                               <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2036                         interrupt-controller;
2037                         #interrupt-cells = <3>;
2038                         interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2039                 };
2040
2041                 apcs1_mbox: mailbox@b011000 {
2042                         compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2043                         reg = <0x0b011000 0x1000>;
2044                         clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2045                         clock-names = "pll", "aux", "ref";
2046                         #clock-cells = <0>;
2047                         assigned-clocks = <&apcs2>;
2048                         assigned-clock-rates = <297600000>;
2049                         #mbox-cells = <1>;
2050                 };
2051
2052                 a53pll_c1: clock@b016000 {
2053                         compatible = "qcom,msm8939-a53pll";
2054                         reg = <0x0b016000 0x40>;
2055                         #clock-cells = <0>;
2056                 };
2057
2058                 acc0: clock-controller@b088000 {
2059                         compatible = "qcom,kpss-acc-v2";
2060                         reg = <0x0b088000 0x1000>;
2061                 };
2062
2063                 saw0: power-manager@b089000 {
2064                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2065                         reg = <0x0b089000 0x1000>;
2066                 };
2067
2068                 acc1: clock-controller@b098000 {
2069                         compatible = "qcom,kpss-acc-v2";
2070                         reg = <0x0b098000 0x1000>;
2071                 };
2072
2073                 saw1: power-manager@b099000 {
2074                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2075                         reg = <0x0b099000 0x1000>;
2076                 };
2077
2078                 acc2: clock-controller@b0a8000 {
2079                         compatible = "qcom,kpss-acc-v2";
2080                         reg = <0x0b0a8000 0x1000>;
2081                 };
2082
2083                 saw2: power-manager@b0a9000 {
2084                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2085                         reg = <0x0b0a9000 0x1000>;
2086                 };
2087
2088                 acc3: clock-controller@b0b8000 {
2089                         compatible = "qcom,kpss-acc-v2";
2090                         reg = <0x0b0b8000 0x1000>;
2091                 };
2092
2093                 saw3: power-manager@b0b9000 {
2094                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2095                         reg = <0x0b0b9000 0x1000>;
2096                 };
2097
2098                 apcs0_mbox: mailbox@b111000 {
2099                         compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2100                         reg = <0x0b111000 0x1000>;
2101                         clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2102                         clock-names = "pll", "aux", "ref";
2103                         #clock-cells = <0>;
2104                         #mbox-cells = <1>;
2105                 };
2106
2107                 a53pll_c0: clock@b116000 {
2108                         compatible = "qcom,msm8939-a53pll";
2109                         reg = <0x0b116000 0x40>;
2110                         #clock-cells = <0>;
2111                 };
2112
2113                 timer@b120000 {
2114                         compatible = "arm,armv7-timer-mem";
2115                         reg = <0x0b120000 0x1000>;
2116                         #address-cells = <1>;
2117                         #size-cells = <1>;
2118                         ranges;
2119
2120                         frame@b121000 {
2121                                 reg = <0x0b121000 0x1000>,
2122                                       <0x0b122000 0x1000>;
2123                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2124                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2125                                 frame-number = <0>;
2126                         };
2127
2128                         frame@b123000 {
2129                                 reg = <0x0b123000 0x1000>;
2130                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2131                                 frame-number = <1>;
2132                                 status = "disabled";
2133                         };
2134
2135                         frame@b124000 {
2136                                 reg = <0x0b124000 0x1000>;
2137                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2138                                 frame-number = <2>;
2139                                 status = "disabled";
2140                         };
2141
2142                         frame@b125000 {
2143                                 reg = <0x0b125000 0x1000>;
2144                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2145                                 frame-number = <3>;
2146                                 status = "disabled";
2147                         };
2148
2149                         frame@b126000 {
2150                                 reg = <0x0b126000 0x1000>;
2151                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2152                                 frame-number = <4>;
2153                                 status = "disabled";
2154                         };
2155
2156                         frame@b127000 {
2157                                 reg = <0x0b127000 0x1000>;
2158                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2159                                 frame-number = <5>;
2160                                 status = "disabled";
2161                         };
2162
2163                         frame@b128000 {
2164                                 reg = <0x0b128000 0x1000>;
2165                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2166                                 frame-number = <6>;
2167                                 status = "disabled";
2168                         };
2169                 };
2170
2171                 acc4: clock-controller@b188000 {
2172                         compatible = "qcom,kpss-acc-v2";
2173                         reg = <0x0b188000 0x1000>;
2174                 };
2175
2176                 saw4: power-manager@b189000 {
2177                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2178                         reg = <0x0b189000 0x1000>;
2179                 };
2180
2181                 acc5: clock-controller@b198000 {
2182                         compatible = "qcom,kpss-acc-v2";
2183                         reg = <0x0b198000 0x1000>;
2184                 };
2185
2186                 saw5: power-manager@b199000 {
2187                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2188                         reg = <0x0b199000 0x1000>;
2189                 };
2190
2191                 acc6: clock-controller@b1a8000 {
2192                         compatible = "qcom,kpss-acc-v2";
2193                         reg = <0x0b1a8000 0x1000>;
2194                 };
2195
2196                 saw6: power-manager@b1a9000 {
2197                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2198                         reg = <0x0b1a9000 0x1000>;
2199                 };
2200
2201                 acc7: clock-controller@b1b8000 {
2202                         compatible = "qcom,kpss-acc-v2";
2203                         reg = <0x0b1b8000 0x1000>;
2204                 };
2205
2206                 saw7: power-manager@b1b9000 {
2207                         compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
2208                         reg = <0x0b1b9000 0x1000>;
2209                 };
2210
2211                 a53pll_cci: clock@b1d0000 {
2212                         compatible = "qcom,msm8939-a53pll";
2213                         reg = <0x0b1d0000 0x40>;
2214                         #clock-cells = <0>;
2215                 };
2216
2217                 apcs2: mailbox@b1d1000 {
2218                         compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
2219                         reg = <0x0b1d1000 0x1000>;
2220                         clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
2221                         clock-names = "pll", "aux", "ref";
2222                         #clock-cells = <0>;
2223                         #mbox-cells = <1>;
2224                 };
2225         };
2226
2227         thermal_zones: thermal-zones {
2228                 cpu0-thermal {
2229                         polling-delay-passive = <250>;
2230                         polling-delay = <1000>;
2231
2232                         thermal-sensors = <&tsens 5>;
2233
2234                         trips {
2235                                 cpu0_alert: trip0 {
2236                                         temperature = <75000>;
2237                                         hysteresis = <2000>;
2238                                         type = "passive";
2239                                 };
2240
2241                                 cpu0_crit: trip1 {
2242                                         temperature = <115000>;
2243                                         hysteresis = <0>;
2244                                         type = "critical";
2245                                 };
2246                         };
2247
2248                         cooling-maps {
2249                                 map0 {
2250                                         trip = <&cpu0_alert>;
2251                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2252                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2253                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2254                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2255                                 };
2256                         };
2257                 };
2258
2259                 cpu1-thermal {
2260                         polling-delay-passive = <250>;
2261                         polling-delay = <1000>;
2262
2263                         thermal-sensors = <&tsens 6>;
2264
2265                         trips {
2266                                 cpu1_alert: trip0 {
2267                                         temperature = <75000>;
2268                                         hysteresis = <2000>;
2269                                         type = "passive";
2270                                 };
2271
2272                                 cpu1_crit: trip1 {
2273                                         temperature = <110000>;
2274                                         hysteresis = <2000>;
2275                                         type = "critical";
2276                                 };
2277                         };
2278
2279                         cooling-maps {
2280                                 map0 {
2281                                         trip = <&cpu1_alert>;
2282                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2283                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2284                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2285                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2286                                 };
2287                         };
2288                 };
2289
2290                 cpu2-thermal {
2291                         polling-delay-passive = <250>;
2292                         polling-delay = <1000>;
2293
2294                         thermal-sensors = <&tsens 7>;
2295
2296                         trips {
2297                                 cpu2_alert: trip0 {
2298                                         temperature = <75000>;
2299                                         hysteresis = <2000>;
2300                                         type = "passive";
2301                                 };
2302
2303                                 cpu2_crit: trip1 {
2304                                         temperature = <110000>;
2305                                         hysteresis = <2000>;
2306                                         type = "critical";
2307                                 };
2308                         };
2309
2310                         cooling-maps {
2311                                 map0 {
2312                                         trip = <&cpu2_alert>;
2313                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2314                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2315                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2316                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2317                                 };
2318                         };
2319                 };
2320
2321                 cpu3-thermal {
2322                         polling-delay-passive = <250>;
2323                         polling-delay = <1000>;
2324
2325                         thermal-sensors = <&tsens 8>;
2326
2327                         trips {
2328                                 cpu3_alert: trip0 {
2329                                         temperature = <75000>;
2330                                         hysteresis = <2000>;
2331                                         type = "passive";
2332                                 };
2333
2334                                 cpu3_crit: trip1 {
2335                                         temperature = <110000>;
2336                                         hysteresis = <2000>;
2337                                         type = "critical";
2338                                 };
2339                         };
2340
2341                         cooling-maps {
2342                                 map0 {
2343                                         trip = <&cpu3_alert>;
2344                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2345                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2346                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2347                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2348                                 };
2349                         };
2350                 };
2351
2352                 cpu4567-thermal {
2353                         polling-delay-passive = <250>;
2354                         polling-delay = <1000>;
2355
2356                         thermal-sensors = <&tsens 9>;
2357
2358                         trips {
2359                                 cpu4567_alert: trip0 {
2360                                         temperature = <75000>;
2361                                         hysteresis = <2000>;
2362                                         type = "passive";
2363                                 };
2364
2365                                 cpu4567_crit: trip1 {
2366                                         temperature = <110000>;
2367                                         hysteresis = <2000>;
2368                                         type = "critical";
2369                                 };
2370                         };
2371
2372                         cooling-maps {
2373                                 map0 {
2374                                         trip = <&cpu4567_alert>;
2375                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2376                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2377                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2378                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2379                                 };
2380                         };
2381                 };
2382
2383                 gpu-thermal {
2384                         polling-delay-passive = <250>;
2385                         polling-delay = <1000>;
2386
2387                         thermal-sensors = <&tsens 3>;
2388
2389                         trips {
2390                                 gpu_alert0: trip-point0 {
2391                                         temperature = <75000>;
2392                                         hysteresis = <2000>;
2393                                         type = "passive";
2394                                 };
2395
2396                                 gpu_crit: gpu_crit {
2397                                         temperature = <95000>;
2398                                         hysteresis = <2000>;
2399                                         type = "critical";
2400                                 };
2401                         };
2402                 };
2403
2404                 modem1-thermal {
2405                         polling-delay-passive = <250>;
2406                         polling-delay = <1000>;
2407
2408                         thermal-sensors = <&tsens 0>;
2409
2410                         trips {
2411                                 modem1_alert0: trip-point0 {
2412                                         temperature = <85000>;
2413                                         hysteresis = <2000>;
2414                                         type = "hot";
2415                                 };
2416                         };
2417                 };
2418
2419                 modem2-thermal {
2420                         polling-delay-passive = <250>;
2421                         polling-delay = <1000>;
2422
2423                         thermal-sensors = <&tsens 2>;
2424
2425                         trips {
2426                                 modem2_alert0: trip-point0 {
2427                                         temperature = <85000>;
2428                                         hysteresis = <2000>;
2429                                         type = "hot";
2430                                 };
2431                         };
2432                 };
2433
2434                 camera-thermal {
2435                         polling-delay-passive = <250>;
2436                         polling-delay = <1000>;
2437
2438                         thermal-sensors = <&tsens 1>;
2439
2440                         trips {
2441                                 cam_alert0: trip-point0 {
2442                                         temperature = <75000>;
2443                                         hysteresis = <2000>;
2444                                         type = "hot";
2445                                 };
2446                         };
2447                 };
2448         };
2449
2450         timer {
2451                 compatible = "arm,armv8-timer";
2452                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2453                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2454                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2455                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2456         };
2457 };