2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
19 model = "Qualcomm Technologies, Inc. MSM8916";
20 compatible = "qcom,msm8916";
22 interrupt-parent = <&intc>;
28 mmc0 = &sdhc_1; /* SDC1 eMMC slot */
29 mmc1 = &sdhc_2; /* SDC2 SD card slot */
35 device_type = "memory";
36 /* We expect the bootloader to fill in the reg */
46 reg = <0x0 0x86000000 0x0 0x300000>;
50 smem_mem: smem_region@86300000 {
51 reg = <0x0 0x86300000 0x0 0x100000>;
56 reg = <0x0 0x86400000 0x0 0x100000>;
61 reg = <0x0 0x86500000 0x0 0x180000>;
66 reg = <0x0 0x86680000 0x0 0x80000>;
71 reg = <0x0 0x86700000 0x0 0xe0000>;
76 reg = <0x0 0x867e0000 0x0 0x20000>;
81 reg = <0x0 0x86800000 0x0 0x2b00000>;
86 reg = <0x0 0x89300000 0x0 0x600000>;
90 mba_mem: mba@8ea00000 {
92 reg = <0 0x8ea00000 0 0x100000>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 next-level-cache = <&L2_0>;
105 enable-method = "psci";
106 cpu-idle-states = <&CPU_SPC>;
111 compatible = "arm,cortex-a53", "arm,armv8";
113 next-level-cache = <&L2_0>;
114 enable-method = "psci";
115 cpu-idle-states = <&CPU_SPC>;
120 compatible = "arm,cortex-a53", "arm,armv8";
122 next-level-cache = <&L2_0>;
123 enable-method = "psci";
124 cpu-idle-states = <&CPU_SPC>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 next-level-cache = <&L2_0>;
132 enable-method = "psci";
133 cpu-idle-states = <&CPU_SPC>;
137 compatible = "cache";
143 compatible = "arm,idle-state";
144 arm,psci-suspend-param = <0x40000002>;
145 entry-latency-us = <130>;
146 exit-latency-us = <150>;
147 min-residency-us = <2000>;
154 compatible = "arm,psci-1.0";
159 compatible = "arm,armv8-pmuv3";
160 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
165 polling-delay-passive = <250>;
166 polling-delay = <1000>;
168 thermal-sensors = <&tsens 4>;
172 temperature = <75000>;
177 temperature = <110000>;
185 polling-delay-passive = <250>;
186 polling-delay = <1000>;
188 thermal-sensors = <&tsens 3>;
192 temperature = <75000>;
197 temperature = <110000>;
207 compatible = "arm,armv8-timer";
208 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
211 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
216 compatible = "fixed-clock";
218 clock-frequency = <19200000>;
221 sleep_clk: sleep_clk {
222 compatible = "fixed-clock";
224 clock-frequency = <32768>;
229 compatible = "qcom,smem";
231 memory-region = <&smem_mem>;
232 qcom,rpm-msg-ram = <&rpm_msg_ram>;
234 hwlocks = <&tcsr_mutex 3>;
239 compatible = "qcom,scm";
240 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
241 clock-names = "core", "bus", "iface";
247 #address-cells = <1>;
249 ranges = <0 0 0 0xffffffff>;
250 compatible = "simple-bus";
253 compatible = "qcom,pshold";
254 reg = <0x4ab000 0x4>;
257 msmgpio: pinctrl@1000000 {
258 compatible = "qcom,msm8916-pinctrl";
259 reg = <0x1000000 0x300000>;
260 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
267 gcc: clock-controller@1800000 {
268 compatible = "qcom,gcc-msm8916";
271 #power-domain-cells = <1>;
272 reg = <0x1800000 0x80000>;
275 tcsr_mutex_regs: syscon@1905000 {
276 compatible = "syscon";
277 reg = <0x1905000 0x20000>;
280 tcsr: syscon@1937000 {
281 compatible = "qcom,tcsr-msm8916", "syscon";
282 reg = <0x1937000 0x30000>;
286 compatible = "qcom,tcsr-mutex";
287 syscon = <&tcsr_mutex_regs 0 0x1000>;
291 rpm_msg_ram: memory@60000 {
292 compatible = "qcom,rpm-msg-ram";
293 reg = <0x60000 0x8000>;
296 blsp1_uart1: serial@78af000 {
297 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
298 reg = <0x78af000 0x200>;
299 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
301 clock-names = "core", "iface";
302 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
303 dma-names = "rx", "tx";
307 apcs: syscon@b011000 {
308 compatible = "syscon";
309 reg = <0x0b011000 0x1000>;
312 blsp1_uart2: serial@78b0000 {
313 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
314 reg = <0x78b0000 0x200>;
315 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
317 clock-names = "core", "iface";
318 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
319 dma-names = "rx", "tx";
323 blsp_dma: dma@7884000 {
324 compatible = "qcom,bam-v1.7.0";
325 reg = <0x07884000 0x23000>;
326 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
328 clock-names = "bam_clk";
334 blsp_spi1: spi@78b5000 {
335 compatible = "qcom,spi-qup-v2.2.1";
336 reg = <0x078b5000 0x600>;
337 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
339 <&gcc GCC_BLSP1_AHB_CLK>;
340 clock-names = "core", "iface";
341 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
342 dma-names = "rx", "tx";
343 pinctrl-names = "default", "sleep";
344 pinctrl-0 = <&spi1_default>;
345 pinctrl-1 = <&spi1_sleep>;
346 #address-cells = <1>;
351 blsp_spi2: spi@78b6000 {
352 compatible = "qcom,spi-qup-v2.2.1";
353 reg = <0x078b6000 0x600>;
354 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
356 <&gcc GCC_BLSP1_AHB_CLK>;
357 clock-names = "core", "iface";
358 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
359 dma-names = "rx", "tx";
360 pinctrl-names = "default", "sleep";
361 pinctrl-0 = <&spi2_default>;
362 pinctrl-1 = <&spi2_sleep>;
363 #address-cells = <1>;
368 blsp_spi3: spi@78b7000 {
369 compatible = "qcom,spi-qup-v2.2.1";
370 reg = <0x078b7000 0x600>;
371 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
373 <&gcc GCC_BLSP1_AHB_CLK>;
374 clock-names = "core", "iface";
375 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
376 dma-names = "rx", "tx";
377 pinctrl-names = "default", "sleep";
378 pinctrl-0 = <&spi3_default>;
379 pinctrl-1 = <&spi3_sleep>;
380 #address-cells = <1>;
385 blsp_spi4: spi@78b8000 {
386 compatible = "qcom,spi-qup-v2.2.1";
387 reg = <0x078b8000 0x600>;
388 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
390 <&gcc GCC_BLSP1_AHB_CLK>;
391 clock-names = "core", "iface";
392 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
393 dma-names = "rx", "tx";
394 pinctrl-names = "default", "sleep";
395 pinctrl-0 = <&spi4_default>;
396 pinctrl-1 = <&spi4_sleep>;
397 #address-cells = <1>;
402 blsp_spi5: spi@78b9000 {
403 compatible = "qcom,spi-qup-v2.2.1";
404 reg = <0x078b9000 0x600>;
405 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
407 <&gcc GCC_BLSP1_AHB_CLK>;
408 clock-names = "core", "iface";
409 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
410 dma-names = "rx", "tx";
411 pinctrl-names = "default", "sleep";
412 pinctrl-0 = <&spi5_default>;
413 pinctrl-1 = <&spi5_sleep>;
414 #address-cells = <1>;
419 blsp_spi6: spi@78ba000 {
420 compatible = "qcom,spi-qup-v2.2.1";
421 reg = <0x078ba000 0x600>;
422 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
424 <&gcc GCC_BLSP1_AHB_CLK>;
425 clock-names = "core", "iface";
426 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
427 dma-names = "rx", "tx";
428 pinctrl-names = "default", "sleep";
429 pinctrl-0 = <&spi6_default>;
430 pinctrl-1 = <&spi6_sleep>;
431 #address-cells = <1>;
436 blsp_i2c2: i2c@78b6000 {
437 compatible = "qcom,i2c-qup-v2.2.1";
438 reg = <0x78b6000 0x1000>;
439 interrupts = <GIC_SPI 96 0>;
440 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
441 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
442 clock-names = "iface", "core";
443 pinctrl-names = "default", "sleep";
444 pinctrl-0 = <&i2c2_default>;
445 pinctrl-1 = <&i2c2_sleep>;
446 #address-cells = <1>;
451 blsp_i2c4: i2c@78b8000 {
452 compatible = "qcom,i2c-qup-v2.2.1";
453 reg = <0x78b8000 0x1000>;
454 interrupts = <GIC_SPI 98 0>;
455 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
456 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
457 clock-names = "iface", "core";
458 pinctrl-names = "default", "sleep";
459 pinctrl-0 = <&i2c4_default>;
460 pinctrl-1 = <&i2c4_sleep>;
461 #address-cells = <1>;
466 blsp_i2c6: i2c@78ba000 {
467 compatible = "qcom,i2c-qup-v2.2.1";
468 reg = <0x78ba000 0x1000>;
469 interrupts = <GIC_SPI 100 0>;
470 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
471 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
472 clock-names = "iface", "core";
473 pinctrl-names = "default", "sleep";
474 pinctrl-0 = <&i2c6_default>;
475 pinctrl-1 = <&i2c6_sleep>;
476 #address-cells = <1>;
481 lpass: lpass@07708000 {
483 compatible = "qcom,lpass-cpu-apq8016";
484 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
485 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
486 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
487 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
488 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
489 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
490 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
492 clock-names = "ahbix-clk",
499 #sound-dai-cells = <1>;
501 interrupts = <0 160 0>;
502 interrupt-names = "lpass-irq-lpaif";
503 reg = <0x07708000 0x10000>;
504 reg-names = "lpass-lpaif";
507 sdhc_1: sdhci@07824000 {
508 compatible = "qcom,sdhci-msm-v4";
509 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
510 reg-names = "hc_mem", "core_mem";
512 interrupts = <0 123 0>, <0 138 0>;
513 interrupt-names = "hc_irq", "pwr_irq";
514 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
515 <&gcc GCC_SDCC1_AHB_CLK>;
516 clock-names = "core", "iface";
522 sdhc_2: sdhci@07864000 {
523 compatible = "qcom,sdhci-msm-v4";
524 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
525 reg-names = "hc_mem", "core_mem";
527 interrupts = <0 125 0>, <0 221 0>;
528 interrupt-names = "hc_irq", "pwr_irq";
529 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
530 <&gcc GCC_SDCC2_AHB_CLK>;
531 clock-names = "core", "iface";
536 usb_dev: usb@78d9000 {
537 compatible = "qcom,ci-hdrc";
538 reg = <0x78d9000 0x400>;
539 dr_mode = "peripheral";
540 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
541 usb-phy = <&usb_otg>;
545 usb_host: ehci@78d9000 {
546 compatible = "qcom,ehci-host";
547 reg = <0x78d9000 0x400>;
548 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
549 usb-phy = <&usb_otg>;
553 usb_otg: phy@78d9000 {
554 compatible = "qcom,usb-otg-snps";
555 reg = <0x78d9000 0x400>;
556 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
559 qcom,vdd-levels = <500000 1000000 1320000>;
560 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
561 dr_mode = "peripheral";
562 qcom,otg-control = <2>; // PMIC
565 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
566 <&gcc GCC_USB_HS_SYSTEM_CLK>,
567 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
568 clock-names = "iface", "core", "sleep";
570 resets = <&gcc GCC_USB2A_PHY_BCR>,
571 <&gcc GCC_USB_HS_BCR>;
572 reset-names = "phy", "link";
576 intc: interrupt-controller@b000000 {
577 compatible = "qcom,msm-qgic2";
578 interrupt-controller;
579 #interrupt-cells = <3>;
580 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
584 #address-cells = <1>;
587 compatible = "arm,armv7-timer-mem";
588 reg = <0xb020000 0x1000>;
589 clock-frequency = <19200000>;
593 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
595 reg = <0xb021000 0x1000>,
601 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
602 reg = <0xb023000 0x1000>;
608 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
609 reg = <0xb024000 0x1000>;
615 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
616 reg = <0xb025000 0x1000>;
622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
623 reg = <0xb026000 0x1000>;
629 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
630 reg = <0xb027000 0x1000>;
636 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
637 reg = <0xb028000 0x1000>;
642 spmi_bus: spmi@200f000 {
643 compatible = "qcom,spmi-pmic-arb";
644 reg = <0x200f000 0x001000>,
645 <0x2400000 0x400000>,
646 <0x2c00000 0x400000>,
647 <0x3800000 0x200000>,
648 <0x200a000 0x002100>;
649 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
650 interrupt-names = "periph_irq";
651 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
654 #address-cells = <2>;
656 interrupt-controller;
657 #interrupt-cells = <4>;
661 compatible = "qcom,prng";
662 reg = <0x00022000 0x200>;
663 clocks = <&gcc GCC_PRNG_AHB_CLK>;
664 clock-names = "core";
667 qfprom: qfprom@5c000 {
668 compatible = "qcom,qfprom";
669 reg = <0x5c000 0x1000>;
670 #address-cells = <1>;
672 tsens_caldata: caldata@d0 {
675 tsens_calsel: calsel@ec {
680 tsens: thermal-sensor@4a8000 {
681 compatible = "qcom,msm8916-tsens";
682 reg = <0x4a8000 0x2000>;
683 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
684 nvmem-cell-names = "calib", "calib_sel";
685 #thermal-sensor-cells = <1>;
689 compatible = "qcom,mdss";
690 reg = <0x1a00000 0x1000>,
692 reg-names = "mdss_phys", "vbif_phys";
694 power-domains = <&gcc MDSS_GDSC>;
696 clocks = <&gcc GCC_MDSS_AHB_CLK>,
697 <&gcc GCC_MDSS_AXI_CLK>,
698 <&gcc GCC_MDSS_VSYNC_CLK>;
699 clock-names = "iface_clk",
703 interrupts = <0 72 0>;
705 interrupt-controller;
706 #interrupt-cells = <1>;
708 #address-cells = <1>;
713 compatible = "qcom,mdp5";
714 reg = <0x1a01000 0x90000>;
715 reg-names = "mdp_phys";
717 interrupt-parent = <&mdss>;
720 clocks = <&gcc GCC_MDSS_AHB_CLK>,
721 <&gcc GCC_MDSS_AXI_CLK>,
722 <&gcc GCC_MDSS_MDP_CLK>,
723 <&gcc GCC_MDSS_VSYNC_CLK>;
724 clock-names = "iface_clk",
730 #address-cells = <1>;
735 mdp5_intf1_out: endpoint {
736 remote-endpoint = <&dsi0_in>;
743 compatible = "qcom,mdss-dsi-ctrl";
744 reg = <0x1a98000 0x25c>;
745 reg-names = "dsi_ctrl";
747 interrupt-parent = <&mdss>;
750 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
751 <&gcc PCLK0_CLK_SRC>;
752 assigned-clock-parents = <&dsi_phy0 0>,
755 clocks = <&gcc GCC_MDSS_MDP_CLK>,
756 <&gcc GCC_MDSS_AHB_CLK>,
757 <&gcc GCC_MDSS_AXI_CLK>,
758 <&gcc GCC_MDSS_BYTE0_CLK>,
759 <&gcc GCC_MDSS_PCLK0_CLK>,
760 <&gcc GCC_MDSS_ESC0_CLK>;
761 clock-names = "mdp_core_clk",
768 phy-names = "dsi-phy";
771 #address-cells = <1>;
777 remote-endpoint = <&mdp5_intf1_out>;
789 dsi_phy0: dsi-phy@1a98300 {
790 compatible = "qcom,dsi-phy-28nm-lp";
791 reg = <0x1a98300 0xd4>,
794 reg-names = "dsi_pll",
801 clocks = <&gcc GCC_MDSS_AHB_CLK>;
802 clock-names = "iface_clk";
808 compatible = "qcom,smd";
811 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
812 qcom,ipc = <&apcs 8 0>;
813 qcom,smd-edge = <15>;
816 compatible = "qcom,rpm-msm8916";
817 qcom,smd-channels = "rpm_requests";
820 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
824 smd_rpm_regulators: pm8916-regulators {
825 compatible = "qcom,rpm-pm8916-regulators";
855 compatible = "qcom,smp2p";
856 qcom,smem = <435>, <428>;
858 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
860 qcom,ipc = <&apcs 8 14>;
862 qcom,local-pid = <0>;
863 qcom,remote-pid = <1>;
865 hexagon_smp2p_out: master-kernel {
866 qcom,entry-name = "master-kernel";
868 #qcom,smem-state-cells = <1>;
871 hexagon_smp2p_in: slave-kernel {
872 qcom,entry-name = "slave-kernel";
874 interrupt-controller;
875 #interrupt-cells = <2>;
880 compatible = "qcom,smp2p";
881 qcom,smem = <451>, <431>;
883 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
885 qcom,ipc = <&apcs 8 18>;
887 qcom,local-pid = <0>;
888 qcom,remote-pid = <4>;
890 wcnss_smp2p_out: master-kernel {
891 qcom,entry-name = "master-kernel";
893 #qcom,smem-state-cells = <1>;
896 wcnss_smp2p_in: slave-kernel {
897 qcom,entry-name = "slave-kernel";
899 interrupt-controller;
900 #interrupt-cells = <2>;
905 compatible = "qcom,smsm";
907 #address-cells = <1>;
910 qcom,ipc-1 = <&apcs 8 13>;
911 qcom,ipc-3 = <&apcs 8 19>;
916 #qcom,smem-state-cells = <1>;
919 hexagon_smsm: hexagon@1 {
921 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
923 interrupt-controller;
924 #interrupt-cells = <2>;
927 wcnss_smsm: wcnss@6 {
929 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
931 interrupt-controller;
932 #interrupt-cells = <2>;
937 #include "msm8916-pins.dtsi"