2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
17 #include <dt-bindings/clock/qcom,rpmcc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 model = "Qualcomm Technologies, Inc. MSM8916";
22 compatible = "qcom,msm8916";
24 interrupt-parent = <&intc>;
30 mmc0 = &sdhc_1; /* SDC1 eMMC slot */
31 mmc1 = &sdhc_2; /* SDC2 SD card slot */
37 device_type = "memory";
38 /* We expect the bootloader to fill in the reg */
48 reg = <0x0 0x86000000 0x0 0x300000>;
52 smem_mem: smem_region@86300000 {
53 reg = <0x0 0x86300000 0x0 0x100000>;
58 reg = <0x0 0x86400000 0x0 0x100000>;
63 reg = <0x0 0x86500000 0x0 0x180000>;
68 reg = <0x0 0x86680000 0x0 0x80000>;
73 compatible = "qcom,rmtfs-mem";
74 reg = <0x0 0x86700000 0x0 0xe0000>;
81 reg = <0x0 0x867e0000 0x0 0x20000>;
85 mpss_mem: mpss@86800000 {
86 reg = <0x0 0x86800000 0x0 0x2b00000>;
90 wcnss_mem: wcnss@89300000 {
91 reg = <0x0 0x89300000 0x0 0x600000>;
95 venus_mem: venus@89900000 {
96 reg = <0x0 0x89900000 0x0 0x600000>;
100 mba_mem: mba@8ea00000 {
102 reg = <0 0x8ea00000 0 0x100000>;
107 #address-cells = <1>;
112 compatible = "arm,cortex-a53", "arm,armv8";
114 next-level-cache = <&L2_0>;
115 enable-method = "psci";
116 cpu-idle-states = <&CPU_SPC>;
118 operating-points-v2 = <&cpu_opp_table>;
119 #cooling-cells = <2>;
124 compatible = "arm,cortex-a53", "arm,armv8";
126 next-level-cache = <&L2_0>;
127 enable-method = "psci";
128 cpu-idle-states = <&CPU_SPC>;
130 operating-points-v2 = <&cpu_opp_table>;
131 #cooling-cells = <2>;
136 compatible = "arm,cortex-a53", "arm,armv8";
138 next-level-cache = <&L2_0>;
139 enable-method = "psci";
140 cpu-idle-states = <&CPU_SPC>;
142 operating-points-v2 = <&cpu_opp_table>;
143 #cooling-cells = <2>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 next-level-cache = <&L2_0>;
151 enable-method = "psci";
152 cpu-idle-states = <&CPU_SPC>;
154 operating-points-v2 = <&cpu_opp_table>;
155 #cooling-cells = <2>;
159 compatible = "cache";
165 compatible = "arm,idle-state";
166 arm,psci-suspend-param = <0x40000002>;
167 entry-latency-us = <130>;
168 exit-latency-us = <150>;
169 min-residency-us = <2000>;
176 compatible = "arm,psci-1.0";
181 compatible = "arm,cortex-a53-pmu";
182 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
187 polling-delay-passive = <250>;
188 polling-delay = <1000>;
190 thermal-sensors = <&tsens 4>;
194 temperature = <75000>;
199 temperature = <110000>;
207 trip = <&cpu_alert0>;
208 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
214 polling-delay-passive = <250>;
215 polling-delay = <1000>;
217 thermal-sensors = <&tsens 3>;
221 temperature = <75000>;
226 temperature = <110000>;
234 trip = <&cpu_alert1>;
235 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
242 cpu_opp_table: cpu_opp_table {
243 compatible = "operating-points-v2";
247 opp-hz = /bits/ 64 <200000000>;
250 opp-hz = /bits/ 64 <400000000>;
253 opp-hz = /bits/ 64 <800000000>;
256 opp-hz = /bits/ 64 <998400000>;
260 gpu_opp_table: opp_table {
261 compatible = "operating-points-v2";
264 opp-hz = /bits/ 64 <400000000>;
267 opp-hz = /bits/ 64 <19200000>;
272 compatible = "arm,armv8-timer";
273 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
274 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
275 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
276 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
281 compatible = "fixed-clock";
283 clock-frequency = <19200000>;
286 sleep_clk: sleep_clk {
287 compatible = "fixed-clock";
289 clock-frequency = <32768>;
294 compatible = "qcom,smem";
296 memory-region = <&smem_mem>;
297 qcom,rpm-msg-ram = <&rpm_msg_ram>;
299 hwlocks = <&tcsr_mutex 3>;
304 compatible = "qcom,scm";
305 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
306 clock-names = "core", "bus", "iface";
309 qcom,dload-mode = <&tcsr 0x6100>;
314 #address-cells = <1>;
316 ranges = <0 0 0 0xffffffff>;
317 compatible = "simple-bus";
320 compatible = "qcom,pshold";
321 reg = <0x4ab000 0x4>;
324 msmgpio: pinctrl@1000000 {
325 compatible = "qcom,msm8916-pinctrl";
326 reg = <0x1000000 0x300000>;
327 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
334 gcc: clock-controller@1800000 {
335 compatible = "qcom,gcc-msm8916";
338 #power-domain-cells = <1>;
339 reg = <0x1800000 0x80000>;
342 tcsr_mutex_regs: syscon@1905000 {
343 compatible = "syscon";
344 reg = <0x1905000 0x20000>;
347 tcsr: syscon@1937000 {
348 compatible = "qcom,tcsr-msm8916", "syscon";
349 reg = <0x1937000 0x30000>;
353 compatible = "qcom,tcsr-mutex";
354 syscon = <&tcsr_mutex_regs 0 0x1000>;
358 rpm_msg_ram: memory@60000 {
359 compatible = "qcom,rpm-msg-ram";
360 reg = <0x60000 0x8000>;
363 blsp1_uart1: serial@78af000 {
364 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
365 reg = <0x78af000 0x200>;
366 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
368 clock-names = "core", "iface";
369 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
370 dma-names = "rx", "tx";
374 a53pll: clock@b016000 {
375 compatible = "qcom,msm8916-a53pll";
376 reg = <0xb016000 0x40>;
380 apcs: mailbox@b011000 {
381 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
382 reg = <0xb011000 0x1000>;
388 blsp1_uart2: serial@78b0000 {
389 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
390 reg = <0x78b0000 0x200>;
391 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
393 clock-names = "core", "iface";
394 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
395 dma-names = "rx", "tx";
399 blsp_dma: dma@7884000 {
400 compatible = "qcom,bam-v1.7.0";
401 reg = <0x07884000 0x23000>;
402 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
404 clock-names = "bam_clk";
410 blsp_spi1: spi@78b5000 {
411 compatible = "qcom,spi-qup-v2.2.1";
412 reg = <0x078b5000 0x500>;
413 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
415 <&gcc GCC_BLSP1_AHB_CLK>;
416 clock-names = "core", "iface";
417 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
418 dma-names = "rx", "tx";
419 pinctrl-names = "default", "sleep";
420 pinctrl-0 = <&spi1_default>;
421 pinctrl-1 = <&spi1_sleep>;
422 #address-cells = <1>;
427 blsp_spi2: spi@78b6000 {
428 compatible = "qcom,spi-qup-v2.2.1";
429 reg = <0x078b6000 0x500>;
430 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
432 <&gcc GCC_BLSP1_AHB_CLK>;
433 clock-names = "core", "iface";
434 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
435 dma-names = "rx", "tx";
436 pinctrl-names = "default", "sleep";
437 pinctrl-0 = <&spi2_default>;
438 pinctrl-1 = <&spi2_sleep>;
439 #address-cells = <1>;
444 blsp_spi3: spi@78b7000 {
445 compatible = "qcom,spi-qup-v2.2.1";
446 reg = <0x078b7000 0x500>;
447 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
449 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", "iface";
451 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
452 dma-names = "rx", "tx";
453 pinctrl-names = "default", "sleep";
454 pinctrl-0 = <&spi3_default>;
455 pinctrl-1 = <&spi3_sleep>;
456 #address-cells = <1>;
461 blsp_spi4: spi@78b8000 {
462 compatible = "qcom,spi-qup-v2.2.1";
463 reg = <0x078b8000 0x500>;
464 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
466 <&gcc GCC_BLSP1_AHB_CLK>;
467 clock-names = "core", "iface";
468 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
469 dma-names = "rx", "tx";
470 pinctrl-names = "default", "sleep";
471 pinctrl-0 = <&spi4_default>;
472 pinctrl-1 = <&spi4_sleep>;
473 #address-cells = <1>;
478 blsp_spi5: spi@78b9000 {
479 compatible = "qcom,spi-qup-v2.2.1";
480 reg = <0x078b9000 0x500>;
481 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
483 <&gcc GCC_BLSP1_AHB_CLK>;
484 clock-names = "core", "iface";
485 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
486 dma-names = "rx", "tx";
487 pinctrl-names = "default", "sleep";
488 pinctrl-0 = <&spi5_default>;
489 pinctrl-1 = <&spi5_sleep>;
490 #address-cells = <1>;
495 blsp_spi6: spi@78ba000 {
496 compatible = "qcom,spi-qup-v2.2.1";
497 reg = <0x078ba000 0x500>;
498 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", "iface";
502 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
503 dma-names = "rx", "tx";
504 pinctrl-names = "default", "sleep";
505 pinctrl-0 = <&spi6_default>;
506 pinctrl-1 = <&spi6_sleep>;
507 #address-cells = <1>;
512 blsp_i2c2: i2c@78b6000 {
513 compatible = "qcom,i2c-qup-v2.2.1";
514 reg = <0x078b6000 0x500>;
515 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
517 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
518 clock-names = "iface", "core";
519 pinctrl-names = "default", "sleep";
520 pinctrl-0 = <&i2c2_default>;
521 pinctrl-1 = <&i2c2_sleep>;
522 #address-cells = <1>;
527 blsp_i2c4: i2c@78b8000 {
528 compatible = "qcom,i2c-qup-v2.2.1";
529 reg = <0x078b8000 0x500>;
530 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
532 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
533 clock-names = "iface", "core";
534 pinctrl-names = "default", "sleep";
535 pinctrl-0 = <&i2c4_default>;
536 pinctrl-1 = <&i2c4_sleep>;
537 #address-cells = <1>;
542 blsp_i2c6: i2c@78ba000 {
543 compatible = "qcom,i2c-qup-v2.2.1";
544 reg = <0x078ba000 0x500>;
545 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
547 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
548 clock-names = "iface", "core";
549 pinctrl-names = "default", "sleep";
550 pinctrl-0 = <&i2c6_default>;
551 pinctrl-1 = <&i2c6_sleep>;
552 #address-cells = <1>;
557 lpass: lpass@7708000 {
559 compatible = "qcom,lpass-cpu-apq8016";
560 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
561 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
562 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
563 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
564 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
565 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
566 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
568 clock-names = "ahbix-clk",
575 #sound-dai-cells = <1>;
577 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
578 interrupt-names = "lpass-irq-lpaif";
579 reg = <0x07708000 0x10000>;
580 reg-names = "lpass-lpaif";
584 compatible = "qcom,msm8916-wcd-digital-codec";
585 reg = <0x0771c000 0x400>;
586 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
587 <&gcc GCC_CODEC_DIGCODEC_CLK>;
588 clock-names = "ahbix-clk", "mclk";
589 #sound-dai-cells = <1>;
592 sdhc_1: sdhci@7824000 {
593 compatible = "qcom,sdhci-msm-v4";
594 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
595 reg-names = "hc_mem", "core_mem";
597 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
598 interrupt-names = "hc_irq", "pwr_irq";
599 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
600 <&gcc GCC_SDCC1_AHB_CLK>,
602 clock-names = "core", "iface", "xo";
609 sdhc_2: sdhci@7864000 {
610 compatible = "qcom,sdhci-msm-v4";
611 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
612 reg-names = "hc_mem", "core_mem";
614 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "hc_irq", "pwr_irq";
616 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
617 <&gcc GCC_SDCC2_AHB_CLK>,
619 clock-names = "core", "iface", "xo";
625 compatible = "qcom,ci-hdrc";
626 reg = <0x78d9000 0x200>,
628 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
631 <&gcc GCC_USB_HS_SYSTEM_CLK>;
632 clock-names = "iface", "core";
633 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
634 assigned-clock-rates = <80000000>;
635 resets = <&gcc GCC_USB_HS_BCR>;
636 reset-names = "core";
639 ahb-burst-config = <0>;
640 phy-names = "usb-phy";
641 phys = <&usb_hs_phy>;
647 compatible = "qcom,usb-hs-phy-msm8916",
650 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
651 clock-names = "ref", "sleep";
652 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
653 reset-names = "phy", "por";
654 qcom,init-seq = /bits/ 8 <0x0 0x44
655 0x1 0x6b 0x2 0x24 0x3 0x13>;
660 intc: interrupt-controller@b000000 {
661 compatible = "qcom,msm-qgic2";
662 interrupt-controller;
663 #interrupt-cells = <3>;
664 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
668 #address-cells = <1>;
671 compatible = "arm,armv7-timer-mem";
672 reg = <0xb020000 0x1000>;
673 clock-frequency = <19200000>;
677 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
679 reg = <0xb021000 0x1000>,
685 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
686 reg = <0xb023000 0x1000>;
692 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
693 reg = <0xb024000 0x1000>;
699 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
700 reg = <0xb025000 0x1000>;
706 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
707 reg = <0xb026000 0x1000>;
713 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
714 reg = <0xb027000 0x1000>;
720 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
721 reg = <0xb028000 0x1000>;
726 spmi_bus: spmi@200f000 {
727 compatible = "qcom,spmi-pmic-arb";
728 reg = <0x200f000 0x001000>,
729 <0x2400000 0x400000>,
730 <0x2c00000 0x400000>,
731 <0x3800000 0x200000>,
732 <0x200a000 0x002100>;
733 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
734 interrupt-names = "periph_irq";
735 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
738 #address-cells = <2>;
740 interrupt-controller;
741 #interrupt-cells = <4>;
745 compatible = "qcom,prng";
746 reg = <0x00022000 0x200>;
747 clocks = <&gcc GCC_PRNG_AHB_CLK>;
748 clock-names = "core";
751 qfprom: qfprom@5c000 {
752 compatible = "qcom,qfprom";
753 reg = <0x5c000 0x1000>;
754 #address-cells = <1>;
756 tsens_caldata: caldata@d0 {
759 tsens_calsel: calsel@ec {
764 tsens: thermal-sensor@4a8000 {
765 compatible = "qcom,msm8916-tsens";
766 reg = <0x4a8000 0x2000>;
767 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
768 nvmem-cell-names = "calib", "calib_sel";
769 #thermal-sensor-cells = <1>;
772 apps_iommu: iommu@1ef0000 {
773 #address-cells = <1>;
776 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
777 ranges = <0 0x1e20000 0x40000>;
778 reg = <0x1ef0000 0x3000>;
779 clocks = <&gcc GCC_SMMU_CFG_CLK>,
780 <&gcc GCC_APSS_TCU_CLK>;
781 clock-names = "iface", "bus";
782 qcom,iommu-secure-id = <17>;
786 compatible = "qcom,msm-iommu-v1-ns";
787 reg = <0x4000 0x1000>;
788 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
793 compatible = "qcom,msm-iommu-v1-sec";
794 reg = <0x5000 0x1000>;
795 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
799 gpu_iommu: iommu@1f08000 {
800 #address-cells = <1>;
803 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
804 ranges = <0 0x1f08000 0x10000>;
805 clocks = <&gcc GCC_SMMU_CFG_CLK>,
806 <&gcc GCC_GFX_TCU_CLK>;
807 clock-names = "iface", "bus";
808 qcom,iommu-secure-id = <18>;
812 compatible = "qcom,msm-iommu-v1-ns";
813 reg = <0x1000 0x1000>;
814 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
819 compatible = "qcom,msm-iommu-v1-ns";
820 reg = <0x2000 0x1000>;
821 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
826 compatible = "qcom,adreno-306.0", "qcom,adreno";
827 reg = <0x01c00000 0x20000>;
828 reg-names = "kgsl_3d0_reg_memory";
829 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
830 interrupt-names = "kgsl_3d0_irq";
839 <&gcc GCC_OXILI_GFX3D_CLK>,
840 <&gcc GCC_OXILI_AHB_CLK>,
841 <&gcc GCC_OXILI_GMEM_CLK>,
842 <&gcc GCC_BIMC_GFX_CLK>,
843 <&gcc GCC_BIMC_GPU_CLK>,
844 <&gcc GFX3D_CLK_SRC>;
845 power-domains = <&gcc OXILI_GDSC>;
846 operating-points-v2 = <&gpu_opp_table>;
847 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
851 compatible = "qcom,mdss";
852 reg = <0x1a00000 0x1000>,
854 reg-names = "mdss_phys", "vbif_phys";
856 power-domains = <&gcc MDSS_GDSC>;
858 clocks = <&gcc GCC_MDSS_AHB_CLK>,
859 <&gcc GCC_MDSS_AXI_CLK>,
860 <&gcc GCC_MDSS_VSYNC_CLK>;
861 clock-names = "iface",
865 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
867 interrupt-controller;
868 #interrupt-cells = <1>;
870 #address-cells = <1>;
875 compatible = "qcom,mdp5";
876 reg = <0x1a01000 0x89000>;
877 reg-names = "mdp_phys";
879 interrupt-parent = <&mdss>;
882 clocks = <&gcc GCC_MDSS_AHB_CLK>,
883 <&gcc GCC_MDSS_AXI_CLK>,
884 <&gcc GCC_MDSS_MDP_CLK>,
885 <&gcc GCC_MDSS_VSYNC_CLK>;
886 clock-names = "iface",
891 iommus = <&apps_iommu 4>;
894 #address-cells = <1>;
899 mdp5_intf1_out: endpoint {
900 remote-endpoint = <&dsi0_in>;
907 compatible = "qcom,mdss-dsi-ctrl";
908 reg = <0x1a98000 0x25c>;
909 reg-names = "dsi_ctrl";
911 interrupt-parent = <&mdss>;
914 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
915 <&gcc PCLK0_CLK_SRC>;
916 assigned-clock-parents = <&dsi_phy0 0>,
919 clocks = <&gcc GCC_MDSS_MDP_CLK>,
920 <&gcc GCC_MDSS_AHB_CLK>,
921 <&gcc GCC_MDSS_AXI_CLK>,
922 <&gcc GCC_MDSS_BYTE0_CLK>,
923 <&gcc GCC_MDSS_PCLK0_CLK>,
924 <&gcc GCC_MDSS_ESC0_CLK>;
925 clock-names = "mdp_core",
932 phy-names = "dsi-phy";
935 #address-cells = <1>;
941 remote-endpoint = <&mdp5_intf1_out>;
953 dsi_phy0: dsi-phy@1a98300 {
954 compatible = "qcom,dsi-phy-28nm-lp";
955 reg = <0x1a98300 0xd4>,
958 reg-names = "dsi_pll",
965 clocks = <&gcc GCC_MDSS_AHB_CLK>;
966 clock-names = "iface";
972 compatible = "qcom,q6v5-pil";
973 reg = <0x04080000 0x100>,
976 reg-names = "qdsp6", "rmb";
978 interrupts-extended = <&intc 0 24 1>,
979 <&hexagon_smp2p_in 0 0>,
980 <&hexagon_smp2p_in 1 0>,
981 <&hexagon_smp2p_in 2 0>,
982 <&hexagon_smp2p_in 3 0>;
983 interrupt-names = "wdog", "fatal", "ready",
984 "handover", "stop-ack";
986 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
987 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
988 <&gcc GCC_BOOT_ROM_AHB_CLK>,
990 clock-names = "iface", "bus", "mem", "xo";
992 qcom,smem-states = <&hexagon_smp2p_out 0>;
993 qcom,smem-state-names = "stop";
996 reset-names = "mss_restart";
998 cx-supply = <&pm8916_s1>;
999 mx-supply = <&pm8916_l3>;
1000 pll-supply = <&pm8916_l7>;
1002 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1004 status = "disabled";
1007 memory-region = <&mba_mem>;
1011 memory-region = <&mpss_mem>;
1015 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1017 qcom,smd-edge = <0>;
1018 qcom,ipc = <&apcs 8 12>;
1019 qcom,remote-pid = <1>;
1025 pronto: wcnss@a21b000 {
1026 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1027 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1028 reg-names = "ccu", "dxe", "pmu";
1030 memory-region = <&wcnss_mem>;
1032 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1033 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1034 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1035 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1036 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1037 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1039 vddmx-supply = <&pm8916_l3>;
1040 vddpx-supply = <&pm8916_l7>;
1042 qcom,smem-states = <&wcnss_smp2p_out 0>;
1043 qcom,smem-state-names = "stop";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&wcnss_pin_a>;
1048 status = "disabled";
1051 compatible = "qcom,wcn3620";
1053 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1056 vddxo-supply = <&pm8916_l7>;
1057 vddrfa-supply = <&pm8916_s3>;
1058 vddpa-supply = <&pm8916_l9>;
1059 vdddig-supply = <&pm8916_l5>;
1063 interrupts = <0 142 1>;
1065 qcom,ipc = <&apcs 8 17>;
1066 qcom,smd-edge = <6>;
1067 qcom,remote-pid = <4>;
1072 compatible = "qcom,wcnss";
1073 qcom,smd-channels = "WCNSS_CTRL";
1075 qcom,mmio = <&pronto>;
1078 compatible = "qcom,wcnss-bt";
1082 compatible = "qcom,wcnss-wlan";
1084 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1085 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1086 interrupt-names = "tx", "rx";
1088 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1089 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1096 compatible = "arm,coresight-tpiu", "arm,primecell";
1097 reg = <0x820000 0x1000>;
1099 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1100 clock-names = "apb_pclk", "atclk";
1105 remote-endpoint = <&replicator_out1>;
1111 compatible = "arm,coresight-funnel", "arm,primecell";
1112 reg = <0x821000 0x1000>;
1114 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1115 clock-names = "apb_pclk", "atclk";
1118 #address-cells = <1>;
1122 * Not described input ports:
1123 * 0 - connected to Resource and Power Manger CPU ETM
1125 * 2 - connected to Modem CPU ETM
1128 * 6 - connected trought funnel to Wireless CPU ETM
1129 * 7 - connected to STM component
1134 funnel0_in4: endpoint {
1136 remote-endpoint = <&funnel1_out>;
1141 funnel0_out: endpoint {
1142 remote-endpoint = <&etf_in>;
1149 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1150 reg = <0x824000 0x1000>;
1152 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1153 clock-names = "apb_pclk", "atclk";
1156 #address-cells = <1>;
1161 replicator_out0: endpoint {
1162 remote-endpoint = <&etr_in>;
1167 replicator_out1: endpoint {
1168 remote-endpoint = <&tpiu_in>;
1173 replicator_in: endpoint {
1175 remote-endpoint = <&etf_out>;
1182 compatible = "arm,coresight-tmc", "arm,primecell";
1183 reg = <0x825000 0x1000>;
1185 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1186 clock-names = "apb_pclk", "atclk";
1189 #address-cells = <1>;
1196 remote-endpoint = <&funnel0_out>;
1202 remote-endpoint = <&replicator_in>;
1209 compatible = "arm,coresight-tmc", "arm,primecell";
1210 reg = <0x826000 0x1000>;
1212 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1213 clock-names = "apb_pclk", "atclk";
1218 remote-endpoint = <&replicator_out0>;
1223 funnel@841000 { /* APSS funnel only 4 inputs are used */
1224 compatible = "arm,coresight-funnel", "arm,primecell";
1225 reg = <0x841000 0x1000>;
1227 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1228 clock-names = "apb_pclk", "atclk";
1231 #address-cells = <1>;
1236 funnel1_in0: endpoint {
1238 remote-endpoint = <&etm0_out>;
1243 funnel1_in1: endpoint {
1245 remote-endpoint = <&etm1_out>;
1250 funnel1_in2: endpoint {
1252 remote-endpoint = <&etm2_out>;
1257 funnel1_in3: endpoint {
1259 remote-endpoint = <&etm3_out>;
1264 funnel1_out: endpoint {
1265 remote-endpoint = <&funnel0_in4>;
1272 compatible = "arm,coresight-cpu-debug","arm,primecell";
1273 reg = <0x850000 0x1000>;
1274 clocks = <&rpmcc RPM_QDSS_CLK>;
1275 clock-names = "apb_pclk";
1280 compatible = "arm,coresight-cpu-debug","arm,primecell";
1281 reg = <0x852000 0x1000>;
1282 clocks = <&rpmcc RPM_QDSS_CLK>;
1283 clock-names = "apb_pclk";
1288 compatible = "arm,coresight-cpu-debug","arm,primecell";
1289 reg = <0x854000 0x1000>;
1290 clocks = <&rpmcc RPM_QDSS_CLK>;
1291 clock-names = "apb_pclk";
1296 compatible = "arm,coresight-cpu-debug","arm,primecell";
1297 reg = <0x856000 0x1000>;
1298 clocks = <&rpmcc RPM_QDSS_CLK>;
1299 clock-names = "apb_pclk";
1304 compatible = "arm,coresight-etm4x", "arm,primecell";
1305 reg = <0x85c000 0x1000>;
1307 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1308 clock-names = "apb_pclk", "atclk";
1313 etm0_out: endpoint {
1314 remote-endpoint = <&funnel1_in0>;
1320 compatible = "arm,coresight-etm4x", "arm,primecell";
1321 reg = <0x85d000 0x1000>;
1323 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1324 clock-names = "apb_pclk", "atclk";
1329 etm1_out: endpoint {
1330 remote-endpoint = <&funnel1_in1>;
1336 compatible = "arm,coresight-etm4x", "arm,primecell";
1337 reg = <0x85e000 0x1000>;
1339 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1340 clock-names = "apb_pclk", "atclk";
1345 etm2_out: endpoint {
1346 remote-endpoint = <&funnel1_in2>;
1352 compatible = "arm,coresight-etm4x", "arm,primecell";
1353 reg = <0x85f000 0x1000>;
1355 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1356 clock-names = "apb_pclk", "atclk";
1361 etm3_out: endpoint {
1362 remote-endpoint = <&funnel1_in3>;
1367 venus: video-codec@1d00000 {
1368 compatible = "qcom,msm8916-venus";
1369 reg = <0x01d00000 0xff000>;
1370 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1371 power-domains = <&gcc VENUS_GDSC>;
1372 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1373 <&gcc GCC_VENUS0_AHB_CLK>,
1374 <&gcc GCC_VENUS0_AXI_CLK>;
1375 clock-names = "core", "iface", "bus";
1376 iommus = <&apps_iommu 5>;
1377 memory-region = <&venus_mem>;
1381 compatible = "venus-decoder";
1385 compatible = "venus-encoder";
1391 compatible = "qcom,smd";
1394 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1395 qcom,ipc = <&apcs 8 0>;
1396 qcom,smd-edge = <15>;
1399 compatible = "qcom,rpm-msm8916";
1400 qcom,smd-channels = "rpm_requests";
1403 compatible = "qcom,rpmcc-msm8916";
1407 smd_rpm_regulators: pm8916-regulators {
1408 compatible = "qcom,rpm-pm8916-regulators";
1438 compatible = "qcom,smp2p";
1439 qcom,smem = <435>, <428>;
1441 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1443 qcom,ipc = <&apcs 8 14>;
1445 qcom,local-pid = <0>;
1446 qcom,remote-pid = <1>;
1448 hexagon_smp2p_out: master-kernel {
1449 qcom,entry-name = "master-kernel";
1451 #qcom,smem-state-cells = <1>;
1454 hexagon_smp2p_in: slave-kernel {
1455 qcom,entry-name = "slave-kernel";
1457 interrupt-controller;
1458 #interrupt-cells = <2>;
1463 compatible = "qcom,smp2p";
1464 qcom,smem = <451>, <431>;
1466 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1468 qcom,ipc = <&apcs 8 18>;
1470 qcom,local-pid = <0>;
1471 qcom,remote-pid = <4>;
1473 wcnss_smp2p_out: master-kernel {
1474 qcom,entry-name = "master-kernel";
1476 #qcom,smem-state-cells = <1>;
1479 wcnss_smp2p_in: slave-kernel {
1480 qcom,entry-name = "slave-kernel";
1482 interrupt-controller;
1483 #interrupt-cells = <2>;
1488 compatible = "qcom,smsm";
1490 #address-cells = <1>;
1493 qcom,ipc-1 = <&apcs 8 13>;
1494 qcom,ipc-3 = <&apcs 8 19>;
1499 #qcom,smem-state-cells = <1>;
1502 hexagon_smsm: hexagon@1 {
1504 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1506 interrupt-controller;
1507 #interrupt-cells = <2>;
1510 wcnss_smsm: wcnss@6 {
1512 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1514 interrupt-controller;
1515 #interrupt-cells = <2>;
1520 #include "msm8916-pins.dtsi"