1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ9574 SoC device tree source
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
21 sleep_clk: sleep-clk {
22 compatible = "fixed-clock";
26 xo_board_clk: xo-board-clk {
27 compatible = "fixed-clock";
38 compatible = "arm,cortex-a73";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq9574_s1>;
51 compatible = "arm,cortex-a73";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
57 operating-points-v2 = <&cpu_opp_table>;
58 cpu-supply = <&ipq9574_s1>;
64 compatible = "arm,cortex-a73";
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
70 operating-points-v2 = <&cpu_opp_table>;
71 cpu-supply = <&ipq9574_s1>;
77 compatible = "arm,cortex-a73";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
83 operating-points-v2 = <&cpu_opp_table>;
84 cpu-supply = <&ipq9574_s1>;
97 compatible = "qcom,scm-ipq9574", "qcom,scm";
98 qcom,dload-mode = <&tcsr 0x6100>;
103 device_type = "memory";
104 /* We expect the bootloader to fill in the size */
105 reg = <0x0 0x40000000 0x0 0x0>;
108 cpu_opp_table: opp-table-cpu {
109 compatible = "operating-points-v2";
113 opp-hz = /bits/ 64 <936000000>;
114 opp-microvolt = <725000>;
115 clock-latency-ns = <200000>;
119 opp-hz = /bits/ 64 <1104000000>;
120 opp-microvolt = <787500>;
121 clock-latency-ns = <200000>;
125 opp-hz = /bits/ 64 <1416000000>;
126 opp-microvolt = <862500>;
127 clock-latency-ns = <200000>;
131 opp-hz = /bits/ 64 <1488000000>;
132 opp-microvolt = <925000>;
133 clock-latency-ns = <200000>;
137 opp-hz = /bits/ 64 <1800000000>;
138 opp-microvolt = <987500>;
139 clock-latency-ns = <200000>;
143 opp-hz = /bits/ 64 <2208000000>;
144 opp-microvolt = <1062500>;
145 clock-latency-ns = <200000>;
150 compatible = "arm,cortex-a73-pmu";
151 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
155 compatible = "arm,psci-1.0";
160 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
163 compatible = "qcom,glink-rpm";
164 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
165 qcom,rpm-msg-ram = <&rpm_msg_ram>;
166 mboxes = <&apcs_glb 0>;
168 rpm_requests: rpm-requests {
169 compatible = "qcom,rpm-ipq9574";
170 qcom,glink-channels = "rpm_requests";
176 #address-cells = <2>;
180 bootloader@4a100000 {
181 reg = <0x0 0x4a100000 0x0 0x400000>;
186 reg = <0x0 0x4a500000 0x0 0x100000>;
190 tz_region: tz@4a600000 {
191 reg = <0x0 0x4a600000 0x0 0x400000>;
196 compatible = "qcom,smem";
197 reg = <0x0 0x4aa00000 0x0 0x100000>;
198 hwlocks = <&tcsr_mutex 3>;
204 compatible = "simple-bus";
205 #address-cells = <1>;
207 ranges = <0 0 0 0xffffffff>;
209 rpm_msg_ram: sram@60000 {
210 compatible = "qcom,rpm-msg-ram";
211 reg = <0x00060000 0x6000>;
215 compatible = "qcom,prng-ee";
216 reg = <0x000e3000 0x1000>;
217 clocks = <&gcc GCC_PRNG_AHB_CLK>;
218 clock-names = "core";
221 qfprom: efuse@a4000 {
222 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
223 reg = <0x000a4000 0x5a1>;
224 #address-cells = <1>;
228 cryptobam: dma-controller@704000 {
229 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
230 reg = <0x00704000 0x20000>;
231 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
234 qcom,controlled-remotely;
237 crypto: crypto@73a000 {
238 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
239 reg = <0x0073a000 0x6000>;
240 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
241 <&gcc GCC_CRYPTO_AXI_CLK>,
242 <&gcc GCC_CRYPTO_CLK>;
243 clock-names = "iface", "bus", "core";
244 dmas = <&cryptobam 2>, <&cryptobam 3>;
245 dma-names = "rx", "tx";
248 tsens: thermal-sensor@4a9000 {
249 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
250 reg = <0x004a9000 0x1000>,
252 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
253 interrupt-names = "combined";
254 #qcom,sensors = <16>;
255 #thermal-sensor-cells = <1>;
258 tlmm: pinctrl@1000000 {
259 compatible = "qcom,ipq9574-tlmm";
260 reg = <0x01000000 0x300000>;
261 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
264 gpio-ranges = <&tlmm 0 0 65>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
268 uart2_pins: uart2-state {
269 pins = "gpio34", "gpio35";
270 function = "blsp2_uart";
271 drive-strength = <8>;
276 gcc: clock-controller@1800000 {
277 compatible = "qcom,ipq9574-gcc";
278 reg = <0x01800000 0x80000>;
279 clocks = <&xo_board_clk>,
289 #power-domain-cells = <1>;
292 tcsr_mutex: hwlock@1905000 {
293 compatible = "qcom,tcsr-mutex";
294 reg = <0x01905000 0x20000>;
298 tcsr: syscon@1937000 {
299 compatible = "qcom,tcsr-ipq9574", "syscon";
300 reg = <0x01937000 0x21000>;
303 sdhc_1: mmc@7804000 {
304 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
305 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
306 reg-names = "hc", "cqhci";
308 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-names = "hc_irq", "pwr_irq";
312 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
313 <&gcc GCC_SDCC1_APPS_CLK>,
315 clock-names = "iface", "core", "xo";
320 blsp_dma: dma-controller@7884000 {
321 compatible = "qcom,bam-v1.7.0";
322 reg = <0x07884000 0x2b000>;
323 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
325 clock-names = "bam_clk";
330 blsp1_uart0: serial@78af000 {
331 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
332 reg = <0x078af000 0x200>;
333 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
335 <&gcc GCC_BLSP1_AHB_CLK>;
336 clock-names = "core", "iface";
340 blsp1_uart1: serial@78b0000 {
341 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
342 reg = <0x078b0000 0x200>;
343 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
345 <&gcc GCC_BLSP1_AHB_CLK>;
346 clock-names = "core", "iface";
350 blsp1_uart2: serial@78b1000 {
351 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
352 reg = <0x078b1000 0x200>;
353 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
355 <&gcc GCC_BLSP1_AHB_CLK>;
356 clock-names = "core", "iface";
360 blsp1_uart3: serial@78b2000 {
361 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
362 reg = <0x078b2000 0x200>;
363 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
365 <&gcc GCC_BLSP1_AHB_CLK>;
366 clock-names = "core", "iface";
370 blsp1_uart4: serial@78b3000 {
371 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
372 reg = <0x078b3000 0x200>;
373 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
375 <&gcc GCC_BLSP1_AHB_CLK>;
376 clock-names = "core", "iface";
380 blsp1_uart5: serial@78b4000 {
381 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
382 reg = <0x078b4000 0x200>;
383 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
385 <&gcc GCC_BLSP1_AHB_CLK>;
386 clock-names = "core", "iface";
390 blsp1_spi0: spi@78b5000 {
391 compatible = "qcom,spi-qup-v2.2.1";
392 reg = <0x078b5000 0x600>;
393 #address-cells = <1>;
395 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
397 <&gcc GCC_BLSP1_AHB_CLK>;
398 clock-names = "core", "iface";
399 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
400 dma-names = "tx", "rx";
404 blsp1_i2c1: i2c@78b6000 {
405 compatible = "qcom,i2c-qup-v2.2.1";
406 reg = <0x078b6000 0x600>;
407 #address-cells = <1>;
409 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
411 <&gcc GCC_BLSP1_AHB_CLK>;
412 clock-names = "core", "iface";
413 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
414 assigned-clock-rates = <50000000>;
415 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
416 dma-names = "tx", "rx";
420 blsp1_spi1: spi@78b6000 {
421 compatible = "qcom,spi-qup-v2.2.1";
422 reg = <0x078b6000 0x600>;
423 #address-cells = <1>;
425 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
427 <&gcc GCC_BLSP1_AHB_CLK>;
428 clock-names = "core", "iface";
429 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
430 dma-names = "tx", "rx";
434 blsp1_i2c2: i2c@78b7000 {
435 compatible = "qcom,i2c-qup-v2.2.1";
436 reg = <0x078b7000 0x600>;
437 #address-cells = <1>;
439 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
441 <&gcc GCC_BLSP1_AHB_CLK>;
442 clock-names = "core", "iface";
443 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
444 assigned-clock-rates = <50000000>;
445 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
446 dma-names = "tx", "rx";
450 blsp1_spi2: spi@78b7000 {
451 compatible = "qcom,spi-qup-v2.2.1";
452 reg = <0x078b7000 0x600>;
453 #address-cells = <1>;
455 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
457 <&gcc GCC_BLSP1_AHB_CLK>;
458 clock-names = "core", "iface";
459 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
460 dma-names = "tx", "rx";
464 blsp1_i2c3: i2c@78b8000 {
465 compatible = "qcom,i2c-qup-v2.2.1";
466 reg = <0x078b8000 0x600>;
467 #address-cells = <1>;
469 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
471 <&gcc GCC_BLSP1_AHB_CLK>;
472 clock-names = "core", "iface";
473 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
474 assigned-clock-rates = <50000000>;
475 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
476 dma-names = "tx", "rx";
480 blsp1_spi3: spi@78b8000 {
481 compatible = "qcom,spi-qup-v2.2.1";
482 reg = <0x078b8000 0x600>;
483 #address-cells = <1>;
485 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
486 spi-max-frequency = <50000000>;
487 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
488 <&gcc GCC_BLSP1_AHB_CLK>;
489 clock-names = "core", "iface";
490 dmas = <&blsp_dma 18>, <&blsp_dma 19>;
491 dma-names = "tx", "rx";
495 blsp1_i2c4: i2c@78b9000 {
496 compatible = "qcom,i2c-qup-v2.2.1";
497 reg = <0x078b9000 0x600>;
498 #address-cells = <1>;
500 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
502 <&gcc GCC_BLSP1_AHB_CLK>;
503 clock-names = "core", "iface";
504 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
505 assigned-clock-rates = <50000000>;
506 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
507 dma-names = "tx", "rx";
511 blsp1_spi4: spi@78b9000 {
512 compatible = "qcom,spi-qup-v2.2.1";
513 reg = <0x078b9000 0x600>;
514 #address-cells = <1>;
516 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
518 <&gcc GCC_BLSP1_AHB_CLK>;
519 clock-names = "core", "iface";
520 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
521 dma-names = "tx", "rx";
525 usb_0_qusbphy: phy@7b000 {
526 compatible = "qcom,ipq9574-qusb2-phy";
527 reg = <0x0007b000 0x180>;
530 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
532 clock-names = "cfg_ahb",
535 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
539 usb_0_qmpphy: phy@7d000 {
540 compatible = "qcom,ipq9574-qmp-usb3-phy";
541 reg = <0x0007d000 0xa00>;
544 clocks = <&gcc GCC_USB0_AUX_CLK>,
546 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
547 <&gcc GCC_USB0_PIPE_CLK>;
553 resets = <&gcc GCC_USB0_PHY_BCR>,
554 <&gcc GCC_USB3PHY_0_PHY_BCR>;
559 clock-output-names = "usb0_pipe_clk";
565 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
566 reg = <0x08af8800 0x400>;
567 #address-cells = <1>;
571 clocks = <&gcc GCC_SNOC_USB_CLK>,
572 <&gcc GCC_USB0_MASTER_CLK>,
573 <&gcc GCC_ANOC_USB_AXI_CLK>,
574 <&gcc GCC_USB0_SLEEP_CLK>,
575 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
577 clock-names = "cfg_noc",
583 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
584 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
585 assigned-clock-rates = <200000000>,
588 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-names = "pwr_event";
591 resets = <&gcc GCC_USB_BCR>;
594 usb_0_dwc3: usb@8a00000 {
595 compatible = "snps,dwc3";
596 reg = <0x8a00000 0xcd00>;
597 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
599 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
600 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>;
601 phy-names = "usb2-phy", "usb3-phy";
603 snps,is-utmi-l1-suspend;
604 snps,hird-threshold = /bits/ 8 <0x0>;
605 snps,dis_u2_susphy_quirk;
606 snps,dis_u3_susphy_quirk;
610 intc: interrupt-controller@b000000 {
611 compatible = "qcom,msm-qgic2";
612 reg = <0x0b000000 0x1000>, /* GICD */
613 <0x0b002000 0x2000>, /* GICC */
614 <0x0b001000 0x1000>, /* GICH */
615 <0x0b004000 0x2000>; /* GICV */
616 #address-cells = <1>;
618 interrupt-controller;
619 #interrupt-cells = <3>;
620 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
621 ranges = <0 0x0b00c000 0x3000>;
624 compatible = "arm,gic-v2m-frame";
625 reg = <0x00000000 0xffd>;
630 compatible = "arm,gic-v2m-frame";
631 reg = <0x00001000 0xffd>;
636 compatible = "arm,gic-v2m-frame";
637 reg = <0x00002000 0xffd>;
642 watchdog: watchdog@b017000 {
643 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
644 reg = <0x0b017000 0x1000>;
645 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
646 clocks = <&sleep_clk>;
650 apcs_glb: mailbox@b111000 {
651 compatible = "qcom,ipq9574-apcs-apps-global",
652 "qcom,ipq6018-apcs-apps-global";
653 reg = <0x0b111000 0x1000>;
655 clocks = <&a73pll>, <&xo_board_clk>;
656 clock-names = "pll", "xo";
660 a73pll: clock@b116000 {
661 compatible = "qcom,ipq9574-a73pll";
662 reg = <0x0b116000 0x40>;
664 clocks = <&xo_board_clk>;
669 compatible = "arm,armv7-timer-mem";
670 reg = <0x0b120000 0x1000>;
671 #address-cells = <1>;
676 reg = <0x0b121000 0x1000>,
679 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
684 reg = <0x0b123000 0x1000>;
686 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
691 reg = <0x0b124000 0x1000>;
693 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
698 reg = <0x0b125000 0x1000>;
700 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
705 reg = <0x0b126000 0x1000>;
707 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
712 reg = <0x0b127000 0x1000>;
714 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
719 reg = <0x0b128000 0x1000>;
721 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
729 polling-delay-passive = <0>;
731 thermal-sensors = <&tsens 3>;
735 temperature = <125000>;
743 polling-delay-passive = <0>;
745 thermal-sensors = <&tsens 4>;
749 temperature = <125000>;
757 polling-delay-passive = <0>;
759 thermal-sensors = <&tsens 5>;
763 temperature = <125000>;
771 polling-delay-passive = <0>;
773 thermal-sensors = <&tsens 6>;
777 temperature = <125000>;
785 polling-delay-passive = <0>;
787 thermal-sensors = <&tsens 7>;
791 temperature = <125000>;
799 polling-delay-passive = <0>;
801 thermal-sensors = <&tsens 8>;
805 temperature = <125000>;
813 polling-delay-passive = <0>;
815 thermal-sensors = <&tsens 9>;
819 temperature = <125000>;
827 polling-delay-passive = <0>;
829 thermal-sensors = <&tsens 10>;
832 cpu0_crit: cpu-critical {
833 temperature = <120000>;
834 hysteresis = <10000>;
838 cpu0_alert: cpu-passive {
839 temperature = <110000>;
847 trip = <&cpu0_alert>;
848 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
849 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
850 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
851 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
857 polling-delay-passive = <0>;
859 thermal-sensors = <&tsens 11>;
862 cpu1_crit: cpu-critical {
863 temperature = <120000>;
864 hysteresis = <10000>;
868 cpu1_alert: cpu-passive {
869 temperature = <110000>;
877 trip = <&cpu1_alert>;
878 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
879 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
880 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
881 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
887 polling-delay-passive = <0>;
889 thermal-sensors = <&tsens 12>;
892 cpu2_crit: cpu-critical {
893 temperature = <120000>;
894 hysteresis = <10000>;
898 cpu2_alert: cpu-passive {
899 temperature = <110000>;
907 trip = <&cpu2_alert>;
908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
917 polling-delay-passive = <0>;
919 thermal-sensors = <&tsens 13>;
922 cpu3_crit: cpu-critical {
923 temperature = <120000>;
924 hysteresis = <10000>;
928 cpu3_alert: cpu-passive {
929 temperature = <110000>;
937 trip = <&cpu3_alert>;
938 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
939 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
940 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
941 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
947 polling-delay-passive = <0>;
949 thermal-sensors = <&tsens 14>;
953 temperature = <125000>;
961 polling-delay-passive = <0>;
963 thermal-sensors = <&tsens 15>;
967 temperature = <125000>;
976 compatible = "arm,armv8-timer";
977 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
978 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
979 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
980 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;