arm64: dts: qcom: sm8550: add TRNG node
[linux-modified.git] / arch / arm64 / boot / dts / qcom / ipq9574-rdp418.dts
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * IPQ9574 RDP418 board device tree source
4  *
5  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
7  */
8
9 /dts-v1/;
10
11 #include "ipq9574.dtsi"
12
13 / {
14         model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
15         compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
16
17         aliases {
18                 serial0 = &blsp1_uart2;
19         };
20
21         chosen {
22                 stdout-path = "serial0:115200n8";
23         };
24 };
25
26 &blsp1_spi0 {
27         pinctrl-0 = <&spi_0_pins>;
28         pinctrl-names = "default";
29         status = "okay";
30
31         flash@0 {
32                 compatible = "micron,n25q128a11", "jedec,spi-nor";
33                 reg = <0>;
34                 #address-cells = <1>;
35                 #size-cells = <1>;
36                 spi-max-frequency = <50000000>;
37         };
38 };
39
40 &blsp1_uart2 {
41         pinctrl-0 = <&uart2_pins>;
42         pinctrl-names = "default";
43         status = "okay";
44 };
45
46 &rpm_requests {
47         regulators {
48                 compatible = "qcom,rpm-mp5496-regulators";
49
50                 ipq9574_s1: s1 {
51                 /*
52                  * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
53                  * During regulator registration, kernel not knowing the initial voltage,
54                  * considers it as zero and brings up the regulators with minimum supported voltage.
55                  * Update the regulator-min-microvolt with SVS voltage of 725mV so that
56                  * the regulators are brought up with 725mV which is sufficient for all the
57                  * corner parts to operate at 800MHz
58                  */
59                         regulator-min-microvolt = <725000>;
60                         regulator-max-microvolt = <1075000>;
61                 };
62         };
63 };
64
65 &sdhc_1 {
66         pinctrl-0 = <&sdc_default_state>;
67         pinctrl-names = "default";
68         mmc-ddr-1_8v;
69         mmc-hs200-1_8v;
70         mmc-hs400-1_8v;
71         mmc-hs400-enhanced-strobe;
72         max-frequency = <384000000>;
73         bus-width = <8>;
74         status = "okay";
75 };
76
77 &sleep_clk {
78         clock-frequency = <32000>;
79 };
80
81 &tlmm {
82         sdc_default_state: sdc-default-state {
83                 clk-pins {
84                         pins = "gpio5";
85                         function = "sdc_clk";
86                         drive-strength = <8>;
87                         bias-disable;
88                 };
89
90                 cmd-pins {
91                         pins = "gpio4";
92                         function = "sdc_cmd";
93                         drive-strength = <8>;
94                         bias-pull-up;
95                 };
96
97                 data-pins {
98                         pins = "gpio0", "gpio1", "gpio2",
99                                "gpio3", "gpio6", "gpio7",
100                                "gpio8", "gpio9";
101                         function = "sdc_data";
102                         drive-strength = <8>;
103                         bias-pull-up;
104                 };
105
106                 rclk-pins {
107                         pins = "gpio10";
108                         function = "sdc_rclk";
109                         drive-strength = <8>;
110                         bias-pull-down;
111                 };
112         };
113
114         spi_0_pins: spi-0-state {
115                 pins = "gpio11", "gpio12", "gpio13", "gpio14";
116                 function = "blsp0_spi";
117                 drive-strength = <8>;
118                 bias-disable;
119         };
120 };
121
122 &xo_board_clk {
123         clock-frequency = <24000000>;
124 };