arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12
  13         model = "Qualcomm Technologies, Inc. IPQ8074";
  14         compatible = "qcom,ipq8074";
  15         interrupt-parent = <&intc>;
  16
  17         clocks {
  18                 sleep_clk: sleep_clk {
  19                         compatible = "fixed-clock";
  20                         clock-frequency = <32768>;
  21                         #clock-cells = <0>;
  22                 };
  23
  24                 xo: xo {
  25                         compatible = "fixed-clock";
  26                         clock-frequency = <19200000>;
  27                         #clock-cells = <0>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <0x1>;
  33                 #size-cells = <0x0>;
  34
  35                 CPU0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         reg = <0x0>;
  39                         next-level-cache = <&L2_0>;
  40                         enable-method = "psci";
  41                 };
  42
  43                 CPU1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         enable-method = "psci";
  47                         reg = <0x1>;
  48                         next-level-cache = <&L2_0>;
  49                 };
  50
  51                 CPU2: cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         enable-method = "psci";
  55                         reg = <0x2>;
  56                         next-level-cache = <&L2_0>;
  57                 };
  58
  59                 CPU3: cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a53";
  62                         enable-method = "psci";
  63                         reg = <0x3>;
  64                         next-level-cache = <&L2_0>;
  65                 };
  66
  67                 L2_0: l2-cache {
  68                         compatible = "cache";
  69                         cache-level = <0x2>;
  70                 };
  71         };
  72
  73         pmu {
  74                 compatible = "arm,cortex-a53-pmu";
  75                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  76         };
  77
  78         psci {
  79                 compatible = "arm,psci-1.0";
  80                 method = "smc";
  81         };
  82
  83         reserved-memory {
  84                 #address-cells = <2>;
  85                 #size-cells = <2>;
  86                 ranges;
  87
  88                 smem@4ab00000 {
  89                         compatible = "qcom,smem";
  90                         reg = <0x0 0x4ab00000 0x0 0x00100000>;
  91                         no-map;
  92
  93                         hwlocks = <&tcsr_mutex 3>;
  94                 };
  95
  96                 memory@4ac00000 {
  97                         no-map;
  98                         reg = <0x0 0x4ac00000 0x0 0x00400000>;
  99                 };
 100         };
 101
 102         firmware {
 103                 scm {
 104                         compatible = "qcom,scm-ipq8074", "qcom,scm";
 105                 };
 106         };
 107
 108         soc: soc {
 109                 #address-cells = <0x1>;
 110                 #size-cells = <0x1>;
 111                 ranges = <0 0 0 0xffffffff>;
 112                 compatible = "simple-bus";
 113
 114                 ssphy_1: phy@58000 {
 115                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 116                         reg = <0x00058000 0x1c4>;
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         ranges;
 120
 121                         clocks = <&gcc GCC_USB1_AUX_CLK>,
 122                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 123                                 <&xo>;
 124                         clock-names = "aux", "cfg_ahb", "ref";
 125
 126                         resets = <&gcc GCC_USB1_PHY_BCR>,
 127                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
 128                         reset-names = "phy","common";
 129                         status = "disabled";
 130
 131                         usb1_ssphy: phy@58200 {
 132                                 reg = <0x00058200 0x130>,       /* Tx */
 133                                       <0x00058400 0x200>,     /* Rx */
 134                                       <0x00058800 0x1f8>,     /* PCS  */
 135                                       <0x00058600 0x044>;     /* PCS misc*/
 136                                 #phy-cells = <0>;
 137                                 #clock-cells = <0>;
 138                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
 139                                 clock-names = "pipe0";
 140                                 clock-output-names = "usb3phy_1_cc_pipe_clk";
 141                         };
 142                 };
 143
 144                 qusb_phy_1: phy@59000 {
 145                         compatible = "qcom,ipq8074-qusb2-phy";
 146                         reg = <0x00059000 0x180>;
 147                         #phy-cells = <0>;
 148
 149                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 150                                  <&xo>;
 151                         clock-names = "cfg_ahb", "ref";
 152
 153                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 154                         status = "disabled";
 155                 };
 156
 157                 ssphy_0: phy@78000 {
 158                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 159                         reg = <0x00078000 0x1c4>;
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         ranges;
 163
 164                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 165                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 166                                 <&xo>;
 167                         clock-names = "aux", "cfg_ahb", "ref";
 168
 169                         resets = <&gcc GCC_USB0_PHY_BCR>,
 170                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
 171                         reset-names = "phy","common";
 172                         status = "disabled";
 173
 174                         usb0_ssphy: phy@78200 {
 175                                 reg = <0x00078200 0x130>,       /* Tx */
 176                                       <0x00078400 0x200>,     /* Rx */
 177                                       <0x00078800 0x1f8>,     /* PCS  */
 178                                       <0x00078600 0x044>;     /* PCS misc*/
 179                                 #phy-cells = <0>;
 180                                 #clock-cells = <0>;
 181                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 182                                 clock-names = "pipe0";
 183                                 clock-output-names = "usb3phy_0_cc_pipe_clk";
 184                         };
 185                 };
 186
 187                 qusb_phy_0: phy@79000 {
 188                         compatible = "qcom,ipq8074-qusb2-phy";
 189                         reg = <0x00079000 0x180>;
 190                         #phy-cells = <0>;
 191
 192                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 193                                  <&xo>;
 194                         clock-names = "cfg_ahb", "ref";
 195
 196                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 197                         status = "disabled";
 198                 };
 199
 200                 pcie_qmp0: phy@84000 {
 201                         compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
 202                         reg = <0x00084000 0x1bc>;
 203                         #address-cells = <1>;
 204                         #size-cells = <1>;
 205                         ranges;
 206
 207                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 208                                 <&gcc GCC_PCIE0_AHB_CLK>;
 209                         clock-names = "aux", "cfg_ahb";
 210                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 211                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 212                         reset-names = "phy",
 213                                       "common";
 214                         status = "disabled";
 215
 216                         pcie_phy0: phy@84200 {
 217                                 reg = <0x84200 0x16c>,
 218                                       <0x84400 0x200>,
 219                                       <0x84800 0x1f0>,
 220                                       <0x84c00 0xf4>;
 221                                 #phy-cells = <0>;
 222                                 #clock-cells = <0>;
 223                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 224                                 clock-names = "pipe0";
 225                                 clock-output-names = "pcie20_phy0_pipe_clk";
 226                         };
 227                 };
 228
 229                 pcie_qmp1: phy@8e000 {
 230                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 231                         reg = <0x0008e000 0x1c4>;
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         ranges;
 235
 236                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
 237                                 <&gcc GCC_PCIE1_AHB_CLK>;
 238                         clock-names = "aux", "cfg_ahb";
 239                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 240                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
 241                         reset-names = "phy",
 242                                       "common";
 243                         status = "disabled";
 244
 245                         pcie_phy1: phy@8e200 {
 246                                 reg = <0x8e200 0x130>,
 247                                       <0x8e400 0x200>,
 248                                       <0x8e800 0x1f8>;
 249                                 #phy-cells = <0>;
 250                                 #clock-cells = <0>;
 251                                 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 252                                 clock-names = "pipe0";
 253                                 clock-output-names = "pcie20_phy1_pipe_clk";
 254                         };
 255                 };
 256
 257                 mdio: mdio@90000 {
 258                         compatible = "qcom,ipq4019-mdio";
 259                         reg = <0x00090000 0x64>;
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262
 263                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 264                         clock-names = "gcc_mdio_ahb_clk";
 265
 266                         status = "disabled";
 267                 };
 268
 269                 prng: rng@e3000 {
 270                         compatible = "qcom,prng-ee";
 271                         reg = <0x000e3000 0x1000>;
 272                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 273                         clock-names = "core";
 274                         status = "disabled";
 275                 };
 276
 277                 cryptobam: dma-controller@704000 {
 278                         compatible = "qcom,bam-v1.7.0";
 279                         reg = <0x00704000 0x20000>;
 280                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 282                         clock-names = "bam_clk";
 283                         #dma-cells = <1>;
 284                         qcom,ee = <1>;
 285                         qcom,controlled-remotely;
 286                         status = "disabled";
 287                 };
 288
 289                 crypto: crypto@73a000 {
 290                         compatible = "qcom,crypto-v5.1";
 291                         reg = <0x0073a000 0x6000>;
 292                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 293                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 294                                  <&gcc GCC_CRYPTO_CLK>;
 295                         clock-names = "iface", "bus", "core";
 296                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 297                         dma-names = "rx", "tx";
 298                         status = "disabled";
 299                 };
 300
 301                 tlmm: pinctrl@1000000 {
 302                         compatible = "qcom,ipq8074-pinctrl";
 303                         reg = <0x01000000 0x300000>;
 304                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 305                         gpio-controller;
 306                         gpio-ranges = <&tlmm 0 0 70>;
 307                         #gpio-cells = <0x2>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <0x2>;
 310
 311                         serial_4_pins: serial4-pinmux {
 312                                 pins = "gpio23", "gpio24";
 313                                 function = "blsp4_uart1";
 314                                 drive-strength = <8>;
 315                                 bias-disable;
 316                         };
 317
 318                         i2c_0_pins: i2c-0-pinmux {
 319                                 pins = "gpio42", "gpio43";
 320                                 function = "blsp1_i2c";
 321                                 drive-strength = <8>;
 322                                 bias-disable;
 323                         };
 324
 325                         spi_0_pins: spi-0-pins {
 326                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 327                                 function = "blsp0_spi";
 328                                 drive-strength = <8>;
 329                                 bias-disable;
 330                         };
 331
 332                         hsuart_pins: hsuart-pins {
 333                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 334                                 function = "blsp2_uart";
 335                                 drive-strength = <8>;
 336                                 bias-disable;
 337                         };
 338
 339                         qpic_pins: qpic-pins {
 340                                 pins = "gpio1", "gpio3", "gpio4",
 341                                        "gpio5", "gpio6", "gpio7",
 342                                        "gpio8", "gpio10", "gpio11",
 343                                        "gpio12", "gpio13", "gpio14",
 344                                        "gpio15", "gpio16", "gpio17";
 345                                 function = "qpic";
 346                                 drive-strength = <8>;
 347                                 bias-disable;
 348                         };
 349                 };
 350
 351                 gcc: gcc@1800000 {
 352                         compatible = "qcom,gcc-ipq8074";
 353                         reg = <0x01800000 0x80000>;
 354                         #clock-cells = <0x1>;
 355                         #power-domain-cells = <1>;
 356                         #reset-cells = <0x1>;
 357                 };
 358
 359                 tcsr_mutex: hwlock@1905000 {
 360                         compatible = "qcom,tcsr-mutex";
 361                         reg = <0x01905000 0x20000>;
 362                         #hwlock-cells = <1>;
 363                 };
 364
 365                 spmi_bus: spmi@200f000 {
 366                         compatible = "qcom,spmi-pmic-arb";
 367                         reg = <0x0200f000 0x001000>,
 368                               <0x02400000 0x800000>,
 369                               <0x02c00000 0x800000>,
 370                               <0x03800000 0x200000>,
 371                               <0x0200a000 0x000700>;
 372                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 373                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 374                         interrupt-names = "periph_irq";
 375                         qcom,ee = <0>;
 376                         qcom,channel = <0>;
 377                         #address-cells = <2>;
 378                         #size-cells = <0>;
 379                         interrupt-controller;
 380                         #interrupt-cells = <4>;
 381                         cell-index = <0>;
 382                 };
 383
 384                 sdhc_1: mmc@7824900 {
 385                         compatible = "qcom,sdhci-msm-v4";
 386                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 387                         reg-names = "hc", "core";
 388
 389                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 391                         interrupt-names = "hc_irq", "pwr_irq";
 392
 393                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 394                                  <&gcc GCC_SDCC1_APPS_CLK>,
 395                                  <&xo>;
 396                         clock-names = "iface", "core", "xo";
 397                         resets = <&gcc GCC_SDCC1_BCR>;
 398                         max-frequency = <384000000>;
 399                         mmc-ddr-1_8v;
 400                         mmc-hs200-1_8v;
 401                         mmc-hs400-1_8v;
 402                         bus-width = <8>;
 403
 404                         status = "disabled";
 405                 };
 406
 407                 blsp_dma: dma-controller@7884000 {
 408                         compatible = "qcom,bam-v1.7.0";
 409                         reg = <0x07884000 0x2b000>;
 410                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 412                         clock-names = "bam_clk";
 413                         #dma-cells = <1>;
 414                         qcom,ee = <0>;
 415                 };
 416
 417                 blsp1_uart1: serial@78af000 {
 418                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 419                         reg = <0x078af000 0x200>;
 420                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 421                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 422                                  <&gcc GCC_BLSP1_AHB_CLK>;
 423                         clock-names = "core", "iface";
 424                         status = "disabled";
 425                 };
 426
 427                 blsp1_uart3: serial@78b1000 {
 428                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 429                         reg = <0x078b1000 0x200>;
 430                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 431                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 432                                 <&gcc GCC_BLSP1_AHB_CLK>;
 433                         clock-names = "core", "iface";
 434                         dmas = <&blsp_dma 4>,
 435                                 <&blsp_dma 5>;
 436                         dma-names = "tx", "rx";
 437                         pinctrl-0 = <&hsuart_pins>;
 438                         pinctrl-names = "default";
 439                         status = "disabled";
 440                 };
 441
 442                 blsp1_uart5: serial@78b3000 {
 443                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 444                         reg = <0x078b3000 0x200>;
 445                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 447                                  <&gcc GCC_BLSP1_AHB_CLK>;
 448                         clock-names = "core", "iface";
 449                         pinctrl-0 = <&serial_4_pins>;
 450                         pinctrl-names = "default";
 451                         status = "disabled";
 452                 };
 453
 454                 blsp1_spi1: spi@78b5000 {
 455                         compatible = "qcom,spi-qup-v2.2.1";
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         reg = <0x078b5000 0x600>;
 459                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 460                         spi-max-frequency = <50000000>;
 461                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 462                                 <&gcc GCC_BLSP1_AHB_CLK>;
 463                         clock-names = "core", "iface";
 464                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 465                         dma-names = "tx", "rx";
 466                         pinctrl-0 = <&spi_0_pins>;
 467                         pinctrl-names = "default";
 468                         status = "disabled";
 469                 };
 470
 471                 blsp1_i2c2: i2c@78b6000 {
 472                         compatible = "qcom,i2c-qup-v2.2.1";
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         reg = <0x078b6000 0x600>;
 476                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 477                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 478                                  <&gcc GCC_BLSP1_AHB_CLK>;
 479                         clock-names = "core", "iface";
 480                         clock-frequency = <400000>;
 481                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 482                         dma-names = "tx", "rx";
 483                         pinctrl-0 = <&i2c_0_pins>;
 484                         pinctrl-names = "default";
 485                         status = "disabled";
 486                 };
 487
 488                 blsp1_i2c3: i2c@78b7000 {
 489                         compatible = "qcom,i2c-qup-v2.2.1";
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         reg = <0x078b7000 0x600>;
 493                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 495                                  <&gcc GCC_BLSP1_AHB_CLK>;
 496                         clock-names = "core", "iface";
 497                         clock-frequency = <100000>;
 498                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 499                         dma-names = "tx", "rx";
 500                         status = "disabled";
 501                 };
 502
 503                 blsp1_i2c5: i2c@78b9000 {
 504                         compatible = "qcom,i2c-qup-v2.2.1";
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         reg = <0x78b9000 0x600>;
 508                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 509                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 510                                  <&gcc GCC_BLSP1_AHB_CLK>;
 511                         clock-names = "core", "iface";
 512                         clock-frequency = <400000>;
 513                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 514                         dma-names = "tx", "rx";
 515                         status = "disabled";
 516                 };
 517
 518                 blsp1_i2c6: i2c@78ba000 {
 519                         compatible = "qcom,i2c-qup-v2.2.1";
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         reg = <0x078ba000 0x600>;
 523                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 525                                  <&gcc GCC_BLSP1_AHB_CLK>;
 526                         clock-names = "core", "iface";
 527                         clock-frequency = <100000>;
 528                         dmas = <&blsp_dma 22>, <&blsp_dma 23>;
 529                         dma-names = "tx", "rx";
 530                         status = "disabled";
 531                 };
 532
 533                 qpic_bam: dma-controller@7984000 {
 534                         compatible = "qcom,bam-v1.7.0";
 535                         reg = <0x07984000 0x1a000>;
 536                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 537                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 538                         clock-names = "bam_clk";
 539                         #dma-cells = <1>;
 540                         qcom,ee = <0>;
 541                         status = "disabled";
 542                 };
 543
 544                 qpic_nand: nand-controller@79b0000 {
 545                         compatible = "qcom,ipq8074-nand";
 546                         reg = <0x079b0000 0x10000>;
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         clocks = <&gcc GCC_QPIC_CLK>,
 550                                  <&gcc GCC_QPIC_AHB_CLK>;
 551                         clock-names = "core", "aon";
 552
 553                         dmas = <&qpic_bam 0>,
 554                                <&qpic_bam 1>,
 555                                <&qpic_bam 2>;
 556                         dma-names = "tx", "rx", "cmd";
 557                         pinctrl-0 = <&qpic_pins>;
 558                         pinctrl-names = "default";
 559                         status = "disabled";
 560                 };
 561
 562                 usb_0: usb@8af8800 {
 563                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 564                         reg = <0x08af8800 0x400>;
 565                         #address-cells = <1>;
 566                         #size-cells = <1>;
 567                         ranges;
 568
 569                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 570                                 <&gcc GCC_USB0_MASTER_CLK>,
 571                                 <&gcc GCC_USB0_SLEEP_CLK>,
 572                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 573                         clock-names = "cfg_noc",
 574                                 "core",
 575                                 "sleep",
 576                                 "mock_utmi";
 577
 578                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 579                                           <&gcc GCC_USB0_MASTER_CLK>,
 580                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 581                         assigned-clock-rates = <133330000>,
 582                                                 <133330000>,
 583                                                 <19200000>;
 584
 585                         power-domains = <&gcc USB0_GDSC>;
 586
 587                         resets = <&gcc GCC_USB0_BCR>;
 588                         status = "disabled";
 589
 590                         dwc_0: usb@8a00000 {
 591                                 compatible = "snps,dwc3";
 592                                 reg = <0x8a00000 0xcd00>;
 593                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 594                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 595                                 phy-names = "usb2-phy", "usb3-phy";
 596                                 snps,is-utmi-l1-suspend;
 597                                 snps,hird-threshold = /bits/ 8 <0x0>;
 598                                 snps,dis_u2_susphy_quirk;
 599                                 snps,dis_u3_susphy_quirk;
 600                                 dr_mode = "host";
 601                         };
 602                 };
 603
 604                 usb_1: usb@8cf8800 {
 605                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
 606                         reg = <0x08cf8800 0x400>;
 607                         #address-cells = <1>;
 608                         #size-cells = <1>;
 609                         ranges;
 610
 611                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 612                                 <&gcc GCC_USB1_MASTER_CLK>,
 613                                 <&gcc GCC_USB1_SLEEP_CLK>,
 614                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 615                         clock-names = "cfg_noc",
 616                                 "core",
 617                                 "sleep",
 618                                 "mock_utmi";
 619
 620                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 621                                           <&gcc GCC_USB1_MASTER_CLK>,
 622                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 623                         assigned-clock-rates = <133330000>,
 624                                                 <133330000>,
 625                                                 <19200000>;
 626
 627                         power-domains = <&gcc USB1_GDSC>;
 628
 629                         resets = <&gcc GCC_USB1_BCR>;
 630                         status = "disabled";
 631
 632                         dwc_1: usb@8c00000 {
 633                                 compatible = "snps,dwc3";
 634                                 reg = <0x8c00000 0xcd00>;
 635                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 636                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
 637                                 phy-names = "usb2-phy", "usb3-phy";
 638                                 snps,is-utmi-l1-suspend;
 639                                 snps,hird-threshold = /bits/ 8 <0x0>;
 640                                 snps,dis_u2_susphy_quirk;
 641                                 snps,dis_u3_susphy_quirk;
 642                                 dr_mode = "host";
 643                         };
 644                 };
 645
 646                 intc: interrupt-controller@b000000 {
 647                         compatible = "qcom,msm-qgic2";
 648                         #address-cells = <1>;
 649                         #size-cells = <1>;
 650                         interrupt-controller;
 651                         #interrupt-cells = <0x3>;
 652                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 653                         ranges = <0 0xb00a000 0xffd>;
 654
 655                         v2m@0 {
 656                                 compatible = "arm,gic-v2m-frame";
 657                                 msi-controller;
 658                                 reg = <0x0 0xffd>;
 659                         };
 660                 };
 661
 662                 watchdog: watchdog@b017000 {
 663                         compatible = "qcom,kpss-wdt";
 664                         reg = <0xb017000 0x1000>;
 665                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 666                         clocks = <&sleep_clk>;
 667                         timeout-sec = <30>;
 668                 };
 669
 670                 apcs_glb: mailbox@b111000 {
 671                         compatible = "qcom,ipq8074-apcs-apps-global";
 672                         reg = <0x0b111000 0x1000>;
 673
 674                         #clock-cells = <1>;
 675                         #mbox-cells = <1>;
 676                 };
 677
 678                 timer@b120000 {
 679                         #address-cells = <1>;
 680                         #size-cells = <1>;
 681                         ranges;
 682                         compatible = "arm,armv7-timer-mem";
 683                         reg = <0x0b120000 0x1000>;
 684
 685                         frame@b120000 {
 686                                 frame-number = <0>;
 687                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 688                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 689                                 reg = <0x0b121000 0x1000>,
 690                                       <0x0b122000 0x1000>;
 691                         };
 692
 693                         frame@b123000 {
 694                                 frame-number = <1>;
 695                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 696                                 reg = <0x0b123000 0x1000>;
 697                                 status = "disabled";
 698                         };
 699
 700                         frame@b124000 {
 701                                 frame-number = <2>;
 702                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 703                                 reg = <0x0b124000 0x1000>;
 704                                 status = "disabled";
 705                         };
 706
 707                         frame@b125000 {
 708                                 frame-number = <3>;
 709                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 710                                 reg = <0x0b125000 0x1000>;
 711                                 status = "disabled";
 712                         };
 713
 714                         frame@b126000 {
 715                                 frame-number = <4>;
 716                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 717                                 reg = <0x0b126000 0x1000>;
 718                                 status = "disabled";
 719                         };
 720
 721                         frame@b127000 {
 722                                 frame-number = <5>;
 723                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 724                                 reg = <0x0b127000 0x1000>;
 725                                 status = "disabled";
 726                         };
 727
 728                         frame@b128000 {
 729                                 frame-number = <6>;
 730                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 731                                 reg = <0x0b128000 0x1000>;
 732                                 status = "disabled";
 733                         };
 734                 };
 735
 736                 pcie1: pci@10000000 {
 737                         compatible = "qcom,pcie-ipq8074";
 738                         reg =  <0x10000000 0xf1d>,
 739                                <0x10000f20 0xa8>,
 740                                <0x00088000 0x2000>,
 741                                <0x10100000 0x1000>;
 742                         reg-names = "dbi", "elbi", "parf", "config";
 743                         device_type = "pci";
 744                         linux,pci-domain = <1>;
 745                         bus-range = <0x00 0xff>;
 746                         num-lanes = <1>;
 747                         #address-cells = <3>;
 748                         #size-cells = <2>;
 749
 750                         phys = <&pcie_phy1>;
 751                         phy-names = "pciephy";
 752
 753                         ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
 754                                  <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
 755
 756                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 757                         interrupt-names = "msi";
 758                         #interrupt-cells = <1>;
 759                         interrupt-map-mask = <0 0 0 0x7>;
 760                         interrupt-map = <0 0 0 1 &intc 0 142
 761                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 762                                         <0 0 0 2 &intc 0 143
 763                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 764                                         <0 0 0 3 &intc 0 144
 765                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 766                                         <0 0 0 4 &intc 0 145
 767                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 768
 769                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 770                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 771                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 772                                  <&gcc GCC_PCIE1_AHB_CLK>,
 773                                  <&gcc GCC_PCIE1_AUX_CLK>;
 774                         clock-names = "iface",
 775                                       "axi_m",
 776                                       "axi_s",
 777                                       "ahb",
 778                                       "aux";
 779                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 780                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 781                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 782                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 783                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 784                                  <&gcc GCC_PCIE1_AHB_ARES>,
 785                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 786                         reset-names = "pipe",
 787                                       "sleep",
 788                                       "sticky",
 789                                       "axi_m",
 790                                       "axi_s",
 791                                       "ahb",
 792                                       "axi_m_sticky";
 793                         status = "disabled";
 794                 };
 795
 796                 pcie0: pci@20000000 {
 797                         compatible = "qcom,pcie-ipq8074-gen3";
 798                         reg = <0x20000000 0xf1d>,
 799                               <0x20000f20 0xa8>,
 800                               <0x20001000 0x1000>,
 801                               <0x00080000 0x4000>,
 802                               <0x20100000 0x1000>;
 803                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 804                         device_type = "pci";
 805                         linux,pci-domain = <0>;
 806                         bus-range = <0x00 0xff>;
 807                         num-lanes = <1>;
 808                         max-link-speed = <3>;
 809                         #address-cells = <3>;
 810                         #size-cells = <2>;
 811
 812                         phys = <&pcie_phy0>;
 813                         phy-names = "pciephy";
 814
 815                         ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
 816                                  <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
 817
 818                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 819                         interrupt-names = "msi";
 820                         #interrupt-cells = <1>;
 821                         interrupt-map-mask = <0 0 0 0x7>;
 822                         interrupt-map = <0 0 0 1 &intc 0 75
 823                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 824                                         <0 0 0 2 &intc 0 78
 825                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 826                                         <0 0 0 3 &intc 0 79
 827                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 828                                         <0 0 0 4 &intc 0 83
 829                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 830
 831                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 832                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 833                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 834                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 835                                  <&gcc GCC_PCIE0_RCHNG_CLK>;
 836                         clock-names = "iface",
 837                                       "axi_m",
 838                                       "axi_s",
 839                                       "axi_bridge",
 840                                       "rchng";
 841
 842                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 843                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 844                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 845                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 846                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 847                                  <&gcc GCC_PCIE0_AHB_ARES>,
 848                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 849                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 850                         reset-names = "pipe",
 851                                       "sleep",
 852                                       "sticky",
 853                                       "axi_m",
 854                                       "axi_s",
 855                                       "ahb",
 856                                       "axi_m_sticky",
 857                                       "axi_s_sticky";
 858                         status = "disabled";
 859                 };
 860         };
 861
 862         timer {
 863                 compatible = "arm,armv8-timer";
 864                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 865                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 866                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 867                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 868         };
 869 };