1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
13 model = "Qualcomm Technologies, Inc. IPQ8074";
14 compatible = "qcom,ipq8074";
15 interrupt-parent = <&intc>;
18 sleep_clk: sleep_clk {
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
25 compatible = "fixed-clock";
26 clock-frequency = <19200000>;
37 compatible = "arm,cortex-a53";
39 next-level-cache = <&L2_0>;
40 enable-method = "psci";
45 compatible = "arm,cortex-a53";
46 enable-method = "psci";
48 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53";
62 enable-method = "psci";
64 next-level-cache = <&L2_0>;
75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
80 compatible = "arm,psci-1.0";
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
100 compatible = "qcom,smem";
101 reg = <0x0 0x4ab00000 0x0 0x100000>;
104 hwlocks = <&tcsr_mutex 3>;
108 reg = <0x0 0x4ac00000 0x0 0x400000>;
115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tcsr 0x6100>;
121 #address-cells = <1>;
123 ranges = <0 0 0 0xffffffff>;
124 compatible = "simple-bus";
127 compatible = "qcom,ipq8074-qmp-usb3-phy";
128 reg = <0x00058000 0x1c4>;
129 #address-cells = <1>;
133 clocks = <&gcc GCC_USB1_AUX_CLK>,
134 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
136 clock-names = "aux", "cfg_ahb", "ref";
138 resets = <&gcc GCC_USB1_PHY_BCR>,
139 <&gcc GCC_USB3PHY_1_PHY_BCR>;
140 reset-names = "phy","common";
143 usb1_ssphy: phy@58200 {
144 reg = <0x00058200 0x130>, /* Tx */
145 <0x00058400 0x200>, /* Rx */
146 <0x00058800 0x1f8>, /* PCS */
147 <0x00058600 0x044>; /* PCS misc */
150 clocks = <&gcc GCC_USB1_PIPE_CLK>;
151 clock-names = "pipe0";
152 clock-output-names = "usb3phy_1_cc_pipe_clk";
156 qusb_phy_1: phy@59000 {
157 compatible = "qcom,ipq8074-qusb2-phy";
158 reg = <0x00059000 0x180>;
161 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
163 clock-names = "cfg_ahb", "ref";
165 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
170 compatible = "qcom,ipq8074-qmp-usb3-phy";
171 reg = <0x00078000 0x1c4>;
172 #address-cells = <1>;
176 clocks = <&gcc GCC_USB0_AUX_CLK>,
177 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
179 clock-names = "aux", "cfg_ahb", "ref";
181 resets = <&gcc GCC_USB0_PHY_BCR>,
182 <&gcc GCC_USB3PHY_0_PHY_BCR>;
183 reset-names = "phy","common";
186 usb0_ssphy: phy@78200 {
187 reg = <0x00078200 0x130>, /* Tx */
188 <0x00078400 0x200>, /* Rx */
189 <0x00078800 0x1f8>, /* PCS */
190 <0x00078600 0x044>; /* PCS misc */
193 clocks = <&gcc GCC_USB0_PIPE_CLK>;
194 clock-names = "pipe0";
195 clock-output-names = "usb3phy_0_cc_pipe_clk";
199 qusb_phy_0: phy@79000 {
200 compatible = "qcom,ipq8074-qusb2-phy";
201 reg = <0x00079000 0x180>;
204 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
206 clock-names = "cfg_ahb", "ref";
208 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
212 pcie_qmp0: phy@84000 {
213 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
214 reg = <0x00084000 0x1000>;
216 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
217 <&gcc GCC_PCIE0_AHB_CLK>,
218 <&gcc GCC_PCIE0_PIPE_CLK>;
223 clock-output-names = "pcie20_phy0_pipe_clk";
228 resets = <&gcc GCC_PCIE0_PHY_BCR>,
229 <&gcc GCC_PCIE0PHY_PHY_BCR>;
235 pcie_qmp1: phy@8e000 {
236 compatible = "qcom,ipq8074-qmp-pcie-phy";
237 reg = <0x0008e000 0x1000>;
239 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
240 <&gcc GCC_PCIE1_AHB_CLK>,
241 <&gcc GCC_PCIE1_PIPE_CLK>;
246 clock-output-names = "pcie20_phy1_pipe_clk";
251 resets = <&gcc GCC_PCIE1_PHY_BCR>,
252 <&gcc GCC_PCIE1PHY_PHY_BCR>;
259 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
260 reg = <0x00090000 0x64>;
261 #address-cells = <1>;
264 clocks = <&gcc GCC_MDIO_AHB_CLK>;
265 clock-names = "gcc_mdio_ahb_clk";
270 qfprom: efuse@a4000 {
271 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
272 reg = <0x000a4000 0x2000>;
273 #address-cells = <1>;
278 compatible = "qcom,prng-ee";
279 reg = <0x000e3000 0x1000>;
280 clocks = <&gcc GCC_PRNG_AHB_CLK>;
281 clock-names = "core";
285 tsens: thermal-sensor@4a9000 {
286 compatible = "qcom,ipq8074-tsens";
287 reg = <0x4a9000 0x1000>, /* TM */
288 <0x4a8000 0x1000>; /* SROT */
289 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "combined";
291 #qcom,sensors = <16>;
292 #thermal-sensor-cells = <1>;
295 cryptobam: dma-controller@704000 {
296 compatible = "qcom,bam-v1.7.0";
297 reg = <0x00704000 0x20000>;
298 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
300 clock-names = "bam_clk";
303 qcom,controlled-remotely;
307 crypto: crypto@73a000 {
308 compatible = "qcom,crypto-v5.1";
309 reg = <0x0073a000 0x6000>;
310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
311 <&gcc GCC_CRYPTO_AXI_CLK>,
312 <&gcc GCC_CRYPTO_CLK>;
313 clock-names = "iface", "bus", "core";
314 dmas = <&cryptobam 2>, <&cryptobam 3>;
315 dma-names = "rx", "tx";
319 tlmm: pinctrl@1000000 {
320 compatible = "qcom,ipq8074-pinctrl";
321 reg = <0x01000000 0x300000>;
322 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
324 gpio-ranges = <&tlmm 0 0 70>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
329 serial_4_pins: serial4-state {
330 pins = "gpio23", "gpio24";
331 function = "blsp4_uart1";
332 drive-strength = <8>;
336 i2c_0_pins: i2c-0-state {
337 pins = "gpio42", "gpio43";
338 function = "blsp1_i2c";
339 drive-strength = <8>;
343 spi_0_pins: spi-0-state {
344 pins = "gpio38", "gpio39", "gpio40", "gpio41";
345 function = "blsp0_spi";
346 drive-strength = <8>;
350 hsuart_pins: hsuart-state {
351 pins = "gpio46", "gpio47", "gpio48", "gpio49";
352 function = "blsp2_uart";
353 drive-strength = <8>;
357 qpic_pins: qpic-state {
358 pins = "gpio1", "gpio3", "gpio4",
359 "gpio5", "gpio6", "gpio7",
360 "gpio8", "gpio10", "gpio11",
361 "gpio12", "gpio13", "gpio14",
362 "gpio15", "gpio16", "gpio17";
364 drive-strength = <8>;
370 compatible = "qcom,gcc-ipq8074";
371 reg = <0x01800000 0x80000>;
372 clocks = <&xo>, <&sleep_clk>;
373 clock-names = "xo", "sleep_clk";
375 #power-domain-cells = <1>;
379 tcsr_mutex: hwlock@1905000 {
380 compatible = "qcom,tcsr-mutex";
381 reg = <0x01905000 0x20000>;
385 tcsr: syscon@1937000 {
386 compatible = "qcom,tcsr-ipq8074", "syscon";
387 reg = <0x01937000 0x21000>;
390 spmi_bus: spmi@200f000 {
391 compatible = "qcom,spmi-pmic-arb";
392 reg = <0x0200f000 0x001000>,
393 <0x02400000 0x800000>,
394 <0x02c00000 0x800000>,
395 <0x03800000 0x200000>,
396 <0x0200a000 0x000700>;
397 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
398 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
399 interrupt-names = "periph_irq";
402 #address-cells = <2>;
404 interrupt-controller;
405 #interrupt-cells = <4>;
408 sdhc_1: mmc@7824900 {
409 compatible = "qcom,sdhci-msm-v4";
410 reg = <0x7824900 0x500>, <0x7824000 0x800>;
411 reg-names = "hc", "core";
413 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
415 interrupt-names = "hc_irq", "pwr_irq";
417 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
418 <&gcc GCC_SDCC1_APPS_CLK>,
420 clock-names = "iface", "core", "xo";
421 resets = <&gcc GCC_SDCC1_BCR>;
422 max-frequency = <384000000>;
431 blsp_dma: dma-controller@7884000 {
432 compatible = "qcom,bam-v1.7.0";
433 reg = <0x07884000 0x2b000>;
434 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
436 clock-names = "bam_clk";
441 blsp1_uart1: serial@78af000 {
442 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
443 reg = <0x078af000 0x200>;
444 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
446 <&gcc GCC_BLSP1_AHB_CLK>;
447 clock-names = "core", "iface";
451 blsp1_uart3: serial@78b1000 {
452 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
453 reg = <0x078b1000 0x200>;
454 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
456 <&gcc GCC_BLSP1_AHB_CLK>;
457 clock-names = "core", "iface";
458 dmas = <&blsp_dma 4>,
460 dma-names = "tx", "rx";
461 pinctrl-0 = <&hsuart_pins>;
462 pinctrl-names = "default";
466 blsp1_uart5: serial@78b3000 {
467 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
468 reg = <0x078b3000 0x200>;
469 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
471 <&gcc GCC_BLSP1_AHB_CLK>;
472 clock-names = "core", "iface";
473 pinctrl-0 = <&serial_4_pins>;
474 pinctrl-names = "default";
478 blsp1_spi1: spi@78b5000 {
479 compatible = "qcom,spi-qup-v2.2.1";
480 #address-cells = <1>;
482 reg = <0x078b5000 0x600>;
483 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
485 <&gcc GCC_BLSP1_AHB_CLK>;
486 clock-names = "core", "iface";
487 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
488 dma-names = "tx", "rx";
489 pinctrl-0 = <&spi_0_pins>;
490 pinctrl-names = "default";
494 blsp1_i2c2: i2c@78b6000 {
495 compatible = "qcom,i2c-qup-v2.2.1";
496 #address-cells = <1>;
498 reg = <0x078b6000 0x600>;
499 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
501 <&gcc GCC_BLSP1_AHB_CLK>;
502 clock-names = "core", "iface";
503 clock-frequency = <400000>;
504 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
505 dma-names = "tx", "rx";
506 pinctrl-0 = <&i2c_0_pins>;
507 pinctrl-names = "default";
511 blsp1_i2c3: i2c@78b7000 {
512 compatible = "qcom,i2c-qup-v2.2.1";
513 #address-cells = <1>;
515 reg = <0x078b7000 0x600>;
516 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
518 <&gcc GCC_BLSP1_AHB_CLK>;
519 clock-names = "core", "iface";
520 clock-frequency = <100000>;
521 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
522 dma-names = "tx", "rx";
526 blsp1_i2c5: i2c@78b9000 {
527 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>;
530 reg = <0x78b9000 0x600>;
531 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
533 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", "iface";
535 clock-frequency = <400000>;
536 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
537 dma-names = "tx", "rx";
541 blsp1_spi5: spi@78b9000 {
542 compatible = "qcom,spi-qup-v2.2.1";
543 #address-cells = <1>;
545 reg = <0x78b9000 0x600>;
546 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", "iface";
550 dmas = <&blsp_dma 20>, <&blsp_dma 21>;
551 dma-names = "tx", "rx";
555 blsp1_i2c6: i2c@78ba000 {
556 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>;
559 reg = <0x078ba000 0x600>;
560 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", "iface";
564 clock-frequency = <100000>;
565 dmas = <&blsp_dma 22>, <&blsp_dma 23>;
566 dma-names = "tx", "rx";
570 qpic_bam: dma-controller@7984000 {
571 compatible = "qcom,bam-v1.7.0";
572 reg = <0x07984000 0x1a000>;
573 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&gcc GCC_QPIC_AHB_CLK>;
575 clock-names = "bam_clk";
581 qpic_nand: nand-controller@79b0000 {
582 compatible = "qcom,ipq8074-nand";
583 reg = <0x079b0000 0x10000>;
584 #address-cells = <1>;
586 clocks = <&gcc GCC_QPIC_CLK>,
587 <&gcc GCC_QPIC_AHB_CLK>;
588 clock-names = "core", "aon";
590 dmas = <&qpic_bam 0>,
593 dma-names = "tx", "rx", "cmd";
594 pinctrl-0 = <&qpic_pins>;
595 pinctrl-names = "default";
600 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
601 reg = <0x08af8800 0x400>;
602 #address-cells = <1>;
606 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
607 <&gcc GCC_USB0_MASTER_CLK>,
608 <&gcc GCC_USB0_SLEEP_CLK>,
609 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
610 clock-names = "cfg_noc",
615 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
616 <&gcc GCC_USB0_MASTER_CLK>,
617 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
618 assigned-clock-rates = <133330000>,
622 power-domains = <&gcc USB0_GDSC>;
624 resets = <&gcc GCC_USB0_BCR>;
628 compatible = "snps,dwc3";
629 reg = <0x8a00000 0xcd00>;
630 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
631 phys = <&qusb_phy_0>, <&usb0_ssphy>;
632 phy-names = "usb2-phy", "usb3-phy";
633 snps,is-utmi-l1-suspend;
634 snps,hird-threshold = /bits/ 8 <0x0>;
635 snps,dis_u2_susphy_quirk;
636 snps,dis_u3_susphy_quirk;
642 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
643 reg = <0x08cf8800 0x400>;
644 #address-cells = <1>;
648 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
649 <&gcc GCC_USB1_MASTER_CLK>,
650 <&gcc GCC_USB1_SLEEP_CLK>,
651 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
652 clock-names = "cfg_noc",
657 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
658 <&gcc GCC_USB1_MASTER_CLK>,
659 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
660 assigned-clock-rates = <133330000>,
664 power-domains = <&gcc USB1_GDSC>;
666 resets = <&gcc GCC_USB1_BCR>;
670 compatible = "snps,dwc3";
671 reg = <0x8c00000 0xcd00>;
672 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
673 phys = <&qusb_phy_1>, <&usb1_ssphy>;
674 phy-names = "usb2-phy", "usb3-phy";
675 snps,is-utmi-l1-suspend;
676 snps,hird-threshold = /bits/ 8 <0x0>;
677 snps,dis_u2_susphy_quirk;
678 snps,dis_u3_susphy_quirk;
683 intc: interrupt-controller@b000000 {
684 compatible = "qcom,msm-qgic2";
685 #address-cells = <1>;
687 interrupt-controller;
688 #interrupt-cells = <3>;
689 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
690 ranges = <0 0xb00a000 0xffd>;
693 compatible = "arm,gic-v2m-frame";
699 watchdog: watchdog@b017000 {
700 compatible = "qcom,kpss-wdt";
701 reg = <0xb017000 0x1000>;
702 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
703 clocks = <&sleep_clk>;
707 apcs_glb: mailbox@b111000 {
708 compatible = "qcom,ipq8074-apcs-apps-global",
709 "qcom,ipq6018-apcs-apps-global";
710 reg = <0x0b111000 0x1000>;
711 clocks = <&a53pll>, <&xo>;
712 clock-names = "pll", "xo";
718 a53pll: clock@b116000 {
719 compatible = "qcom,ipq8074-a53pll";
720 reg = <0x0b116000 0x40>;
727 #address-cells = <1>;
730 compatible = "arm,armv7-timer-mem";
731 reg = <0x0b120000 0x1000>;
735 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
737 reg = <0x0b121000 0x1000>,
743 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
744 reg = <0x0b123000 0x1000>;
750 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
751 reg = <0x0b124000 0x1000>;
757 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
758 reg = <0x0b125000 0x1000>;
764 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
765 reg = <0x0b126000 0x1000>;
771 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
772 reg = <0x0b127000 0x1000>;
778 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
779 reg = <0x0b128000 0x1000>;
784 pcie1: pci@10000000 {
785 compatible = "qcom,pcie-ipq8074";
786 reg = <0x10000000 0xf1d>,
790 reg-names = "dbi", "elbi", "parf", "config";
792 linux,pci-domain = <1>;
793 bus-range = <0x00 0xff>;
795 max-link-speed = <2>;
796 #address-cells = <3>;
800 phy-names = "pciephy";
802 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
803 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
805 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
806 interrupt-names = "msi";
807 #interrupt-cells = <1>;
808 interrupt-map-mask = <0 0 0 0x7>;
809 interrupt-map = <0 0 0 1 &intc 0 142
810 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
812 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
814 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
816 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
818 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
819 <&gcc GCC_PCIE1_AXI_M_CLK>,
820 <&gcc GCC_PCIE1_AXI_S_CLK>,
821 <&gcc GCC_PCIE1_AHB_CLK>,
822 <&gcc GCC_PCIE1_AUX_CLK>;
823 clock-names = "iface",
828 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
829 <&gcc GCC_PCIE1_SLEEP_ARES>,
830 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
831 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
832 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
833 <&gcc GCC_PCIE1_AHB_ARES>,
834 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
835 reset-names = "pipe",
845 pcie0: pci@20000000 {
846 compatible = "qcom,pcie-ipq8074-gen3";
847 reg = <0x20000000 0xf1d>,
852 reg-names = "dbi", "elbi", "atu", "parf", "config";
854 linux,pci-domain = <0>;
855 bus-range = <0x00 0xff>;
857 max-link-speed = <3>;
858 #address-cells = <3>;
862 phy-names = "pciephy";
864 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
865 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
867 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "msi";
869 #interrupt-cells = <1>;
870 interrupt-map-mask = <0 0 0 0x7>;
871 interrupt-map = <0 0 0 1 &intc 0 75
872 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
874 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
876 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
878 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
880 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
881 <&gcc GCC_PCIE0_AXI_M_CLK>,
882 <&gcc GCC_PCIE0_AXI_S_CLK>,
883 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
884 <&gcc GCC_PCIE0_RCHNG_CLK>;
885 clock-names = "iface",
891 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
892 <&gcc GCC_PCIE0_SLEEP_ARES>,
893 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
894 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
895 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
896 <&gcc GCC_PCIE0_AHB_ARES>,
897 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
898 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
899 reset-names = "pipe",
912 compatible = "arm,armv8-timer";
913 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
914 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
915 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
916 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
921 polling-delay-passive = <250>;
922 polling-delay = <1000>;
924 thermal-sensors = <&tsens 4>;
928 temperature = <110000>;
936 polling-delay-passive = <250>;
937 polling-delay = <1000>;
939 thermal-sensors = <&tsens 5>;
943 temperature = <110000>;
951 polling-delay-passive = <250>;
952 polling-delay = <1000>;
954 thermal-sensors = <&tsens 6>;
958 temperature = <110000>;
966 polling-delay-passive = <250>;
967 polling-delay = <1000>;
969 thermal-sensors = <&tsens 7>;
973 temperature = <110000>;
981 polling-delay-passive = <250>;
982 polling-delay = <1000>;
984 thermal-sensors = <&tsens 8>;
988 temperature = <110000>;
995 cpu0_thermal: cpu0-thermal {
996 polling-delay-passive = <250>;
997 polling-delay = <1000>;
999 thermal-sensors = <&tsens 9>;
1003 temperature = <110000>;
1004 hysteresis = <1000>;
1010 cpu1_thermal: cpu1-thermal {
1011 polling-delay-passive = <250>;
1012 polling-delay = <1000>;
1014 thermal-sensors = <&tsens 10>;
1018 temperature = <110000>;
1019 hysteresis = <1000>;
1025 cpu2_thermal: cpu2-thermal {
1026 polling-delay-passive = <250>;
1027 polling-delay = <1000>;
1029 thermal-sensors = <&tsens 11>;
1033 temperature = <110000>;
1034 hysteresis = <1000>;
1040 cpu3_thermal: cpu3-thermal {
1041 polling-delay-passive = <250>;
1042 polling-delay = <1000>;
1044 thermal-sensors = <&tsens 12>;
1048 temperature = <110000>;
1049 hysteresis = <1000>;
1055 cluster_thermal: cluster-thermal {
1056 polling-delay-passive = <250>;
1057 polling-delay = <1000>;
1059 thermal-sensors = <&tsens 13>;
1063 temperature = <110000>;
1064 hysteresis = <1000>;
1070 wcss-phyb0-thermal {
1071 polling-delay-passive = <250>;
1072 polling-delay = <1000>;
1074 thermal-sensors = <&tsens 14>;
1078 temperature = <110000>;
1079 hysteresis = <1000>;
1085 wcss-phyb1-thermal {
1086 polling-delay-passive = <250>;
1087 polling-delay = <1000>;
1089 thermal-sensors = <&tsens 15>;
1093 temperature = <110000>;
1094 hysteresis = <1000>;