1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * IPQ6018 SoC device tree source
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
93 compatible = "qcom,scm-ipq6018", "qcom,scm";
94 qcom,dload-mode = <&tcsr 0x6100>;
98 cpu_opp_table: opp-table-cpu {
99 compatible = "operating-points-v2";
103 opp-hz = /bits/ 64 <864000000>;
104 opp-microvolt = <725000>;
105 clock-latency-ns = <200000>;
109 opp-hz = /bits/ 64 <1056000000>;
110 opp-microvolt = <787500>;
111 clock-latency-ns = <200000>;
115 opp-hz = /bits/ 64 <1320000000>;
116 opp-microvolt = <862500>;
117 clock-latency-ns = <200000>;
121 opp-hz = /bits/ 64 <1440000000>;
122 opp-microvolt = <925000>;
123 clock-latency-ns = <200000>;
127 opp-hz = /bits/ 64 <1608000000>;
128 opp-microvolt = <987500>;
129 clock-latency-ns = <200000>;
133 opp-hz = /bits/ 64 <1800000000>;
134 opp-microvolt = <1062500>;
135 clock-latency-ns = <200000>;
140 compatible = "arm,cortex-a53-pmu";
141 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
145 compatible = "arm,psci-1.0";
150 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
153 compatible = "qcom,glink-rpm";
154 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
155 qcom,rpm-msg-ram = <&rpm_msg_ram>;
156 mboxes = <&apcs_glb 0>;
158 rpm_requests: rpm-requests {
159 compatible = "qcom,rpm-ipq6018";
160 qcom,glink-channels = "rpm_requests";
163 compatible = "qcom,rpm-mp5496-regulators";
166 regulator-min-microvolt = <725000>;
167 regulator-max-microvolt = <1062500>;
176 #address-cells = <2>;
180 rpm_msg_ram: memory@60000 {
181 reg = <0x0 0x00060000 0x0 0x6000>;
185 bootloader@4a100000 {
186 reg = <0x0 0x4a100000 0x0 0x400000>;
191 reg = <0x0 0x4a500000 0x0 0x100000>;
195 tz: memory@4a600000 {
196 reg = <0x0 0x4a600000 0x0 0x400000>;
200 smem_region: memory@4aa00000 {
201 reg = <0x0 0x4aa00000 0x0 0x100000>;
205 q6_region: memory@4ab00000 {
206 reg = <0x0 0x4ab00000 0x0 0x5500000>;
212 compatible = "qcom,smem";
213 memory-region = <&smem_region>;
214 hwlocks = <&tcsr_mutex 3>;
218 #address-cells = <2>;
220 ranges = <0 0 0 0 0x0 0xffffffff>;
222 compatible = "simple-bus";
224 qusb_phy_1: qusb@59000 {
225 compatible = "qcom,ipq6018-qusb2-phy";
226 reg = <0x0 0x00059000 0x0 0x180>;
229 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
231 clock-names = "cfg_ahb", "ref";
233 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
237 ssphy_0: ssphy@78000 {
238 compatible = "qcom,ipq6018-qmp-usb3-phy";
239 reg = <0x0 0x00078000 0x0 0x1c4>;
240 #address-cells = <2>;
244 clocks = <&gcc GCC_USB0_AUX_CLK>,
245 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
246 clock-names = "aux", "cfg_ahb", "ref";
248 resets = <&gcc GCC_USB0_PHY_BCR>,
249 <&gcc GCC_USB3PHY_0_PHY_BCR>;
250 reset-names = "phy","common";
253 usb0_ssphy: phy@78200 {
254 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
255 <0x0 0x00078400 0x0 0x200>, /* Rx */
256 <0x0 0x00078800 0x0 0x1f8>, /* PCS */
257 <0x0 0x00078600 0x0 0x044>; /* PCS misc */
260 clocks = <&gcc GCC_USB0_PIPE_CLK>;
261 clock-names = "pipe0";
262 clock-output-names = "gcc_usb0_pipe_clk_src";
266 qusb_phy_0: qusb@79000 {
267 compatible = "qcom,ipq6018-qusb2-phy";
268 reg = <0x0 0x00079000 0x0 0x180>;
271 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
273 clock-names = "cfg_ahb", "ref";
275 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
279 pcie_phy: phy@84000 {
280 compatible = "qcom,ipq6018-qmp-pcie-phy";
281 reg = <0x0 0x00084000 0x0 0x1000>;
284 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
285 <&gcc GCC_PCIE0_AHB_CLK>,
286 <&gcc GCC_PCIE0_PIPE_CLK>;
291 clock-output-names = "gcc_pcie0_pipe_clk_src";
296 resets = <&gcc GCC_PCIE0_PHY_BCR>,
297 <&gcc GCC_PCIE0PHY_PHY_BCR>;
303 #address-cells = <1>;
305 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
306 reg = <0x0 0x00090000 0x0 0x64>;
307 clocks = <&gcc GCC_MDIO_AHB_CLK>;
308 clock-names = "gcc_mdio_ahb_clk";
312 qfprom: efuse@a4000 {
313 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
314 reg = <0x0 0x000a4000 0x0 0x2000>;
315 #address-cells = <1>;
320 compatible = "qcom,prng-ee";
321 reg = <0x0 0x000e3000 0x0 0x1000>;
322 clocks = <&gcc GCC_PRNG_AHB_CLK>;
323 clock-names = "core";
326 cryptobam: dma-controller@704000 {
327 compatible = "qcom,bam-v1.7.0";
328 reg = <0x0 0x00704000 0x0 0x20000>;
329 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
331 clock-names = "bam_clk";
334 qcom,controlled-remotely;
337 crypto: crypto@73a000 {
338 compatible = "qcom,crypto-v5.1";
339 reg = <0x0 0x0073a000 0x0 0x6000>;
340 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
341 <&gcc GCC_CRYPTO_AXI_CLK>,
342 <&gcc GCC_CRYPTO_CLK>;
343 clock-names = "iface", "bus", "core";
344 dmas = <&cryptobam 2>, <&cryptobam 3>;
345 dma-names = "rx", "tx";
348 tlmm: pinctrl@1000000 {
349 compatible = "qcom,ipq6018-pinctrl";
350 reg = <0x0 0x01000000 0x0 0x300000>;
351 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
354 gpio-ranges = <&tlmm 0 0 80>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
358 serial_3_pins: serial3-state {
359 pins = "gpio44", "gpio45";
360 function = "blsp2_uart";
361 drive-strength = <8>;
365 qpic_pins: qpic-state {
366 pins = "gpio1", "gpio3", "gpio4",
367 "gpio5", "gpio6", "gpio7",
368 "gpio8", "gpio10", "gpio11",
369 "gpio12", "gpio13", "gpio14",
371 function = "qpic_pad";
372 drive-strength = <8>;
378 compatible = "qcom,gcc-ipq6018";
379 reg = <0x0 0x01800000 0x0 0x80000>;
380 clocks = <&xo>, <&sleep_clk>;
381 clock-names = "xo", "sleep_clk";
386 tcsr_mutex: hwlock@1905000 {
387 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
388 reg = <0x0 0x01905000 0x0 0x20000>;
392 tcsr: syscon@1937000 {
393 compatible = "qcom,tcsr-ipq6018", "syscon";
394 reg = <0x0 0x01937000 0x0 0x21000>;
398 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
399 reg = <0x0 0x070f8800 0x0 0x400>;
400 #address-cells = <2>;
403 clocks = <&gcc GCC_USB1_MASTER_CLK>,
404 <&gcc GCC_USB1_SLEEP_CLK>,
405 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
406 clock-names = "core",
410 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
411 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
412 assigned-clock-rates = <133330000>,
414 resets = <&gcc GCC_USB1_BCR>;
418 compatible = "snps,dwc3";
419 reg = <0x0 0x07000000 0x0 0xcd00>;
420 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
421 phys = <&qusb_phy_1>;
422 phy-names = "usb2-phy";
424 snps,is-utmi-l1-suspend;
425 snps,hird-threshold = /bits/ 8 <0x0>;
426 snps,dis_u2_susphy_quirk;
427 snps,dis_u3_susphy_quirk;
432 blsp_dma: dma-controller@7884000 {
433 compatible = "qcom,bam-v1.7.0";
434 reg = <0x0 0x07884000 0x0 0x2b000>;
435 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
437 clock-names = "bam_clk";
442 blsp1_uart3: serial@78b1000 {
443 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
444 reg = <0x0 0x078b1000 0x0 0x200>;
445 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
447 <&gcc GCC_BLSP1_AHB_CLK>;
448 clock-names = "core", "iface";
452 blsp1_spi1: spi@78b5000 {
453 compatible = "qcom,spi-qup-v2.2.1";
454 #address-cells = <1>;
456 reg = <0x0 0x078b5000 0x0 0x600>;
457 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
459 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", "iface";
461 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
462 dma-names = "tx", "rx";
466 blsp1_spi2: spi@78b6000 {
467 compatible = "qcom,spi-qup-v2.2.1";
468 #address-cells = <1>;
470 reg = <0x0 0x078b6000 0x0 0x600>;
471 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
473 <&gcc GCC_BLSP1_AHB_CLK>;
474 clock-names = "core", "iface";
475 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
476 dma-names = "tx", "rx";
480 blsp1_i2c2: i2c@78b6000 {
481 compatible = "qcom,i2c-qup-v2.2.1";
482 #address-cells = <1>;
484 reg = <0x0 0x078b6000 0x0 0x600>;
485 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
487 <&gcc GCC_BLSP1_AHB_CLK>;
488 clock-names = "core", "iface";
489 clock-frequency = <400000>;
490 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
491 dma-names = "tx", "rx";
495 blsp1_i2c3: i2c@78b7000 {
496 compatible = "qcom,i2c-qup-v2.2.1";
497 #address-cells = <1>;
499 reg = <0x0 0x078b7000 0x0 0x600>;
500 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
502 <&gcc GCC_BLSP1_AHB_CLK>;
503 clock-names = "core", "iface";
504 clock-frequency = <400000>;
505 dmas = <&blsp_dma 16>, <&blsp_dma 17>;
506 dma-names = "tx", "rx";
510 qpic_bam: dma-controller@7984000 {
511 compatible = "qcom,bam-v1.7.0";
512 reg = <0x0 0x07984000 0x0 0x1a000>;
513 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&gcc GCC_QPIC_AHB_CLK>;
515 clock-names = "bam_clk";
521 qpic_nand: nand-controller@79b0000 {
522 compatible = "qcom,ipq6018-nand";
523 reg = <0x0 0x079b0000 0x0 0x10000>;
524 #address-cells = <1>;
526 clocks = <&gcc GCC_QPIC_CLK>,
527 <&gcc GCC_QPIC_AHB_CLK>;
528 clock-names = "core", "aon";
530 dmas = <&qpic_bam 0>,
533 dma-names = "tx", "rx", "cmd";
534 pinctrl-0 = <&qpic_pins>;
535 pinctrl-names = "default";
540 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
541 reg = <0x0 0x08af8800 0x0 0x400>;
542 #address-cells = <2>;
546 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
547 <&gcc GCC_USB0_MASTER_CLK>,
548 <&gcc GCC_USB0_SLEEP_CLK>,
549 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
550 clock-names = "cfg_noc",
555 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
556 <&gcc GCC_USB0_MASTER_CLK>,
557 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
558 assigned-clock-rates = <133330000>,
562 resets = <&gcc GCC_USB0_BCR>;
566 compatible = "snps,dwc3";
567 reg = <0x0 0x08a00000 0x0 0xcd00>;
568 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
569 phys = <&qusb_phy_0>, <&usb0_ssphy>;
570 phy-names = "usb2-phy", "usb3-phy";
574 snps,is-utmi-l1-suspend;
575 snps,hird-threshold = /bits/ 8 <0x0>;
576 snps,dis_u2_susphy_quirk;
577 snps,dis_u3_susphy_quirk;
582 intc: interrupt-controller@b000000 {
583 compatible = "qcom,msm-qgic2";
584 #address-cells = <2>;
586 interrupt-controller;
587 #interrupt-cells = <3>;
588 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
589 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/
590 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/
591 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/
592 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
593 ranges = <0 0 0 0xb00a000 0 0xffd>;
596 compatible = "arm,gic-v2m-frame";
598 reg = <0x0 0x0 0x0 0xffd>;
603 compatible = "qcom,kpss-wdt";
604 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
605 reg = <0x0 0x0b017000 0x0 0x40>;
606 clocks = <&sleep_clk>;
610 apcs_glb: mailbox@b111000 {
611 compatible = "qcom,ipq6018-apcs-apps-global";
612 reg = <0x0 0x0b111000 0x0 0x1000>;
614 clocks = <&a53pll>, <&xo>;
615 clock-names = "pll", "xo";
619 a53pll: clock@b116000 {
620 compatible = "qcom,ipq6018-a53pll";
621 reg = <0x0 0x0b116000 0x0 0x40>;
628 #address-cells = <1>;
630 ranges = <0 0 0 0x10000000>;
631 compatible = "arm,armv7-timer-mem";
632 reg = <0x0 0x0b120000 0x0 0x1000>;
636 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
638 reg = <0x0b121000 0x1000>,
644 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
645 reg = <0x0b123000 0x1000>;
651 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
652 reg = <0x0b124000 0x1000>;
658 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
659 reg = <0x0b125000 0x1000>;
665 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
666 reg = <0x0b126000 0x1000>;
672 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
673 reg = <0x0b127000 0x1000>;
679 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
680 reg = <0x0b128000 0x1000>;
685 q6v5_wcss: remoteproc@cd00000 {
686 compatible = "qcom,ipq6018-wcss-pil";
687 reg = <0x0 0x0cd00000 0x0 0x4040>,
688 <0x0 0x004ab000 0x0 0x20>;
691 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
692 <&wcss_smp2p_in 0 0>,
693 <&wcss_smp2p_in 1 0>,
694 <&wcss_smp2p_in 2 0>,
695 <&wcss_smp2p_in 3 0>;
696 interrupt-names = "wdog",
702 resets = <&gcc GCC_WCSSAON_RESET>,
704 <&gcc GCC_WCSS_Q6_BCR>;
706 reset-names = "wcss_aon_reset",
710 clocks = <&gcc GCC_PRNG_AHB_CLK>;
711 clock-names = "prng";
713 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
715 qcom,smem-states = <&wcss_smp2p_out 0>,
717 qcom,smem-state-names = "shutdown",
720 memory-region = <&q6_region>;
723 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
725 qcom,remote-pid = <1>;
726 mboxes = <&apcs_glb 8>;
729 qcom,glink-channels = "IPCRTR";
734 pcie0: pci@20000000 {
735 compatible = "qcom,pcie-ipq6018";
736 reg = <0x0 0x20000000 0x0 0xf1d>,
737 <0x0 0x20000f20 0x0 0xa8>,
738 <0x0 0x20001000 0x0 0x1000>,
739 <0x0 0x80000 0x0 0x4000>,
740 <0x0 0x20100000 0x0 0x1000>;
741 reg-names = "dbi", "elbi", "atu", "parf", "config";
744 linux,pci-domain = <0>;
745 bus-range = <0x00 0xff>;
747 max-link-speed = <3>;
748 #address-cells = <3>;
752 phy-names = "pciephy";
754 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
755 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
757 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
758 interrupt-names = "msi";
760 #interrupt-cells = <1>;
761 interrupt-map-mask = <0 0 0 0x7>;
762 interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
763 <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
764 <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
765 <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
767 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
768 <&gcc GCC_PCIE0_AXI_M_CLK>,
769 <&gcc GCC_PCIE0_AXI_S_CLK>,
770 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
771 <&gcc PCIE0_RCHNG_CLK>;
772 clock-names = "iface",
778 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
779 <&gcc GCC_PCIE0_SLEEP_ARES>,
780 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
781 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
782 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
783 <&gcc GCC_PCIE0_AHB_ARES>,
784 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
785 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
786 reset-names = "pipe",
800 compatible = "arm,armv8-timer";
801 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
802 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
803 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
804 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
808 compatible = "qcom,smp2p";
809 qcom,smem = <435>, <428>;
811 interrupt-parent = <&intc>;
812 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
814 mboxes = <&apcs_glb 9>;
816 qcom,local-pid = <0>;
817 qcom,remote-pid = <1>;
819 wcss_smp2p_out: master-kernel {
820 qcom,entry-name = "master-kernel";
821 #qcom,smem-state-cells = <1>;
824 wcss_smp2p_in: slave-kernel {
825 qcom,entry-name = "slave-kernel";
826 interrupt-controller;
827 #interrupt-cells = <2>;