arch/arm64/boot/dts/qcom/ipq6018.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * IPQ6018 SoC device tree source
   4  *
   5  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  11 #include <dt-bindings/clock/qcom,apss-ipq.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&intc>;
  17
  18         clocks {
  19                 sleep_clk: sleep-clk {
  20                         compatible = "fixed-clock";
  21                         clock-frequency = <32000>;
  22                         #clock-cells = <0>;
  23                 };
  24
  25                 xo: xo {
  26                         compatible = "fixed-clock";
  27                         clock-frequency = <24000000>;
  28                         #clock-cells = <0>;
  29                 };
  30         };
  31
  32         cpus: cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 CPU0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         reg = <0x0>;
  40                         enable-method = "psci";
  41                         next-level-cache = <&L2_0>;
  42                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  43                         clock-names = "cpu";
  44                         operating-points-v2 = <&cpu_opp_table>;
  45                         cpu-supply = <&ipq6018_s2>;
  46                 };
  47
  48                 CPU1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         enable-method = "psci";
  52                         reg = <0x1>;
  53                         next-level-cache = <&L2_0>;
  54                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  55                         clock-names = "cpu";
  56                         operating-points-v2 = <&cpu_opp_table>;
  57                         cpu-supply = <&ipq6018_s2>;
  58                 };
  59
  60                 CPU2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         enable-method = "psci";
  64                         reg = <0x2>;
  65                         next-level-cache = <&L2_0>;
  66                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  67                         clock-names = "cpu";
  68                         operating-points-v2 = <&cpu_opp_table>;
  69                         cpu-supply = <&ipq6018_s2>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         enable-method = "psci";
  76                         reg = <0x3>;
  77                         next-level-cache = <&L2_0>;
  78                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  79                         clock-names = "cpu";
  80                         operating-points-v2 = <&cpu_opp_table>;
  81                         cpu-supply = <&ipq6018_s2>;
  82                 };
  83
  84                 L2_0: l2-cache {
  85                         compatible = "cache";
  86                         cache-level = <2>;
  87                         cache-unified;
  88                 };
  89         };
  90
  91         firmware {
  92                 scm {
  93                         compatible = "qcom,scm-ipq6018", "qcom,scm";
  94                         qcom,dload-mode = <&tcsr 0x6100>;
  95                 };
  96         };
  97
  98         cpu_opp_table: opp-table-cpu {
  99                 compatible = "operating-points-v2";
 100                 opp-shared;
 101
 102                 opp-864000000 {
 103                         opp-hz = /bits/ 64 <864000000>;
 104                         opp-microvolt = <725000>;
 105                         clock-latency-ns = <200000>;
 106                 };
 107
 108                 opp-1056000000 {
 109                         opp-hz = /bits/ 64 <1056000000>;
 110                         opp-microvolt = <787500>;
 111                         clock-latency-ns = <200000>;
 112                 };
 113
 114                 opp-1320000000 {
 115                         opp-hz = /bits/ 64 <1320000000>;
 116                         opp-microvolt = <862500>;
 117                         clock-latency-ns = <200000>;
 118                 };
 119
 120                 opp-1440000000 {
 121                         opp-hz = /bits/ 64 <1440000000>;
 122                         opp-microvolt = <925000>;
 123                         clock-latency-ns = <200000>;
 124                 };
 125
 126                 opp-1608000000 {
 127                         opp-hz = /bits/ 64 <1608000000>;
 128                         opp-microvolt = <987500>;
 129                         clock-latency-ns = <200000>;
 130                 };
 131
 132                 opp-1800000000 {
 133                         opp-hz = /bits/ 64 <1800000000>;
 134                         opp-microvolt = <1062500>;
 135                         clock-latency-ns = <200000>;
 136                 };
 137         };
 138
 139         pmuv8: pmu {
 140                 compatible = "arm,cortex-a53-pmu";
 141                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 142         };
 143
 144         psci: psci {
 145                 compatible = "arm,psci-1.0";
 146                 method = "smc";
 147         };
 148
 149         rpm: remoteproc {
 150                 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
 151
 152                 glink-edge {
 153                         compatible = "qcom,glink-rpm";
 154                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 155                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 156                         mboxes = <&apcs_glb 0>;
 157
 158                         rpm_requests: rpm-requests {
 159                                 compatible = "qcom,rpm-ipq6018";
 160                                 qcom,glink-channels = "rpm_requests";
 161
 162                                 regulators {
 163                                         compatible = "qcom,rpm-mp5496-regulators";
 164
 165                                         ipq6018_s2: s2 {
 166                                                 regulator-min-microvolt = <725000>;
 167                                                 regulator-max-microvolt = <1062500>;
 168                                                 regulator-always-on;
 169                                         };
 170                                 };
 171                         };
 172                 };
 173         };
 174
 175         reserved-memory {
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges;
 179
 180                 rpm_msg_ram: memory@60000 {
 181                         reg = <0x0 0x00060000 0x0 0x6000>;
 182                         no-map;
 183                 };
 184
 185                 bootloader@4a100000 {
 186                         reg = <0x0 0x4a100000 0x0 0x400000>;
 187                         no-map;
 188                 };
 189
 190                 sbl@4a500000 {
 191                         reg = <0x0 0x4a500000 0x0 0x100000>;
 192                         no-map;
 193                 };
 194
 195                 tz: memory@4a600000 {
 196                         reg = <0x0 0x4a600000 0x0 0x400000>;
 197                         no-map;
 198                 };
 199
 200                 smem_region: memory@4aa00000 {
 201                         reg = <0x0 0x4aa00000 0x0 0x100000>;
 202                         no-map;
 203                 };
 204
 205                 q6_region: memory@4ab00000 {
 206                         reg = <0x0 0x4ab00000 0x0 0x5500000>;
 207                         no-map;
 208                 };
 209         };
 210
 211         smem {
 212                 compatible = "qcom,smem";
 213                 memory-region = <&smem_region>;
 214                 hwlocks = <&tcsr_mutex 3>;
 215         };
 216
 217         soc: soc@0 {
 218                 #address-cells = <2>;
 219                 #size-cells = <2>;
 220                 ranges = <0 0 0 0 0x0 0xffffffff>;
 221                 dma-ranges;
 222                 compatible = "simple-bus";
 223
 224                 qusb_phy_1: qusb@59000 {
 225                         compatible = "qcom,ipq6018-qusb2-phy";
 226                         reg = <0x0 0x00059000 0x0 0x180>;
 227                         #phy-cells = <0>;
 228
 229                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 230                                  <&xo>;
 231                         clock-names = "cfg_ahb", "ref";
 232
 233                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 234                         status = "disabled";
 235                 };
 236
 237                 ssphy_0: ssphy@78000 {
 238                         compatible = "qcom,ipq6018-qmp-usb3-phy";
 239                         reg = <0x0 0x00078000 0x0 0x1c4>;
 240                         #address-cells = <2>;
 241                         #size-cells = <2>;
 242                         ranges;
 243
 244                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 245                                  <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
 246                         clock-names = "aux", "cfg_ahb", "ref";
 247
 248                         resets = <&gcc GCC_USB0_PHY_BCR>,
 249                                  <&gcc GCC_USB3PHY_0_PHY_BCR>;
 250                         reset-names = "phy","common";
 251                         status = "disabled";
 252
 253                         usb0_ssphy: phy@78200 {
 254                                 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
 255                                       <0x0 0x00078400 0x0 0x200>, /* Rx */
 256                                       <0x0 0x00078800 0x0 0x1f8>, /* PCS */
 257                                       <0x0 0x00078600 0x0 0x044>; /* PCS misc */
 258                                 #phy-cells = <0>;
 259                                 #clock-cells = <0>;
 260                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 261                                 clock-names = "pipe0";
 262                                 clock-output-names = "gcc_usb0_pipe_clk_src";
 263                         };
 264                 };
 265
 266                 qusb_phy_0: qusb@79000 {
 267                         compatible = "qcom,ipq6018-qusb2-phy";
 268                         reg = <0x0 0x00079000 0x0 0x180>;
 269                         #phy-cells = <0>;
 270
 271                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 272                                 <&xo>;
 273                         clock-names = "cfg_ahb", "ref";
 274
 275                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 276                         status = "disabled";
 277                 };
 278
 279                 pcie_phy: phy@84000 {
 280                         compatible = "qcom,ipq6018-qmp-pcie-phy";
 281                         reg = <0x0 0x00084000 0x0 0x1000>;
 282                         status = "disabled";
 283
 284                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 285                                 <&gcc GCC_PCIE0_AHB_CLK>,
 286                                 <&gcc GCC_PCIE0_PIPE_CLK>;
 287                         clock-names = "aux",
 288                                       "cfg_ahb",
 289                                       "pipe";
 290
 291                         clock-output-names = "gcc_pcie0_pipe_clk_src";
 292                         #clock-cells = <0>;
 293
 294                         #phy-cells = <0>;
 295
 296                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 297                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 298                         reset-names = "phy",
 299                                       "common";
 300                 };
 301
 302                 mdio: mdio@90000 {
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
 306                         reg = <0x0 0x00090000 0x0 0x64>;
 307                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 308                         clock-names = "gcc_mdio_ahb_clk";
 309                         status = "disabled";
 310                 };
 311
 312                 qfprom: efuse@a4000 {
 313                         compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
 314                         reg = <0x0 0x000a4000 0x0 0x2000>;
 315                         #address-cells = <1>;
 316                         #size-cells = <1>;
 317                 };
 318
 319                 prng: qrng@e3000 {
 320                         compatible = "qcom,prng-ee";
 321                         reg = <0x0 0x000e3000 0x0 0x1000>;
 322                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 323                         clock-names = "core";
 324                 };
 325
 326                 cryptobam: dma-controller@704000 {
 327                         compatible = "qcom,bam-v1.7.0";
 328                         reg = <0x0 0x00704000 0x0 0x20000>;
 329                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 330                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 331                         clock-names = "bam_clk";
 332                         #dma-cells = <1>;
 333                         qcom,ee = <1>;
 334                         qcom,controlled-remotely;
 335                 };
 336
 337                 crypto: crypto@73a000 {
 338                         compatible = "qcom,crypto-v5.1";
 339                         reg = <0x0 0x0073a000 0x0 0x6000>;
 340                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 341                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 342                                  <&gcc GCC_CRYPTO_CLK>;
 343                         clock-names = "iface", "bus", "core";
 344                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 345                         dma-names = "rx", "tx";
 346                 };
 347
 348                 tlmm: pinctrl@1000000 {
 349                         compatible = "qcom,ipq6018-pinctrl";
 350                         reg = <0x0 0x01000000 0x0 0x300000>;
 351                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 352                         gpio-controller;
 353                         #gpio-cells = <2>;
 354                         gpio-ranges = <&tlmm 0 0 80>;
 355                         interrupt-controller;
 356                         #interrupt-cells = <2>;
 357
 358                         serial_3_pins: serial3-state {
 359                                 pins = "gpio44", "gpio45";
 360                                 function = "blsp2_uart";
 361                                 drive-strength = <8>;
 362                                 bias-pull-down;
 363                         };
 364
 365                         qpic_pins: qpic-state {
 366                                 pins = "gpio1", "gpio3", "gpio4",
 367                                         "gpio5", "gpio6", "gpio7",
 368                                         "gpio8", "gpio10", "gpio11",
 369                                         "gpio12", "gpio13", "gpio14",
 370                                         "gpio15", "gpio17";
 371                                 function = "qpic_pad";
 372                                 drive-strength = <8>;
 373                                 bias-disable;
 374                         };
 375                 };
 376
 377                 gcc: gcc@1800000 {
 378                         compatible = "qcom,gcc-ipq6018";
 379                         reg = <0x0 0x01800000 0x0 0x80000>;
 380                         clocks = <&xo>, <&sleep_clk>;
 381                         clock-names = "xo", "sleep_clk";
 382                         #clock-cells = <1>;
 383                         #reset-cells = <1>;
 384                 };
 385
 386                 tcsr_mutex: hwlock@1905000 {
 387                         compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
 388                         reg = <0x0 0x01905000 0x0 0x20000>;
 389                         #hwlock-cells = <1>;
 390                 };
 391
 392                 tcsr: syscon@1937000 {
 393                         compatible = "qcom,tcsr-ipq6018", "syscon";
 394                         reg = <0x0 0x01937000 0x0 0x21000>;
 395                 };
 396
 397                 usb2: usb@70f8800 {
 398                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 399                         reg = <0x0 0x070f8800 0x0 0x400>;
 400                         #address-cells = <2>;
 401                         #size-cells = <2>;
 402                         ranges;
 403                         clocks = <&gcc GCC_USB1_MASTER_CLK>,
 404                                  <&gcc GCC_USB1_SLEEP_CLK>,
 405                                  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 406                         clock-names = "core",
 407                                       "sleep",
 408                                       "mock_utmi";
 409
 410                         assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
 411                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 412                         assigned-clock-rates = <133330000>,
 413                                                <24000000>;
 414                         resets = <&gcc GCC_USB1_BCR>;
 415                         status = "disabled";
 416
 417                         dwc_1: usb@7000000 {
 418                                 compatible = "snps,dwc3";
 419                                 reg = <0x0 0x07000000 0x0 0xcd00>;
 420                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 421                                 phys = <&qusb_phy_1>;
 422                                 phy-names = "usb2-phy";
 423                                 tx-fifo-resize;
 424                                 snps,is-utmi-l1-suspend;
 425                                 snps,hird-threshold = /bits/ 8 <0x0>;
 426                                 snps,dis_u2_susphy_quirk;
 427                                 snps,dis_u3_susphy_quirk;
 428                                 dr_mode = "host";
 429                         };
 430                 };
 431
 432                 blsp_dma: dma-controller@7884000 {
 433                         compatible = "qcom,bam-v1.7.0";
 434                         reg = <0x0 0x07884000 0x0 0x2b000>;
 435                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 437                         clock-names = "bam_clk";
 438                         #dma-cells = <1>;
 439                         qcom,ee = <0>;
 440                 };
 441
 442                 blsp1_uart3: serial@78b1000 {
 443                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 444                         reg = <0x0 0x078b1000 0x0 0x200>;
 445                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 447                                  <&gcc GCC_BLSP1_AHB_CLK>;
 448                         clock-names = "core", "iface";
 449                         status = "disabled";
 450                 };
 451
 452                 blsp1_spi1: spi@78b5000 {
 453                         compatible = "qcom,spi-qup-v2.2.1";
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         reg = <0x0 0x078b5000 0x0 0x600>;
 457                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 458                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 459                                  <&gcc GCC_BLSP1_AHB_CLK>;
 460                         clock-names = "core", "iface";
 461                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 462                         dma-names = "tx", "rx";
 463                         status = "disabled";
 464                 };
 465
 466                 blsp1_spi2: spi@78b6000 {
 467                         compatible = "qcom,spi-qup-v2.2.1";
 468                         #address-cells = <1>;
 469                         #size-cells = <0>;
 470                         reg = <0x0 0x078b6000 0x0 0x600>;
 471                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 473                                  <&gcc GCC_BLSP1_AHB_CLK>;
 474                         clock-names = "core", "iface";
 475                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 476                         dma-names = "tx", "rx";
 477                         status = "disabled";
 478                 };
 479
 480                 blsp1_i2c2: i2c@78b6000 {
 481                         compatible = "qcom,i2c-qup-v2.2.1";
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         reg = <0x0 0x078b6000 0x0 0x600>;
 485                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 486                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 487                                  <&gcc GCC_BLSP1_AHB_CLK>;
 488                         clock-names = "core", "iface";
 489                         clock-frequency = <400000>;
 490                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 491                         dma-names = "tx", "rx";
 492                         status = "disabled";
 493                 };
 494
 495                 blsp1_i2c3: i2c@78b7000 {
 496                         compatible = "qcom,i2c-qup-v2.2.1";
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         reg = <0x0 0x078b7000 0x0 0x600>;
 500                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 502                                  <&gcc GCC_BLSP1_AHB_CLK>;
 503                         clock-names = "core", "iface";
 504                         clock-frequency = <400000>;
 505                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 506                         dma-names = "tx", "rx";
 507                         status = "disabled";
 508                 };
 509
 510                 qpic_bam: dma-controller@7984000 {
 511                         compatible = "qcom,bam-v1.7.0";
 512                         reg = <0x0 0x07984000 0x0 0x1a000>;
 513                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 514                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 515                         clock-names = "bam_clk";
 516                         #dma-cells = <1>;
 517                         qcom,ee = <0>;
 518                         status = "disabled";
 519                 };
 520
 521                 qpic_nand: nand-controller@79b0000 {
 522                         compatible = "qcom,ipq6018-nand";
 523                         reg = <0x0 0x079b0000 0x0 0x10000>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         clocks = <&gcc GCC_QPIC_CLK>,
 527                                  <&gcc GCC_QPIC_AHB_CLK>;
 528                         clock-names = "core", "aon";
 529
 530                         dmas = <&qpic_bam 0>,
 531                                <&qpic_bam 1>,
 532                                <&qpic_bam 2>;
 533                         dma-names = "tx", "rx", "cmd";
 534                         pinctrl-0 = <&qpic_pins>;
 535                         pinctrl-names = "default";
 536                         status = "disabled";
 537                 };
 538
 539                 usb3: usb@8af8800 {
 540                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 541                         reg = <0x0 0x08af8800 0x0 0x400>;
 542                         #address-cells = <2>;
 543                         #size-cells = <2>;
 544                         ranges;
 545
 546                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 547                                 <&gcc GCC_USB0_MASTER_CLK>,
 548                                 <&gcc GCC_USB0_SLEEP_CLK>,
 549                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 550                         clock-names = "cfg_noc",
 551                                 "core",
 552                                 "sleep",
 553                                 "mock_utmi";
 554
 555                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 556                                           <&gcc GCC_USB0_MASTER_CLK>,
 557                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 558                         assigned-clock-rates = <133330000>,
 559                                                <133330000>,
 560                                                <20000000>;
 561
 562                         resets = <&gcc GCC_USB0_BCR>;
 563                         status = "disabled";
 564
 565                         dwc_0: usb@8a00000 {
 566                                 compatible = "snps,dwc3";
 567                                 reg = <0x0 0x08a00000 0x0 0xcd00>;
 568                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 569                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 570                                 phy-names = "usb2-phy", "usb3-phy";
 571                                 clocks = <&xo>;
 572                                 clock-names = "ref";
 573                                 tx-fifo-resize;
 574                                 snps,is-utmi-l1-suspend;
 575                                 snps,hird-threshold = /bits/ 8 <0x0>;
 576                                 snps,dis_u2_susphy_quirk;
 577                                 snps,dis_u3_susphy_quirk;
 578                                 dr_mode = "host";
 579                         };
 580                 };
 581
 582                 intc: interrupt-controller@b000000 {
 583                         compatible = "qcom,msm-qgic2";
 584                         #address-cells = <2>;
 585                         #size-cells = <2>;
 586                         interrupt-controller;
 587                         #interrupt-cells = <3>;
 588                         reg = <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
 589                               <0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
 590                               <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
 591                               <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
 592                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 593                         ranges = <0 0 0 0xb00a000 0 0xffd>;
 594
 595                         v2m@0 {
 596                                 compatible = "arm,gic-v2m-frame";
 597                                 msi-controller;
 598                                 reg = <0x0 0x0 0x0 0xffd>;
 599                         };
 600                 };
 601
 602                 watchdog@b017000 {
 603                         compatible = "qcom,kpss-wdt";
 604                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 605                         reg = <0x0 0x0b017000 0x0 0x40>;
 606                         clocks = <&sleep_clk>;
 607                         timeout-sec = <10>;
 608                 };
 609
 610                 apcs_glb: mailbox@b111000 {
 611                         compatible = "qcom,ipq6018-apcs-apps-global";
 612                         reg = <0x0 0x0b111000 0x0 0x1000>;
 613                         #clock-cells = <1>;
 614                         clocks = <&a53pll>, <&xo>;
 615                         clock-names = "pll", "xo";
 616                         #mbox-cells = <1>;
 617                 };
 618
 619                 a53pll: clock@b116000 {
 620                         compatible = "qcom,ipq6018-a53pll";
 621                         reg = <0x0 0x0b116000 0x0 0x40>;
 622                         #clock-cells = <0>;
 623                         clocks = <&xo>;
 624                         clock-names = "xo";
 625                 };
 626
 627                 timer@b120000 {
 628                         #address-cells = <1>;
 629                         #size-cells = <1>;
 630                         ranges = <0 0 0 0x10000000>;
 631                         compatible = "arm,armv7-timer-mem";
 632                         reg = <0x0 0x0b120000 0x0 0x1000>;
 633
 634                         frame@b120000 {
 635                                 frame-number = <0>;
 636                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 637                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 638                                 reg = <0x0b121000 0x1000>,
 639                                       <0x0b122000 0x1000>;
 640                         };
 641
 642                         frame@b123000 {
 643                                 frame-number = <1>;
 644                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 645                                 reg = <0x0b123000 0x1000>;
 646                                 status = "disabled";
 647                         };
 648
 649                         frame@b124000 {
 650                                 frame-number = <2>;
 651                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 652                                 reg = <0x0b124000 0x1000>;
 653                                 status = "disabled";
 654                         };
 655
 656                         frame@b125000 {
 657                                 frame-number = <3>;
 658                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 659                                 reg = <0x0b125000 0x1000>;
 660                                 status = "disabled";
 661                         };
 662
 663                         frame@b126000 {
 664                                 frame-number = <4>;
 665                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 666                                 reg = <0x0b126000 0x1000>;
 667                                 status = "disabled";
 668                         };
 669
 670                         frame@b127000 {
 671                                 frame-number = <5>;
 672                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 673                                 reg = <0x0b127000 0x1000>;
 674                                 status = "disabled";
 675                         };
 676
 677                         frame@b128000 {
 678                                 frame-number = <6>;
 679                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 680                                 reg = <0x0b128000 0x1000>;
 681                                 status = "disabled";
 682                         };
 683                 };
 684
 685                 q6v5_wcss: remoteproc@cd00000 {
 686                         compatible = "qcom,ipq6018-wcss-pil";
 687                         reg = <0x0 0x0cd00000 0x0 0x4040>,
 688                               <0x0 0x004ab000 0x0 0x20>;
 689                         reg-names = "qdsp6",
 690                                     "rmb";
 691                         interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
 692                                               <&wcss_smp2p_in 0 0>,
 693                                               <&wcss_smp2p_in 1 0>,
 694                                               <&wcss_smp2p_in 2 0>,
 695                                               <&wcss_smp2p_in 3 0>;
 696                         interrupt-names = "wdog",
 697                                           "fatal",
 698                                           "ready",
 699                                           "handover",
 700                                           "stop-ack";
 701
 702                         resets = <&gcc GCC_WCSSAON_RESET>,
 703                                  <&gcc GCC_WCSS_BCR>,
 704                                  <&gcc GCC_WCSS_Q6_BCR>;
 705
 706                         reset-names = "wcss_aon_reset",
 707                                       "wcss_reset",
 708                                       "wcss_q6_reset";
 709
 710                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 711                         clock-names = "prng";
 712
 713                         qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
 714
 715                         qcom,smem-states = <&wcss_smp2p_out 0>,
 716                                            <&wcss_smp2p_out 1>;
 717                         qcom,smem-state-names = "shutdown",
 718                                                 "stop";
 719
 720                         memory-region = <&q6_region>;
 721
 722                         glink-edge {
 723                                 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
 724                                 label = "rtr";
 725                                 qcom,remote-pid = <1>;
 726                                 mboxes = <&apcs_glb 8>;
 727
 728                                 qrtr_requests {
 729                                         qcom,glink-channels = "IPCRTR";
 730                                 };
 731                         };
 732                 };
 733
 734                 pcie0: pci@20000000 {
 735                         compatible = "qcom,pcie-ipq6018";
 736                         reg = <0x0 0x20000000 0x0 0xf1d>,
 737                               <0x0 0x20000f20 0x0 0xa8>,
 738                               <0x0 0x20001000 0x0 0x1000>,
 739                               <0x0 0x80000 0x0 0x4000>,
 740                               <0x0 0x20100000 0x0 0x1000>;
 741                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 742
 743                         device_type = "pci";
 744                         linux,pci-domain = <0>;
 745                         bus-range = <0x00 0xff>;
 746                         num-lanes = <1>;
 747                         max-link-speed = <3>;
 748                         #address-cells = <3>;
 749                         #size-cells = <2>;
 750
 751                         phys = <&pcie_phy>;
 752                         phy-names = "pciephy";
 753
 754                         ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
 755                                  <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
 756
 757                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 758                         interrupt-names = "msi";
 759
 760                         #interrupt-cells = <1>;
 761                         interrupt-map-mask = <0 0 0 0x7>;
 762                         interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 763                                         <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 764                                         <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 765                                         <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 766
 767                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 768                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 769                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 770                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 771                                  <&gcc PCIE0_RCHNG_CLK>;
 772                         clock-names = "iface",
 773                                       "axi_m",
 774                                       "axi_s",
 775                                       "axi_bridge",
 776                                       "rchng";
 777
 778                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 779                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 780                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 781                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 782                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 783                                  <&gcc GCC_PCIE0_AHB_ARES>,
 784                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 785                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 786                         reset-names = "pipe",
 787                                       "sleep",
 788                                       "sticky",
 789                                       "axi_m",
 790                                       "axi_s",
 791                                       "ahb",
 792                                       "axi_m_sticky",
 793                                       "axi_s_sticky";
 794
 795                         status = "disabled";
 796                 };
 797         };
 798
 799         timer {
 800                 compatible = "arm,armv8-timer";
 801                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 802                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 803                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 804                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 805         };
 806
 807         wcss: wcss-smp2p {
 808                 compatible = "qcom,smp2p";
 809                 qcom,smem = <435>, <428>;
 810
 811                 interrupt-parent = <&intc>;
 812                 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
 813
 814                 mboxes = <&apcs_glb 9>;
 815
 816                 qcom,local-pid = <0>;
 817                 qcom,remote-pid = <1>;
 818
 819                 wcss_smp2p_out: master-kernel {
 820                         qcom,entry-name = "master-kernel";
 821                         #qcom,smem-state-cells = <1>;
 822                 };
 823
 824                 wcss_smp2p_in: slave-kernel {
 825                         qcom,entry-name = "slave-kernel";
 826                         interrupt-controller;
 827                         #interrupt-cells = <2>;
 828                 };
 829         };
 830 };