arch/arm64/boot/dts/qcom/ipq6018.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * IPQ6018 SoC device tree source
   4  *
   5  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  11 #include <dt-bindings/clock/qcom,apss-ipq.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&intc>;
  17
  18         clocks {
  19                 sleep_clk: sleep-clk {
  20                         compatible = "fixed-clock";
  21                         clock-frequency = <32000>;
  22                         #clock-cells = <0>;
  23                 };
  24
  25                 xo: xo {
  26                         compatible = "fixed-clock";
  27                         clock-frequency = <24000000>;
  28                         #clock-cells = <0>;
  29                 };
  30         };
  31
  32         cpus: cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 CPU0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         reg = <0x0>;
  40                         enable-method = "psci";
  41                         next-level-cache = <&L2_0>;
  42                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  43                         clock-names = "cpu";
  44                         operating-points-v2 = <&cpu_opp_table>;
  45                         cpu-supply = <&ipq6018_s2>;
  46                 };
  47
  48                 CPU1: cpu@1 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53";
  51                         enable-method = "psci";
  52                         reg = <0x1>;
  53                         next-level-cache = <&L2_0>;
  54                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  55                         clock-names = "cpu";
  56                         operating-points-v2 = <&cpu_opp_table>;
  57                         cpu-supply = <&ipq6018_s2>;
  58                 };
  59
  60                 CPU2: cpu@2 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         enable-method = "psci";
  64                         reg = <0x2>;
  65                         next-level-cache = <&L2_0>;
  66                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  67                         clock-names = "cpu";
  68                         operating-points-v2 = <&cpu_opp_table>;
  69                         cpu-supply = <&ipq6018_s2>;
  70                 };
  71
  72                 CPU3: cpu@3 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         enable-method = "psci";
  76                         reg = <0x3>;
  77                         next-level-cache = <&L2_0>;
  78                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  79                         clock-names = "cpu";
  80                         operating-points-v2 = <&cpu_opp_table>;
  81                         cpu-supply = <&ipq6018_s2>;
  82                 };
  83
  84                 L2_0: l2-cache {
  85                         compatible = "cache";
  86                         cache-level = <0x2>;
  87                 };
  88         };
  89
  90         cpu_opp_table: opp-table-cpu {
  91                 compatible = "operating-points-v2";
  92                 opp-shared;
  93
  94                 opp-864000000 {
  95                         opp-hz = /bits/ 64 <864000000>;
  96                         opp-microvolt = <725000>;
  97                         clock-latency-ns = <200000>;
  98                 };
  99                 opp-1056000000 {
 100                         opp-hz = /bits/ 64 <1056000000>;
 101                         opp-microvolt = <787500>;
 102                         clock-latency-ns = <200000>;
 103                 };
 104                 opp-1320000000 {
 105                         opp-hz = /bits/ 64 <1320000000>;
 106                         opp-microvolt = <862500>;
 107                         clock-latency-ns = <200000>;
 108                 };
 109                 opp-1440000000 {
 110                         opp-hz = /bits/ 64 <1440000000>;
 111                         opp-microvolt = <925000>;
 112                         clock-latency-ns = <200000>;
 113                 };
 114                 opp-1608000000 {
 115                         opp-hz = /bits/ 64 <1608000000>;
 116                         opp-microvolt = <987500>;
 117                         clock-latency-ns = <200000>;
 118                 };
 119                 opp-1800000000 {
 120                         opp-hz = /bits/ 64 <1800000000>;
 121                         opp-microvolt = <1062500>;
 122                         clock-latency-ns = <200000>;
 123                 };
 124         };
 125
 126         firmware {
 127                 scm {
 128                         compatible = "qcom,scm-ipq6018", "qcom,scm";
 129                 };
 130         };
 131
 132         pmuv8: pmu {
 133                 compatible = "arm,cortex-a53-pmu";
 134                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
 135                                          IRQ_TYPE_LEVEL_HIGH)>;
 136         };
 137
 138         psci: psci {
 139                 compatible = "arm,psci-1.0";
 140                 method = "smc";
 141         };
 142
 143         reserved-memory {
 144                 #address-cells = <2>;
 145                 #size-cells = <2>;
 146                 ranges;
 147
 148                 rpm_msg_ram: memory@60000 {
 149                         reg = <0x0 0x00060000 0x0 0x6000>;
 150                         no-map;
 151                 };
 152
 153                 tz: memory@4a600000 {
 154                         reg = <0x0 0x4a600000 0x0 0x00400000>;
 155                         no-map;
 156                 };
 157
 158                 smem_region: memory@4aa00000 {
 159                         reg = <0x0 0x4aa00000 0x0 0x00100000>;
 160                         no-map;
 161                 };
 162
 163                 q6_region: memory@4ab00000 {
 164                         reg = <0x0 0x4ab00000 0x0 0x05500000>;
 165                         no-map;
 166                 };
 167         };
 168
 169         smem {
 170                 compatible = "qcom,smem";
 171                 memory-region = <&smem_region>;
 172                 hwlocks = <&tcsr_mutex 3>;
 173         };
 174
 175         soc: soc {
 176                 #address-cells = <2>;
 177                 #size-cells = <2>;
 178                 ranges = <0 0 0 0 0x0 0xffffffff>;
 179                 dma-ranges;
 180                 compatible = "simple-bus";
 181
 182                 prng: qrng@e1000 {
 183                         compatible = "qcom,prng-ee";
 184                         reg = <0x0 0x000e3000 0x0 0x1000>;
 185                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 186                         clock-names = "core";
 187                 };
 188
 189                 cryptobam: dma-controller@704000 {
 190                         compatible = "qcom,bam-v1.7.0";
 191                         reg = <0x0 0x00704000 0x0 0x20000>;
 192                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 193                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 194                         clock-names = "bam_clk";
 195                         #dma-cells = <1>;
 196                         qcom,ee = <1>;
 197                         qcom,controlled-remotely;
 198                 };
 199
 200                 crypto: crypto@73a000 {
 201                         compatible = "qcom,crypto-v5.1";
 202                         reg = <0x0 0x0073a000 0x0 0x6000>;
 203                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 204                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 205                                  <&gcc GCC_CRYPTO_CLK>;
 206                         clock-names = "iface", "bus", "core";
 207                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 208                         dma-names = "rx", "tx";
 209                 };
 210
 211                 tlmm: pinctrl@1000000 {
 212                         compatible = "qcom,ipq6018-pinctrl";
 213                         reg = <0x0 0x01000000 0x0 0x300000>;
 214                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 215                         gpio-controller;
 216                         #gpio-cells = <2>;
 217                         gpio-ranges = <&tlmm 0 0 80>;
 218                         interrupt-controller;
 219                         #interrupt-cells = <2>;
 220
 221                         serial_3_pins: serial3-pinmux {
 222                                 pins = "gpio44", "gpio45";
 223                                 function = "blsp2_uart";
 224                                 drive-strength = <8>;
 225                                 bias-pull-down;
 226                         };
 227
 228                         qpic_pins: qpic-pins {
 229                                 pins = "gpio1", "gpio3", "gpio4",
 230                                         "gpio5", "gpio6", "gpio7",
 231                                         "gpio8", "gpio10", "gpio11",
 232                                         "gpio12", "gpio13", "gpio14",
 233                                         "gpio15", "gpio17";
 234                                 function = "qpic_pad";
 235                                 drive-strength = <8>;
 236                                 bias-disable;
 237                         };
 238                 };
 239
 240                 gcc: gcc@1800000 {
 241                         compatible = "qcom,gcc-ipq6018";
 242                         reg = <0x0 0x01800000 0x0 0x80000>;
 243                         clocks = <&xo>, <&sleep_clk>;
 244                         clock-names = "xo", "sleep_clk";
 245                         #clock-cells = <1>;
 246                         #reset-cells = <1>;
 247                 };
 248
 249                 tcsr_mutex: hwlock@1905000 {
 250                         compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
 251                         reg = <0x0 0x01905000 0x0 0x20000>;
 252                         #hwlock-cells = <1>;
 253                 };
 254
 255                 tcsr: syscon@1937000 {
 256                         compatible = "qcom,tcsr-ipq6018", "syscon";
 257                         reg = <0x0 0x01937000 0x0 0x21000>;
 258                 };
 259
 260                 blsp_dma: dma-controller@7884000 {
 261                         compatible = "qcom,bam-v1.7.0";
 262                         reg = <0x0 0x07884000 0x0 0x2b000>;
 263                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 265                         clock-names = "bam_clk";
 266                         #dma-cells = <1>;
 267                         qcom,ee = <0>;
 268                 };
 269
 270                 blsp1_uart3: serial@78b1000 {
 271                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 272                         reg = <0x0 0x078b1000 0x0 0x200>;
 273                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 275                                  <&gcc GCC_BLSP1_AHB_CLK>;
 276                         clock-names = "core", "iface";
 277                         status = "disabled";
 278                 };
 279
 280                 blsp1_spi1: spi@78b5000 {
 281                         compatible = "qcom,spi-qup-v2.2.1";
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         reg = <0x0 0x078b5000 0x0 0x600>;
 285                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 286                         spi-max-frequency = <50000000>;
 287                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 288                                  <&gcc GCC_BLSP1_AHB_CLK>;
 289                         clock-names = "core", "iface";
 290                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 291                         dma-names = "tx", "rx";
 292                         status = "disabled";
 293                 };
 294
 295                 blsp1_spi2: spi@78b6000 {
 296                         compatible = "qcom,spi-qup-v2.2.1";
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         reg = <0x0 0x078b6000 0x0 0x600>;
 300                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 301                         spi-max-frequency = <50000000>;
 302                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 303                                  <&gcc GCC_BLSP1_AHB_CLK>;
 304                         clock-names = "core", "iface";
 305                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 306                         dma-names = "tx", "rx";
 307                         status = "disabled";
 308                 };
 309
 310                 blsp1_i2c2: i2c@78b6000 {
 311                         compatible = "qcom,i2c-qup-v2.2.1";
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         reg = <0x0 0x078b6000 0x0 0x600>;
 315                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 316                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 317                                  <&gcc GCC_BLSP1_AHB_CLK>;
 318                         clock-names = "core", "iface";
 319                         clock-frequency = <400000>;
 320                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 321                         dma-names = "tx", "rx";
 322                         status = "disabled";
 323                 };
 324
 325                 blsp1_i2c3: i2c@78b7000 {
 326                         compatible = "qcom,i2c-qup-v2.2.1";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         reg = <0x0 0x078b7000 0x0 0x600>;
 330                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 332                                  <&gcc GCC_BLSP1_AHB_CLK>;
 333                         clock-names = "core", "iface";
 334                         clock-frequency = <400000>;
 335                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 336                         dma-names = "tx", "rx";
 337                         status = "disabled";
 338                 };
 339
 340                 qpic_bam: dma-controller@7984000 {
 341                         compatible = "qcom,bam-v1.7.0";
 342                         reg = <0x0 0x07984000 0x0 0x1a000>;
 343                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 345                         clock-names = "bam_clk";
 346                         #dma-cells = <1>;
 347                         qcom,ee = <0>;
 348                         status = "disabled";
 349                 };
 350
 351                 qpic_nand: nand@79b0000 {
 352                         compatible = "qcom,ipq6018-nand";
 353                         reg = <0x0 0x079b0000 0x0 0x10000>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         clocks = <&gcc GCC_QPIC_CLK>,
 357                                  <&gcc GCC_QPIC_AHB_CLK>;
 358                         clock-names = "core", "aon";
 359
 360                         dmas = <&qpic_bam 0>,
 361                                <&qpic_bam 1>,
 362                                <&qpic_bam 2>;
 363                         dma-names = "tx", "rx", "cmd";
 364                         pinctrl-0 = <&qpic_pins>;
 365                         pinctrl-names = "default";
 366                         status = "disabled";
 367                 };
 368
 369                 intc: interrupt-controller@b000000 {
 370                         compatible = "qcom,msm-qgic2";
 371                         #address-cells = <2>;
 372                         #size-cells = <2>;
 373                         interrupt-controller;
 374                         #interrupt-cells = <0x3>;
 375                         reg = <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
 376                               <0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
 377                               <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
 378                               <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
 379                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 380                         ranges = <0 0 0 0xb00a000 0 0xffd>;
 381
 382                         v2m@0 {
 383                                 compatible = "arm,gic-v2m-frame";
 384                                 msi-controller;
 385                                 reg = <0x0 0x0 0x0 0xffd>;
 386                         };
 387                 };
 388
 389                 pcie_phy: phy@84000 {
 390                         compatible = "qcom,ipq6018-qmp-pcie-phy";
 391                         reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */
 392                         status = "disabled";
 393                         #address-cells = <2>;
 394                         #size-cells = <2>;
 395                         ranges;
 396
 397                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
 398                                 <&gcc GCC_PCIE0_AHB_CLK>;
 399                         clock-names = "aux", "cfg_ahb";
 400
 401                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 402                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 403                         reset-names = "phy",
 404                                       "common";
 405
 406                         pcie_phy0: phy@84200 {
 407                                 reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */
 408                                       <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */
 409                                       <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */
 410                                       <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */
 411                                 #phy-cells = <0>;
 412
 413                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 414                                 clock-names = "pipe0";
 415                                 clock-output-names = "gcc_pcie0_pipe_clk_src";
 416                                 #clock-cells = <0>;
 417                         };
 418                 };
 419
 420                 pcie0: pci@20000000 {
 421                         compatible = "qcom,pcie-ipq6018";
 422                         reg = <0x0 0x20000000 0x0 0xf1d>,
 423                               <0x0 0x20000f20 0x0 0xa8>,
 424                               <0x0 0x20001000 0x0 0x1000>,
 425                               <0x0 0x80000 0x0 0x4000>,
 426                               <0x0 0x20100000 0x0 0x1000>;
 427                         reg-names = "dbi", "elbi", "atu", "parf", "config";
 428
 429                         device_type = "pci";
 430                         linux,pci-domain = <0>;
 431                         bus-range = <0x00 0xff>;
 432                         num-lanes = <1>;
 433                         max-link-speed = <3>;
 434                         #address-cells = <3>;
 435                         #size-cells = <2>;
 436
 437                         phys = <&pcie_phy0>;
 438                         phy-names = "pciephy";
 439
 440                         ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
 441                                  <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
 442
 443                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 444                         interrupt-names = "msi";
 445
 446                         #interrupt-cells = <1>;
 447                         interrupt-map-mask = <0 0 0 0x7>;
 448                         interrupt-map = <0 0 0 1 &intc 0 75
 449                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 450                                         <0 0 0 2 &intc 0 78
 451                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 452                                         <0 0 0 3 &intc 0 79
 453                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 454                                         <0 0 0 4 &intc 0 83
 455                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 456
 457                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 458                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 459                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 460                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
 461                                  <&gcc PCIE0_RCHNG_CLK>;
 462                         clock-names = "iface",
 463                                       "axi_m",
 464                                       "axi_s",
 465                                       "axi_bridge",
 466                                       "rchng";
 467
 468                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 469                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 470                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 471                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 472                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 473                                  <&gcc GCC_PCIE0_AHB_ARES>,
 474                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
 475                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
 476                         reset-names = "pipe",
 477                                       "sleep",
 478                                       "sticky",
 479                                       "axi_m",
 480                                       "axi_s",
 481                                       "ahb",
 482                                       "axi_m_sticky",
 483                                       "axi_s_sticky";
 484
 485                         status = "disabled";
 486                 };
 487
 488                 watchdog@b017000 {
 489                         compatible = "qcom,kpss-wdt";
 490                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 491                         reg = <0x0 0x0b017000 0x0 0x40>;
 492                         clocks = <&sleep_clk>;
 493                         timeout-sec = <10>;
 494                 };
 495
 496                 apcs_glb: mailbox@b111000 {
 497                         compatible = "qcom,ipq6018-apcs-apps-global";
 498                         reg = <0x0 0x0b111000 0x0 0x1000>;
 499                         #clock-cells = <1>;
 500                         clocks = <&a53pll>, <&xo>;
 501                         clock-names = "pll", "xo";
 502                         #mbox-cells = <1>;
 503                 };
 504
 505                 a53pll: clock@b116000 {
 506                         compatible = "qcom,ipq6018-a53pll";
 507                         reg = <0x0 0x0b116000 0x0 0x40>;
 508                         #clock-cells = <0>;
 509                         clocks = <&xo>;
 510                         clock-names = "xo";
 511                 };
 512
 513                 timer {
 514                         compatible = "arm,armv8-timer";
 515                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 516                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 517                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 518                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 519                 };
 520
 521                 timer@b120000 {
 522                         #address-cells = <1>;
 523                         #size-cells = <1>;
 524                         ranges = <0 0 0 0x10000000>;
 525                         compatible = "arm,armv7-timer-mem";
 526                         reg = <0x0 0x0b120000 0x0 0x1000>;
 527
 528                         frame@b120000 {
 529                                 frame-number = <0>;
 530                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 531                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 532                                 reg = <0x0b121000 0x1000>,
 533                                       <0x0b122000 0x1000>;
 534                         };
 535
 536                         frame@b123000 {
 537                                 frame-number = <1>;
 538                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 539                                 reg = <0x0b123000 0x1000>;
 540                                 status = "disabled";
 541                         };
 542
 543                         frame@b124000 {
 544                                 frame-number = <2>;
 545                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 546                                 reg = <0x0b124000 0x1000>;
 547                                 status = "disabled";
 548                         };
 549
 550                         frame@b125000 {
 551                                 frame-number = <3>;
 552                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 553                                 reg = <0x0b125000 0x1000>;
 554                                 status = "disabled";
 555                         };
 556
 557                         frame@b126000 {
 558                                 frame-number = <4>;
 559                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 560                                 reg = <0x0b126000 0x1000>;
 561                                 status = "disabled";
 562                         };
 563
 564                         frame@b127000 {
 565                                 frame-number = <5>;
 566                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 567                                 reg = <0x0b127000 0x1000>;
 568                                 status = "disabled";
 569                         };
 570
 571                         frame@b128000 {
 572                                 frame-number = <6>;
 573                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 574                                 reg = <0x0b128000 0x1000>;
 575                                 status = "disabled";
 576                         };
 577                 };
 578
 579                 q6v5_wcss: remoteproc@cd00000 {
 580                         compatible = "qcom,ipq6018-wcss-pil";
 581                         reg = <0x0 0x0cd00000 0x0 0x4040>,
 582                               <0x0 0x004ab000 0x0 0x20>;
 583                         reg-names = "qdsp6",
 584                                     "rmb";
 585                         interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
 586                                               <&wcss_smp2p_in 0 0>,
 587                                               <&wcss_smp2p_in 1 0>,
 588                                               <&wcss_smp2p_in 2 0>,
 589                                               <&wcss_smp2p_in 3 0>;
 590                         interrupt-names = "wdog",
 591                                           "fatal",
 592                                           "ready",
 593                                           "handover",
 594                                           "stop-ack";
 595
 596                         resets = <&gcc GCC_WCSSAON_RESET>,
 597                                  <&gcc GCC_WCSS_BCR>,
 598                                  <&gcc GCC_WCSS_Q6_BCR>;
 599
 600                         reset-names = "wcss_aon_reset",
 601                                       "wcss_reset",
 602                                       "wcss_q6_reset";
 603
 604                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 605                         clock-names = "prng";
 606
 607                         qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
 608
 609                         qcom,smem-states = <&wcss_smp2p_out 0>,
 610                                            <&wcss_smp2p_out 1>;
 611                         qcom,smem-state-names = "shutdown",
 612                                                 "stop";
 613
 614                         memory-region = <&q6_region>;
 615
 616                         glink-edge {
 617                                 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
 618                                 label = "rtr";
 619                                 qcom,remote-pid = <1>;
 620                                 mboxes = <&apcs_glb 8>;
 621
 622                                 qrtr_requests {
 623                                         qcom,glink-channels = "IPCRTR";
 624                                 };
 625                         };
 626                 };
 627
 628                 mdio: mdio@90000 {
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631                         compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
 632                         reg = <0x0 0x00090000 0x0 0x64>;
 633                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
 634                         clock-names = "gcc_mdio_ahb_clk";
 635                         status = "disabled";
 636                 };
 637
 638                 qusb_phy_1: qusb@59000 {
 639                         compatible = "qcom,ipq6018-qusb2-phy";
 640                         reg = <0x0 0x00059000 0x0 0x180>;
 641                         #phy-cells = <0>;
 642
 643                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 644                                  <&xo>;
 645                         clock-names = "cfg_ahb", "ref";
 646
 647                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 648                         status = "disabled";
 649                 };
 650
 651                 usb2: usb@70f8800 {
 652                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 653                         reg = <0x0 0x070F8800 0x0 0x400>;
 654                         #address-cells = <2>;
 655                         #size-cells = <2>;
 656                         ranges;
 657                         clocks = <&gcc GCC_USB1_MASTER_CLK>,
 658                                  <&gcc GCC_USB1_SLEEP_CLK>,
 659                                  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 660                         clock-names = "core",
 661                                       "sleep",
 662                                       "mock_utmi";
 663
 664                         assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
 665                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 666                         assigned-clock-rates = <133330000>,
 667                                                <24000000>;
 668                         resets = <&gcc GCC_USB1_BCR>;
 669                         status = "disabled";
 670
 671                         dwc_1: usb@7000000 {
 672                                 compatible = "snps,dwc3";
 673                                 reg = <0x0 0x07000000 0x0 0xcd00>;
 674                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 675                                 phys = <&qusb_phy_1>;
 676                                 phy-names = "usb2-phy";
 677                                 tx-fifo-resize;
 678                                 snps,is-utmi-l1-suspend;
 679                                 snps,hird-threshold = /bits/ 8 <0x0>;
 680                                 snps,dis_u2_susphy_quirk;
 681                                 snps,dis_u3_susphy_quirk;
 682                                 dr_mode = "host";
 683                         };
 684                 };
 685
 686                 ssphy_0: ssphy@78000 {
 687                         compatible = "qcom,ipq6018-qmp-usb3-phy";
 688                         reg = <0x0 0x00078000 0x0 0x1c4>;
 689                         #address-cells = <2>;
 690                         #size-cells = <2>;
 691                         ranges;
 692
 693                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 694                                  <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
 695                         clock-names = "aux", "cfg_ahb", "ref";
 696
 697                         resets = <&gcc GCC_USB0_PHY_BCR>,
 698                                  <&gcc GCC_USB3PHY_0_PHY_BCR>;
 699                         reset-names = "phy","common";
 700                         status = "disabled";
 701
 702                         usb0_ssphy: phy@78200 {
 703                                 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
 704                                       <0x0 0x00078400 0x0 0x200>, /* Rx */
 705                                       <0x0 0x00078800 0x0 0x1f8>, /* PCS */
 706                                       <0x0 0x00078600 0x0 0x044>; /* PCS misc */
 707                                 #phy-cells = <0>;
 708                                 #clock-cells = <0>;
 709                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 710                                 clock-names = "pipe0";
 711                                 clock-output-names = "gcc_usb0_pipe_clk_src";
 712                         };
 713                 };
 714
 715                 qusb_phy_0: qusb@79000 {
 716                         compatible = "qcom,ipq6018-qusb2-phy";
 717                         reg = <0x0 0x00079000 0x0 0x180>;
 718                         #phy-cells = <0>;
 719
 720                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 721                                 <&xo>;
 722                         clock-names = "cfg_ahb", "ref";
 723
 724                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 725                         status = "disabled";
 726                 };
 727
 728                 usb3: usb@8af8800 {
 729                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
 730                         reg = <0x0 0x8af8800 0x0 0x400>;
 731                         #address-cells = <2>;
 732                         #size-cells = <2>;
 733                         ranges;
 734
 735                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 736                                 <&gcc GCC_USB0_MASTER_CLK>,
 737                                 <&gcc GCC_USB0_SLEEP_CLK>,
 738                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 739                         clock-names = "cfg_noc",
 740                                 "core",
 741                                 "sleep",
 742                                 "mock_utmi";
 743
 744                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 745                                           <&gcc GCC_USB0_MASTER_CLK>,
 746                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 747                         assigned-clock-rates = <133330000>,
 748                                                <133330000>,
 749                                                <24000000>;
 750
 751                         resets = <&gcc GCC_USB0_BCR>;
 752                         status = "disabled";
 753
 754                         dwc_0: usb@8a00000 {
 755                                 compatible = "snps,dwc3";
 756                                 reg = <0x0 0x8a00000 0x0 0xcd00>;
 757                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 758                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 759                                 phy-names = "usb2-phy", "usb3-phy";
 760                                 clocks = <&xo>;
 761                                 clock-names = "ref";
 762                                 tx-fifo-resize;
 763                                 snps,is-utmi-l1-suspend;
 764                                 snps,hird-threshold = /bits/ 8 <0x0>;
 765                                 snps,dis_u2_susphy_quirk;
 766                                 snps,dis_u3_susphy_quirk;
 767                                 dr_mode = "host";
 768                         };
 769                 };
 770         };
 771
 772         wcss: wcss-smp2p {
 773                 compatible = "qcom,smp2p";
 774                 qcom,smem = <435>, <428>;
 775
 776                 interrupt-parent = <&intc>;
 777                 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
 778
 779                 mboxes = <&apcs_glb 9>;
 780
 781                 qcom,local-pid = <0>;
 782                 qcom,remote-pid = <1>;
 783
 784                 wcss_smp2p_out: master-kernel {
 785                         qcom,entry-name = "master-kernel";
 786                         #qcom,smem-state-cells = <1>;
 787                 };
 788
 789                 wcss_smp2p_in: slave-kernel {
 790                         qcom,entry-name = "slave-kernel";
 791                         interrupt-controller;
 792                         #interrupt-cells = <2>;
 793                 };
 794         };
 795
 796         rpm-glink {
 797                 compatible = "qcom,glink-rpm";
 798                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 799                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 800                 mboxes = <&apcs_glb 0>;
 801
 802                 rpm_requests: glink-channel {
 803                         compatible = "qcom,rpm-ipq6018";
 804                         qcom,glink-channels = "rpm_requests";
 805
 806                         regulators {
 807                                 compatible = "qcom,rpm-mp5496-regulators";
 808
 809                                 ipq6018_s2: s2 {
 810                                         regulator-min-microvolt = <725000>;
 811                                         regulator-max-microvolt = <1062500>;
 812                                         regulator-always-on;
 813                                 };
 814                         };
 815                 };
 816         };
 817 };