arch/arm64/boot/dts/qcom/ipq5018.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * IPQ5018 SoC device tree source
   4  *
   5  * Copyright (c) 2023 The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
  10 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
  11
  12 / {
  13         interrupt-parent = <&intc>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         clocks {
  18                 sleep_clk: sleep-clk {
  19                         compatible = "fixed-clock";
  20                         #clock-cells = <0>;
  21                 };
  22
  23                 xo_board_clk: xo-board-clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                 };
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 CPU0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         reg = <0x0>;
  37                         enable-method = "psci";
  38                         next-level-cache = <&L2_0>;
  39                 };
  40
  41                 CPU1: cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0x1>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&L2_0>;
  47                 };
  48
  49                 L2_0: l2-cache {
  50                         compatible = "cache";
  51                         cache-level = <2>;
  52                         cache-size = <0x80000>;
  53                         cache-unified;
  54                 };
  55         };
  56
  57         firmware {
  58                 scm {
  59                         compatible = "qcom,scm-ipq5018", "qcom,scm";
  60                         qcom,sdi-enabled;
  61                 };
  62         };
  63
  64         memory@40000000 {
  65                 device_type = "memory";
  66                 /* We expect the bootloader to fill in the size */
  67                 reg = <0x0 0x40000000 0x0 0x0>;
  68         };
  69
  70         pmu {
  71                 compatible = "arm,cortex-a53-pmu";
  72                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  73         };
  74
  75         psci {
  76                 compatible = "arm,psci-1.0";
  77                 method = "smc";
  78         };
  79
  80         reserved-memory {
  81                 #address-cells = <2>;
  82                 #size-cells = <2>;
  83                 ranges;
  84
  85                 tz_region: tz@4ac00000 {
  86                         reg = <0x0 0x4ac00000 0x0 0x200000>;
  87                         no-map;
  88                 };
  89         };
  90
  91         soc: soc@0 {
  92                 compatible = "simple-bus";
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 ranges = <0 0 0 0xffffffff>;
  96
  97                 tlmm: pinctrl@1000000 {
  98                         compatible = "qcom,ipq5018-tlmm";
  99                         reg = <0x01000000 0x300000>;
 100                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 101                         gpio-controller;
 102                         #gpio-cells = <2>;
 103                         gpio-ranges = <&tlmm 0 0 47>;
 104                         interrupt-controller;
 105                         #interrupt-cells = <2>;
 106
 107                         uart1_pins: uart1-state {
 108                                 pins = "gpio31", "gpio32", "gpio33", "gpio34";
 109                                 function = "blsp1_uart1";
 110                                 drive-strength = <8>;
 111                                 bias-pull-down;
 112                         };
 113                 };
 114
 115                 gcc: clock-controller@1800000 {
 116                         compatible = "qcom,gcc-ipq5018";
 117                         reg = <0x01800000 0x80000>;
 118                         clocks = <&xo_board_clk>,
 119                                  <&sleep_clk>,
 120                                  <0>,
 121                                  <0>,
 122                                  <0>,
 123                                  <0>,
 124                                  <0>,
 125                                  <0>,
 126                                  <0>;
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129                         #power-domain-cells = <1>;
 130                 };
 131
 132                 sdhc_1: mmc@7804000 {
 133                         compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
 134                         reg = <0x7804000 0x1000>;
 135                         reg-names = "hc";
 136
 137                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 139                         interrupt-names = "hc_irq", "pwr_irq";
 140
 141                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 142                                  <&gcc GCC_SDCC1_APPS_CLK>,
 143                                  <&xo_board_clk>;
 144                         clock-names = "iface", "core", "xo";
 145                         non-removable;
 146                         status = "disabled";
 147                 };
 148
 149                 blsp1_uart1: serial@78af000 {
 150                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 151                         reg = <0x078af000 0x200>;
 152                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 153                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 154                                  <&gcc GCC_BLSP1_AHB_CLK>;
 155                         clock-names = "core", "iface";
 156                         status = "disabled";
 157                 };
 158
 159                 intc: interrupt-controller@b000000 {
 160                         compatible = "qcom,msm-qgic2";
 161                         reg = <0x0b000000 0x1000>,  /* GICD */
 162                               <0x0b002000 0x2000>,  /* GICC */
 163                               <0x0b001000 0x1000>,  /* GICH */
 164                               <0x0b004000 0x2000>;  /* GICV */
 165                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 166                         interrupt-controller;
 167                         #interrupt-cells = <3>;
 168                         #address-cells = <1>;
 169                         #size-cells = <1>;
 170                         ranges = <0 0x0b00a000 0x1ffa>;
 171
 172                         v2m0: v2m@0 {
 173                                 compatible = "arm,gic-v2m-frame";
 174                                 reg = <0x00000000 0xff8>;
 175                                 msi-controller;
 176                         };
 177
 178                         v2m1: v2m@1000 {
 179                                 compatible = "arm,gic-v2m-frame";
 180                                 reg = <0x00001000 0xff8>;
 181                                 msi-controller;
 182                         };
 183                 };
 184
 185                 watchdog: watchdog@b017000 {
 186                         compatible = "qcom,apss-wdt-ipq5018", "qcom,kpss-wdt";
 187                         reg = <0x0b017000 0x40>;
 188                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 189                         clocks = <&sleep_clk>;
 190                 };
 191
 192                 timer@b120000 {
 193                         compatible = "arm,armv7-timer-mem";
 194                         reg = <0x0b120000 0x1000>;
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197                         ranges;
 198
 199                         frame@b120000 {
 200                                 reg = <0x0b121000 0x1000>,
 201                                       <0x0b122000 0x1000>;
 202                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 203                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 204                                 frame-number = <0>;
 205                         };
 206
 207                         frame@b123000 {
 208                                 reg = <0xb123000 0x1000>;
 209                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 210                                 frame-number = <1>;
 211                                 status = "disabled";
 212                         };
 213
 214                         frame@b124000 {
 215                                 frame-number = <2>;
 216                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 217                                 reg = <0x0b124000 0x1000>;
 218                                 status = "disabled";
 219                         };
 220
 221                         frame@b125000 {
 222                                 reg = <0x0b125000 0x1000>;
 223                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 224                                 frame-number = <3>;
 225                                 status = "disabled";
 226                         };
 227
 228                         frame@b126000 {
 229                                 reg = <0x0b126000 0x1000>;
 230                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 231                                 frame-number = <4>;
 232                                 status = "disabled";
 233                         };
 234
 235                         frame@b127000 {
 236                                 reg = <0x0b127000 0x1000>;
 237                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 238                                 frame-number = <5>;
 239                                 status = "disabled";
 240                         };
 241
 242                         frame@b128000 {
 243                                 reg = <0x0b128000 0x1000>;
 244                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 245                                 frame-number = <6>;
 246                                 status = "disabled";
 247                         };
 248                 };
 249         };
 250
 251         timer {
 252                 compatible = "arm,armv8-timer";
 253                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 254                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 255                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 256                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 257         };
 258 };