1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra210.dtsi"
11 model = "NVIDIA Jetson Nano Developer Kit";
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
16 rtc0 = "/i2c@7000d000/pmic@3c";
17 rtc1 = "/rtc@7000e000";
22 stdout-path = "serial0:115200n8";
26 device_type = "memory";
27 reg = <0x0 0x80000000 0x1 0x0>;
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
35 vddio-pex-ctl-supply = <&vdd_1v8>;
38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
43 nvidia,num-lanes = <4>;
48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
53 reg = <0x000000 0 0 0 0>;
54 local-mac-address = [ 00 00 00 00 00 00 ];
67 avdd-dsi-csi-supply = <&vdd_sys_1v2>;
77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
80 nvidia,xbar-cfg = <2 1 0 3 4>;
81 nvidia,dpaux = <&dpaux>;
87 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
89 hdmi-supply = <&vdd_hdmi>;
91 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
94 nvidia,xbar-cfg = <0 1 2 3 4>;
107 vdd-supply = <&vdd_gpu>;
112 dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
114 nvidia,pins = "dvfs_pwm_pbb1";
115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
121 nvidia,pins = "dvfs_pwm_pbb1";
122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
129 /delete-property/ dmas;
130 /delete-property/ dma-names;
140 clock-frequency = <100000>;
143 compatible = "atmel,24c02";
147 vcc-supply = <&vdd_1v8>;
155 compatible = "atmel,24c02";
159 vcc-supply = <&vdd_1v8>;
167 hdmi_ddc: i2c@7000c700 {
169 clock-frequency = <100000>;
174 clock-frequency = <400000>;
177 compatible = "maxim,max77620";
179 interrupt-parent = <&tegra_pmc>;
180 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
188 pinctrl-names = "default";
189 pinctrl-0 = <&max77620_default>;
193 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
194 maxim,suspend-fps-time-period-us = <5120>;
198 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
199 maxim,suspend-fps-time-period-us = <5120>;
203 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
207 max77620_default: pinmux {
215 function = "fps-out";
216 drive-push-pull = <1>;
217 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
218 maxim,active-fps-power-up-slot = <0>;
219 maxim,active-fps-power-down-slot = <7>;
224 function = "fps-out";
225 drive-open-drain = <1>;
226 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
227 maxim,active-fps-power-up-slot = <0>;
228 maxim,active-fps-power-down-slot = <7>;
233 function = "fps-out";
234 drive-open-drain = <1>;
235 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
236 maxim,active-fps-power-up-slot = <4>;
237 maxim,active-fps-power-down-slot = <3>;
242 function = "32k-out1";
246 pins = "gpio5", "gpio6", "gpio7";
248 drive-push-pull = <1>;
253 in-ldo0-1-supply = <&vdd_pre>;
254 in-ldo2-supply = <&vdd_3v3_sys>;
255 in-ldo3-5-supply = <&vdd_1v8>;
256 in-ldo4-6-supply = <&vdd_5v0_sys>;
257 in-ldo7-8-supply = <&vdd_pre>;
258 in-sd0-supply = <&vdd_5v0_sys>;
259 in-sd1-supply = <&vdd_5v0_sys>;
260 in-sd2-supply = <&vdd_5v0_sys>;
261 in-sd3-supply = <&vdd_5v0_sys>;
264 regulator-name = "VDD_SOC";
265 regulator-min-microvolt = <1000000>;
266 regulator-max-microvolt = <1170000>;
267 regulator-enable-ramp-delay = <146>;
268 regulator-ramp-delay = <27500>;
269 regulator-ramp-delay-scale = <300>;
273 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
274 maxim,active-fps-power-up-slot = <1>;
275 maxim,active-fps-power-down-slot = <6>;
279 regulator-name = "VDD_DDR_1V1_PMIC";
280 regulator-min-microvolt = <1150000>;
281 regulator-max-microvolt = <1150000>;
282 regulator-enable-ramp-delay = <176>;
283 regulator-ramp-delay = <27500>;
284 regulator-ramp-delay-scale = <300>;
288 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
289 maxim,active-fps-power-up-slot = <5>;
290 maxim,active-fps-power-down-slot = <2>;
294 regulator-name = "VDD_PRE_REG_1V35";
295 regulator-min-microvolt = <1350000>;
296 regulator-max-microvolt = <1350000>;
297 regulator-enable-ramp-delay = <176>;
298 regulator-ramp-delay = <27500>;
299 regulator-ramp-delay-scale = <350>;
303 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
304 maxim,active-fps-power-up-slot = <2>;
305 maxim,active-fps-power-down-slot = <5>;
309 regulator-name = "VDD_1V8";
310 regulator-min-microvolt = <1800000>;
311 regulator-max-microvolt = <1800000>;
312 regulator-enable-ramp-delay = <242>;
313 regulator-ramp-delay = <27500>;
314 regulator-ramp-delay-scale = <360>;
318 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
319 maxim,active-fps-power-up-slot = <3>;
320 maxim,active-fps-power-down-slot = <4>;
324 regulator-name = "AVDD_SYS_1V2";
325 regulator-min-microvolt = <1200000>;
326 regulator-max-microvolt = <1200000>;
327 regulator-enable-ramp-delay = <26>;
328 regulator-ramp-delay = <100000>;
329 regulator-ramp-delay-scale = <200>;
333 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
334 maxim,active-fps-power-up-slot = <0>;
335 maxim,active-fps-power-down-slot = <7>;
339 regulator-name = "VDD_PEX_1V05";
340 regulator-min-microvolt = <1050000>;
341 regulator-max-microvolt = <1050000>;
342 regulator-enable-ramp-delay = <22>;
343 regulator-ramp-delay = <100000>;
344 regulator-ramp-delay-scale = <200>;
346 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
347 maxim,active-fps-power-up-slot = <0>;
348 maxim,active-fps-power-down-slot = <7>;
352 regulator-name = "VDDIO_SDMMC";
353 regulator-min-microvolt = <1800000>;
354 regulator-max-microvolt = <3300000>;
355 regulator-enable-ramp-delay = <62>;
356 regulator-ramp-delay = <100000>;
357 regulator-ramp-delay-scale = <200>;
359 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
360 maxim,active-fps-power-up-slot = <0>;
361 maxim,active-fps-power-down-slot = <7>;
369 regulator-name = "VDD_RTC";
370 regulator-min-microvolt = <850000>;
371 regulator-max-microvolt = <1100000>;
372 regulator-enable-ramp-delay = <22>;
373 regulator-ramp-delay = <100000>;
374 regulator-ramp-delay-scale = <200>;
375 regulator-disable-active-discharge;
379 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
380 maxim,active-fps-power-up-slot = <1>;
381 maxim,active-fps-power-down-slot = <6>;
392 avdd_1v05_pll: ldo7 {
393 regulator-name = "AVDD_1V05_PLL";
394 regulator-min-microvolt = <1050000>;
395 regulator-max-microvolt = <1050000>;
396 regulator-enable-ramp-delay = <24>;
397 regulator-ramp-delay = <100000>;
398 regulator-ramp-delay-scale = <200>;
400 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
401 maxim,active-fps-power-up-slot = <3>;
402 maxim,active-fps-power-down-slot = <4>;
406 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
407 regulator-min-microvolt = <1050000>;
408 regulator-max-microvolt = <1050000>;
409 regulator-enable-ramp-delay = <22>;
410 regulator-ramp-delay = <100000>;
411 regulator-ramp-delay-scale = <200>;
413 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
414 maxim,active-fps-power-up-slot = <6>;
415 maxim,active-fps-power-down-slot = <1>;
422 nvidia,invert-interrupt;
423 nvidia,suspend-mode = <0>;
424 nvidia,cpu-pwr-good-time = <0>;
425 nvidia,cpu-pwr-off-time = <0>;
426 nvidia,core-pwr-good-time = <4587 3876>;
427 nvidia,core-pwr-off-time = <39065>;
428 nvidia,core-power-req-active-high;
429 nvidia,sys-clock-req-active-high;
433 nvidia,model = "NVIDIA Jetson Nano HDA";
439 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
440 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
441 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
442 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
443 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
445 avdd-usb-supply = <&vdd_3v3_sys>;
446 dvddio-pex-supply = <&vdd_pex_1v05>;
447 hvddio-pex-supply = <&vdd_1v8>;
455 avdd-pll-utmip-supply = <&vdd_1v8>;
456 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
457 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
458 hvdd-pex-pll-e-supply = <&vdd_1v8>;
466 nvidia,function = "xusb";
471 nvidia,function = "xusb";
476 nvidia,function = "xusb";
487 nvidia,function = "pcie-x1";
492 nvidia,function = "pcie-x4";
497 nvidia,function = "pcie-x4";
502 nvidia,function = "pcie-x4";
507 nvidia,function = "pcie-x4";
512 nvidia,function = "usb3-ss";
517 nvidia,function = "usb3-ss";
530 vbus-supply = <&vdd_5v0_usb>;
533 compatible = "gpio-usb-b-connector",
537 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
554 nvidia,usb2-companion = <1>;
555 vbus-supply = <&vdd_hub_3v3>;
564 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
567 vqmmc-supply = <&vddio_sdmmc>;
568 vmmc-supply = <&vdd_3v3_sd>;
575 vqmmc-supply = <&vdd_1v8>;
576 vmmc-supply = <&vdd_3v3_sys>;
580 keep-power-in-suspend;
587 phy-names = "usb2-0";
588 avddio-usb-supply = <&vdd_3v3_sys>;
589 hvdd-usb-supply = <&vdd_1v8>;
598 nvidia,droop-ctrl = <0x00000f00>;
599 nvidia,force-mode = <1>;
600 nvidia,sample-rate = <25000>;
602 nvidia,pwm-min-microvolts = <708000>;
603 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
605 nvidia,pwm-tristate-microvolts = <1000000>;
606 nvidia,pwm-voltage-step-microvolts = <19200>;
608 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
609 pinctrl-0 = <&dvfs_pwm_active_state>;
610 pinctrl-1 = <&dvfs_pwm_inactive_state>;
627 #address-cells = <1>;
633 i2s3_cif_ep: endpoint {
634 remote-endpoint = <&xbar_i2s3_ep>;
641 i2s3_dap_ep: endpoint {
643 /* Placeholder for external Codec */
653 #address-cells = <1>;
659 i2s4_cif_ep: endpoint {
660 remote-endpoint = <&xbar_i2s4_ep>;
667 i2s4_dap_ep: endpoint {
669 /* Placeholder for external Codec */
679 #address-cells = <1>;
685 sfc1_cif_in_ep: endpoint {
686 remote-endpoint = <&xbar_sfc1_in_ep>;
690 sfc1_out_port: port@1 {
693 sfc1_cif_out_ep: endpoint {
694 remote-endpoint = <&xbar_sfc1_out_ep>;
704 #address-cells = <1>;
710 sfc2_cif_in_ep: endpoint {
711 remote-endpoint = <&xbar_sfc2_in_ep>;
715 sfc2_out_port: port@1 {
718 sfc2_cif_out_ep: endpoint {
719 remote-endpoint = <&xbar_sfc2_out_ep>;
729 #address-cells = <1>;
735 sfc3_cif_in_ep: endpoint {
736 remote-endpoint = <&xbar_sfc3_in_ep>;
740 sfc3_out_port: port@1 {
743 sfc3_cif_out_ep: endpoint {
744 remote-endpoint = <&xbar_sfc3_out_ep>;
754 #address-cells = <1>;
760 sfc4_cif_in_ep: endpoint {
761 remote-endpoint = <&xbar_sfc4_in_ep>;
765 sfc4_out_port: port@1 {
768 sfc4_cif_out_ep: endpoint {
769 remote-endpoint = <&xbar_sfc4_out_ep>;
779 #address-cells = <1>;
785 amx1_in1_ep: endpoint {
786 remote-endpoint = <&xbar_amx1_in1_ep>;
793 amx1_in2_ep: endpoint {
794 remote-endpoint = <&xbar_amx1_in2_ep>;
801 amx1_in3_ep: endpoint {
802 remote-endpoint = <&xbar_amx1_in3_ep>;
809 amx1_in4_ep: endpoint {
810 remote-endpoint = <&xbar_amx1_in4_ep>;
814 amx1_out_port: port@4 {
817 amx1_out_ep: endpoint {
818 remote-endpoint = <&xbar_amx1_out_ep>;
828 #address-cells = <1>;
834 amx2_in1_ep: endpoint {
835 remote-endpoint = <&xbar_amx2_in1_ep>;
842 amx2_in2_ep: endpoint {
843 remote-endpoint = <&xbar_amx2_in2_ep>;
847 amx2_in3_port: port@2 {
850 amx2_in3_ep: endpoint {
851 remote-endpoint = <&xbar_amx2_in3_ep>;
855 amx2_in4_port: port@3 {
858 amx2_in4_ep: endpoint {
859 remote-endpoint = <&xbar_amx2_in4_ep>;
863 amx2_out_port: port@4 {
866 amx2_out_ep: endpoint {
867 remote-endpoint = <&xbar_amx2_out_ep>;
877 #address-cells = <1>;
883 adx1_in_ep: endpoint {
884 remote-endpoint = <&xbar_adx1_in_ep>;
888 adx1_out1_port: port@1 {
891 adx1_out1_ep: endpoint {
892 remote-endpoint = <&xbar_adx1_out1_ep>;
896 adx1_out2_port: port@2 {
899 adx1_out2_ep: endpoint {
900 remote-endpoint = <&xbar_adx1_out2_ep>;
904 adx1_out3_port: port@3 {
907 adx1_out3_ep: endpoint {
908 remote-endpoint = <&xbar_adx1_out3_ep>;
912 adx1_out4_port: port@4 {
915 adx1_out4_ep: endpoint {
916 remote-endpoint = <&xbar_adx1_out4_ep>;
926 #address-cells = <1>;
932 adx2_in_ep: endpoint {
933 remote-endpoint = <&xbar_adx2_in_ep>;
937 adx2_out1_port: port@1 {
940 adx2_out1_ep: endpoint {
941 remote-endpoint = <&xbar_adx2_out1_ep>;
945 adx2_out2_port: port@2 {
948 adx2_out2_ep: endpoint {
949 remote-endpoint = <&xbar_adx2_out2_ep>;
953 adx2_out3_port: port@3 {
956 adx2_out3_ep: endpoint {
957 remote-endpoint = <&xbar_adx2_out3_ep>;
961 adx2_out4_port: port@4 {
964 adx2_out4_ep: endpoint {
965 remote-endpoint = <&xbar_adx2_out4_ep>;
975 #address-cells = <1>;
981 dmic1_cif_ep: endpoint {
982 remote-endpoint = <&xbar_dmic1_ep>;
989 dmic1_dap_ep: endpoint {
990 /* Placeholder for external Codec */
1000 #address-cells = <1>;
1006 dmic2_cif_ep: endpoint {
1007 remote-endpoint = <&xbar_dmic2_ep>;
1011 dmic2_port: port@1 {
1014 dmic2_dap_ep: endpoint {
1015 /* Placeholder for external Codec */
1021 processing-engine@702d8000 {
1025 #address-cells = <1>;
1031 ope1_cif_in_ep: endpoint {
1032 remote-endpoint = <&xbar_ope1_in_ep>;
1036 ope1_out_port: port@1 {
1039 ope1_cif_out_ep: endpoint {
1040 remote-endpoint = <&xbar_ope1_out_ep>;
1046 processing-engine@702d8400 {
1050 #address-cells = <1>;
1056 ope2_cif_in_ep: endpoint {
1057 remote-endpoint = <&xbar_ope2_in_ep>;
1061 ope2_out_port: port@1 {
1064 ope2_cif_out_ep: endpoint {
1065 remote-endpoint = <&xbar_ope2_out_ep>;
1075 #address-cells = <1>;
1081 mvc1_cif_in_ep: endpoint {
1082 remote-endpoint = <&xbar_mvc1_in_ep>;
1086 mvc1_out_port: port@1 {
1089 mvc1_cif_out_ep: endpoint {
1090 remote-endpoint = <&xbar_mvc1_out_ep>;
1100 #address-cells = <1>;
1106 mvc2_cif_in_ep: endpoint {
1107 remote-endpoint = <&xbar_mvc2_in_ep>;
1111 mvc2_out_port: port@1 {
1114 mvc2_cif_out_ep: endpoint {
1115 remote-endpoint = <&xbar_mvc2_out_ep>;
1125 #address-cells = <1>;
1131 mixer_in1_ep: endpoint {
1132 remote-endpoint = <&xbar_mixer_in1_ep>;
1139 mixer_in2_ep: endpoint {
1140 remote-endpoint = <&xbar_mixer_in2_ep>;
1147 mixer_in3_ep: endpoint {
1148 remote-endpoint = <&xbar_mixer_in3_ep>;
1155 mixer_in4_ep: endpoint {
1156 remote-endpoint = <&xbar_mixer_in4_ep>;
1163 mixer_in5_ep: endpoint {
1164 remote-endpoint = <&xbar_mixer_in5_ep>;
1171 mixer_in6_ep: endpoint {
1172 remote-endpoint = <&xbar_mixer_in6_ep>;
1179 mixer_in7_ep: endpoint {
1180 remote-endpoint = <&xbar_mixer_in7_ep>;
1187 mixer_in8_ep: endpoint {
1188 remote-endpoint = <&xbar_mixer_in8_ep>;
1195 mixer_in9_ep: endpoint {
1196 remote-endpoint = <&xbar_mixer_in9_ep>;
1203 mixer_in10_ep: endpoint {
1204 remote-endpoint = <&xbar_mixer_in10_ep>;
1208 mixer_out1_port: port@a {
1211 mixer_out1_ep: endpoint {
1212 remote-endpoint = <&xbar_mixer_out1_ep>;
1216 mixer_out2_port: port@b {
1219 mixer_out2_ep: endpoint {
1220 remote-endpoint = <&xbar_mixer_out2_ep>;
1224 mixer_out3_port: port@c {
1227 mixer_out3_ep: endpoint {
1228 remote-endpoint = <&xbar_mixer_out3_ep>;
1232 mixer_out4_port: port@d {
1235 mixer_out4_ep: endpoint {
1236 remote-endpoint = <&xbar_mixer_out4_ep>;
1240 mixer_out5_port: port@e {
1243 mixer_out5_ep: endpoint {
1244 remote-endpoint = <&xbar_mixer_out5_ep>;
1251 xbar_i2s3_port: port@c {
1254 xbar_i2s3_ep: endpoint {
1255 remote-endpoint = <&i2s3_cif_ep>;
1259 xbar_i2s4_port: port@d {
1262 xbar_i2s4_ep: endpoint {
1263 remote-endpoint = <&i2s4_cif_ep>;
1267 xbar_dmic1_port: port@f {
1270 xbar_dmic1_ep: endpoint {
1271 remote-endpoint = <&dmic1_cif_ep>;
1275 xbar_dmic2_port: port@10 {
1278 xbar_dmic2_ep: endpoint {
1279 remote-endpoint = <&dmic2_cif_ep>;
1283 xbar_sfc1_in_port: port@12 {
1286 xbar_sfc1_in_ep: endpoint {
1287 remote-endpoint = <&sfc1_cif_in_ep>;
1294 xbar_sfc1_out_ep: endpoint {
1295 remote-endpoint = <&sfc1_cif_out_ep>;
1299 xbar_sfc2_in_port: port@14 {
1302 xbar_sfc2_in_ep: endpoint {
1303 remote-endpoint = <&sfc2_cif_in_ep>;
1310 xbar_sfc2_out_ep: endpoint {
1311 remote-endpoint = <&sfc2_cif_out_ep>;
1315 xbar_sfc3_in_port: port@16 {
1318 xbar_sfc3_in_ep: endpoint {
1319 remote-endpoint = <&sfc3_cif_in_ep>;
1326 xbar_sfc3_out_ep: endpoint {
1327 remote-endpoint = <&sfc3_cif_out_ep>;
1331 xbar_sfc4_in_port: port@18 {
1334 xbar_sfc4_in_ep: endpoint {
1335 remote-endpoint = <&sfc4_cif_in_ep>;
1342 xbar_sfc4_out_ep: endpoint {
1343 remote-endpoint = <&sfc4_cif_out_ep>;
1347 xbar_mvc1_in_port: port@1a {
1350 xbar_mvc1_in_ep: endpoint {
1351 remote-endpoint = <&mvc1_cif_in_ep>;
1358 xbar_mvc1_out_ep: endpoint {
1359 remote-endpoint = <&mvc1_cif_out_ep>;
1363 xbar_mvc2_in_port: port@1c {
1366 xbar_mvc2_in_ep: endpoint {
1367 remote-endpoint = <&mvc2_cif_in_ep>;
1374 xbar_mvc2_out_ep: endpoint {
1375 remote-endpoint = <&mvc2_cif_out_ep>;
1379 xbar_amx1_in1_port: port@1e {
1382 xbar_amx1_in1_ep: endpoint {
1383 remote-endpoint = <&amx1_in1_ep>;
1387 xbar_amx1_in2_port: port@1f {
1390 xbar_amx1_in2_ep: endpoint {
1391 remote-endpoint = <&amx1_in2_ep>;
1395 xbar_amx1_in3_port: port@20 {
1398 xbar_amx1_in3_ep: endpoint {
1399 remote-endpoint = <&amx1_in3_ep>;
1403 xbar_amx1_in4_port: port@21 {
1406 xbar_amx1_in4_ep: endpoint {
1407 remote-endpoint = <&amx1_in4_ep>;
1414 xbar_amx1_out_ep: endpoint {
1415 remote-endpoint = <&amx1_out_ep>;
1419 xbar_amx2_in1_port: port@23 {
1422 xbar_amx2_in1_ep: endpoint {
1423 remote-endpoint = <&amx2_in1_ep>;
1427 xbar_amx2_in2_port: port@24 {
1430 xbar_amx2_in2_ep: endpoint {
1431 remote-endpoint = <&amx2_in2_ep>;
1435 xbar_amx2_in3_port: port@25 {
1438 xbar_amx2_in3_ep: endpoint {
1439 remote-endpoint = <&amx2_in3_ep>;
1443 xbar_amx2_in4_port: port@26 {
1446 xbar_amx2_in4_ep: endpoint {
1447 remote-endpoint = <&amx2_in4_ep>;
1454 xbar_amx2_out_ep: endpoint {
1455 remote-endpoint = <&amx2_out_ep>;
1459 xbar_adx1_in_port: port@28 {
1462 xbar_adx1_in_ep: endpoint {
1463 remote-endpoint = <&adx1_in_ep>;
1470 xbar_adx1_out1_ep: endpoint {
1471 remote-endpoint = <&adx1_out1_ep>;
1478 xbar_adx1_out2_ep: endpoint {
1479 remote-endpoint = <&adx1_out2_ep>;
1486 xbar_adx1_out3_ep: endpoint {
1487 remote-endpoint = <&adx1_out3_ep>;
1494 xbar_adx1_out4_ep: endpoint {
1495 remote-endpoint = <&adx1_out4_ep>;
1499 xbar_adx2_in_port: port@2d {
1502 xbar_adx2_in_ep: endpoint {
1503 remote-endpoint = <&adx2_in_ep>;
1510 xbar_adx2_out1_ep: endpoint {
1511 remote-endpoint = <&adx2_out1_ep>;
1518 xbar_adx2_out2_ep: endpoint {
1519 remote-endpoint = <&adx2_out2_ep>;
1526 xbar_adx2_out3_ep: endpoint {
1527 remote-endpoint = <&adx2_out3_ep>;
1534 xbar_adx2_out4_ep: endpoint {
1535 remote-endpoint = <&adx2_out4_ep>;
1539 xbar_mixer_in1_port: port@32 {
1542 xbar_mixer_in1_ep: endpoint {
1543 remote-endpoint = <&mixer_in1_ep>;
1547 xbar_mixer_in2_port: port@33 {
1550 xbar_mixer_in2_ep: endpoint {
1551 remote-endpoint = <&mixer_in2_ep>;
1555 xbar_mixer_in3_port: port@34 {
1558 xbar_mixer_in3_ep: endpoint {
1559 remote-endpoint = <&mixer_in3_ep>;
1563 xbar_mixer_in4_port: port@35 {
1566 xbar_mixer_in4_ep: endpoint {
1567 remote-endpoint = <&mixer_in4_ep>;
1571 xbar_mixer_in5_port: port@36 {
1574 xbar_mixer_in5_ep: endpoint {
1575 remote-endpoint = <&mixer_in5_ep>;
1579 xbar_mixer_in6_port: port@37 {
1582 xbar_mixer_in6_ep: endpoint {
1583 remote-endpoint = <&mixer_in6_ep>;
1587 xbar_mixer_in7_port: port@38 {
1590 xbar_mixer_in7_ep: endpoint {
1591 remote-endpoint = <&mixer_in7_ep>;
1595 xbar_mixer_in8_port: port@39 {
1598 xbar_mixer_in8_ep: endpoint {
1599 remote-endpoint = <&mixer_in8_ep>;
1603 xbar_mixer_in9_port: port@3a {
1606 xbar_mixer_in9_ep: endpoint {
1607 remote-endpoint = <&mixer_in9_ep>;
1611 xbar_mixer_in10_port: port@3b {
1614 xbar_mixer_in10_ep: endpoint {
1615 remote-endpoint = <&mixer_in10_ep>;
1622 xbar_mixer_out1_ep: endpoint {
1623 remote-endpoint = <&mixer_out1_ep>;
1630 xbar_mixer_out2_ep: endpoint {
1631 remote-endpoint = <&mixer_out2_ep>;
1638 xbar_mixer_out3_ep: endpoint {
1639 remote-endpoint = <&mixer_out3_ep>;
1646 xbar_mixer_out4_ep: endpoint {
1647 remote-endpoint = <&mixer_out4_ep>;
1654 xbar_mixer_out5_ep: endpoint {
1655 remote-endpoint = <&mixer_out5_ep>;
1659 xbar_ope1_in_port: port@41 {
1662 xbar_ope1_in_ep: endpoint {
1663 remote-endpoint = <&ope1_cif_in_ep>;
1670 xbar_ope1_out_ep: endpoint {
1671 remote-endpoint = <&ope1_cif_out_ep>;
1675 xbar_ope2_in_port: port@43 {
1678 xbar_ope2_in_ep: endpoint {
1679 remote-endpoint = <&ope2_cif_in_ep>;
1686 xbar_ope2_out_ep: endpoint {
1687 remote-endpoint = <&ope2_cif_out_ep>;
1693 dma-controller@702e2000 {
1697 interrupt-controller@702f9000 {
1706 compatible = "jedec,spi-nor";
1708 spi-max-frequency = <104000000>;
1709 spi-tx-bus-width = <2>;
1710 spi-rx-bus-width = <2>;
1714 clk32k_in: clock-32k {
1715 compatible = "fixed-clock";
1716 clock-frequency = <32768>;
1722 enable-method = "psci";
1726 enable-method = "psci";
1730 enable-method = "psci";
1734 enable-method = "psci";
1745 compatible = "gpio-keys";
1747 key-force-recovery {
1748 label = "Force Recovery";
1749 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
1750 linux,input-type = <EV_KEY>;
1751 linux,code = <BTN_1>;
1752 debounce-interval = <30>;
1757 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1758 linux,input-type = <EV_KEY>;
1759 linux,code = <KEY_POWER>;
1760 debounce-interval = <30>;
1761 wakeup-event-action = <EV_ACT_ASSERTED>;
1767 compatible = "arm,psci-1.0";
1772 compatible = "pwm-fan";
1773 pwms = <&pwm 3 45334>;
1775 cooling-levels = <0 64 128 255>;
1776 #cooling-cells = <2>;
1779 vdd_5v0_sys: regulator-vdd-5v0-sys {
1780 compatible = "regulator-fixed";
1782 regulator-name = "VDD_5V0_SYS";
1783 regulator-min-microvolt = <5000000>;
1784 regulator-max-microvolt = <5000000>;
1785 regulator-always-on;
1789 vdd_3v3_sys: regulator-vdd-3v3-sys {
1790 compatible = "regulator-fixed";
1792 regulator-name = "VDD_3V3_SYS";
1793 regulator-min-microvolt = <3300000>;
1794 regulator-max-microvolt = <3300000>;
1795 regulator-enable-ramp-delay = <240>;
1796 regulator-always-on;
1799 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1802 vin-supply = <&vdd_5v0_sys>;
1805 vdd_3v3_sd: regulator-vdd-3v3-sd {
1806 compatible = "regulator-fixed";
1808 regulator-name = "VDD_3V3_SD";
1809 regulator-min-microvolt = <3300000>;
1810 regulator-max-microvolt = <3300000>;
1812 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1815 vin-supply = <&vdd_3v3_sys>;
1818 vdd_hdmi: regulator-vdd-hdmi-5v0 {
1819 compatible = "regulator-fixed";
1821 regulator-name = "VDD_HDMI_5V0";
1822 regulator-min-microvolt = <5000000>;
1823 regulator-max-microvolt = <5000000>;
1825 vin-supply = <&vdd_5v0_sys>;
1828 vdd_hub_3v3: regulator-vdd-hub-3v3 {
1829 compatible = "regulator-fixed";
1831 regulator-name = "VDD_HUB_3V3";
1832 regulator-min-microvolt = <3300000>;
1833 regulator-max-microvolt = <3300000>;
1835 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1838 vin-supply = <&vdd_5v0_sys>;
1841 vdd_cpu: regulator-vdd-cpu {
1842 compatible = "regulator-fixed";
1844 regulator-name = "VDD_CPU";
1845 regulator-min-microvolt = <5000000>;
1846 regulator-max-microvolt = <5000000>;
1847 regulator-always-on;
1850 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1853 vin-supply = <&vdd_5v0_sys>;
1856 vdd_gpu: regulator-vdd-gpu {
1857 compatible = "pwm-regulator";
1858 pwms = <&pwm 1 8000>;
1860 regulator-name = "VDD_GPU";
1861 regulator-min-microvolt = <710000>;
1862 regulator-max-microvolt = <1320000>;
1863 regulator-ramp-delay = <80>;
1864 regulator-enable-ramp-delay = <2000>;
1865 regulator-settling-time-us = <160>;
1867 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
1868 vin-supply = <&vdd_5v0_sys>;
1871 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {
1872 compatible = "regulator-fixed";
1874 regulator-name = "AVDD_IO_EDP_1V05";
1875 regulator-min-microvolt = <1050000>;
1876 regulator-max-microvolt = <1050000>;
1878 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1881 vin-supply = <&avdd_1v05_pll>;
1884 vdd_5v0_usb: regulator-vdd-5v-usb {
1885 compatible = "regulator-fixed";
1887 regulator-name = "VDD_5V_USB";
1888 regulator-min-microvolt = <50000000>;
1889 regulator-max-microvolt = <50000000>;
1891 vin-supply = <&vdd_5v0_sys>;
1895 compatible = "nvidia,tegra210-audio-graph-card";
1899 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1900 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1901 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1904 <&xbar_i2s3_port>, <&xbar_i2s4_port>,
1905 <&xbar_dmic1_port>, <&xbar_dmic2_port>,
1906 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1907 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1908 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1909 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1910 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1911 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1912 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1913 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1914 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1915 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1916 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1917 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1918 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1919 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
1920 /* HW accelerators */
1921 <&sfc1_out_port>, <&sfc2_out_port>,
1922 <&sfc3_out_port>, <&sfc4_out_port>,
1923 <&mvc1_out_port>, <&mvc2_out_port>,
1924 <&amx1_out_port>, <&amx2_out_port>,
1925 <&adx1_out1_port>, <&adx1_out2_port>,
1926 <&adx1_out3_port>, <&adx1_out4_port>,
1927 <&adx2_out1_port>, <&adx2_out2_port>,
1928 <&adx2_out3_port>, <&adx2_out4_port>,
1929 <&mixer_out1_port>, <&mixer_out2_port>,
1930 <&mixer_out3_port>, <&mixer_out4_port>,
1932 <&ope1_out_port>, <&ope2_out_port>,
1934 <&i2s3_port>, <&i2s4_port>,
1935 <&dmic1_port>, <&dmic2_port>;
1937 label = "NVIDIA Jetson Nano APE";
1943 cpu_trip_critical: critical {
1944 temperature = <96500>;
1950 temperature = <70000>;
1951 hysteresis = <2000>;
1955 cpu_trip_active: active {
1956 temperature = <50000>;
1957 hysteresis = <2000>;
1961 cpu_trip_passive: passive {
1962 temperature = <30000>;
1963 hysteresis = <2000>;
1970 cooling-device = <&fan 3 3>;
1971 trip = <&cpu_trip_critical>;
1975 cooling-device = <&fan 2 2>;
1976 trip = <&cpu_trip_hot>;
1980 cooling-device = <&fan 1 1>;
1981 trip = <&cpu_trip_active>;
1985 cooling-device = <&fan 0 0>;
1986 trip = <&cpu_trip_passive>;