1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra210.dtsi"
11 model = "NVIDIA Jetson Nano Developer Kit";
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
15 ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
16 rtc0 = "/i2c@7000d000/pmic@3c";
17 rtc1 = "/rtc@7000e000";
22 stdout-path = "serial0:115200n8";
26 device_type = "memory";
27 reg = <0x0 0x80000000 0x1 0x0>;
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
35 vddio-pex-ctl-supply = <&vdd_1v8>;
38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
39 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
40 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>,
41 <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
42 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
43 nvidia,num-lanes = <4>;
48 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
53 reg = <0x000000 0 0 0 0>;
54 local-mac-address = [ 00 00 00 00 00 00 ];
67 avdd-dsi-csi-supply = <&vdd_sys_1v2>;
77 avdd-io-hdmi-dp-supply = <&avdd_io_edp_1v05>;
78 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
80 nvidia,xbar-cfg = <2 1 0 3 4>;
81 nvidia,dpaux = <&dpaux>;
87 avdd-io-hdmi-dp-supply = <&avdd_1v05>;
88 vdd-hdmi-dp-pll-supply = <&vdd_1v8>;
89 hdmi-supply = <&vdd_hdmi>;
91 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
92 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1)
94 nvidia,xbar-cfg = <0 1 2 3 4>;
107 vdd-supply = <&vdd_gpu>;
112 dvfs_pwm_active_state: dvfs_pwm_active {
114 nvidia,pins = "dvfs_pwm_pbb1";
115 nvidia,tristate = <TEGRA_PIN_DISABLE>;
119 dvfs_pwm_inactive_state: dvfs_pwm_inactive {
121 nvidia,pins = "dvfs_pwm_pbb1";
122 nvidia,tristate = <TEGRA_PIN_ENABLE>;
138 clock-frequency = <100000>;
141 compatible = "atmel,24c02";
145 vcc-supply = <&vdd_1v8>;
153 compatible = "atmel,24c02";
157 vcc-supply = <&vdd_1v8>;
165 hdmi_ddc: i2c@7000c700 {
167 clock-frequency = <100000>;
172 clock-frequency = <400000>;
175 compatible = "maxim,max77620";
177 interrupt-parent = <&tegra_pmc>;
178 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
186 pinctrl-names = "default";
187 pinctrl-0 = <&max77620_default>;
189 max77620_default: pinmux {
197 function = "fps-out";
198 drive-push-pull = <1>;
199 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
200 maxim,active-fps-power-up-slot = <0>;
201 maxim,active-fps-power-down-slot = <7>;
206 function = "fps-out";
207 drive-open-drain = <1>;
208 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
209 maxim,active-fps-power-up-slot = <0>;
210 maxim,active-fps-power-down-slot = <7>;
215 function = "fps-out";
216 drive-open-drain = <1>;
217 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
218 maxim,active-fps-power-up-slot = <4>;
219 maxim,active-fps-power-down-slot = <3>;
224 function = "32k-out1";
228 pins = "gpio5", "gpio6", "gpio7";
230 drive-push-pull = <1>;
236 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
237 maxim,suspend-fps-time-period-us = <5120>;
241 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
242 maxim,suspend-fps-time-period-us = <5120>;
246 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
251 in-ldo0-1-supply = <&vdd_pre>;
252 in-ldo2-supply = <&vdd_3v3_sys>;
253 in-ldo3-5-supply = <&vdd_1v8>;
254 in-ldo4-6-supply = <&vdd_5v0_sys>;
255 in-ldo7-8-supply = <&vdd_pre>;
256 in-sd0-supply = <&vdd_5v0_sys>;
257 in-sd1-supply = <&vdd_5v0_sys>;
258 in-sd2-supply = <&vdd_5v0_sys>;
259 in-sd3-supply = <&vdd_5v0_sys>;
262 regulator-name = "VDD_SOC";
263 regulator-min-microvolt = <1000000>;
264 regulator-max-microvolt = <1170000>;
265 regulator-enable-ramp-delay = <146>;
266 regulator-ramp-delay = <27500>;
267 regulator-ramp-delay-scale = <300>;
271 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
272 maxim,active-fps-power-up-slot = <1>;
273 maxim,active-fps-power-down-slot = <6>;
277 regulator-name = "VDD_DDR_1V1_PMIC";
278 regulator-min-microvolt = <1150000>;
279 regulator-max-microvolt = <1150000>;
280 regulator-enable-ramp-delay = <176>;
281 regulator-ramp-delay = <27500>;
282 regulator-ramp-delay-scale = <300>;
286 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
287 maxim,active-fps-power-up-slot = <5>;
288 maxim,active-fps-power-down-slot = <2>;
292 regulator-name = "VDD_PRE_REG_1V35";
293 regulator-min-microvolt = <1350000>;
294 regulator-max-microvolt = <1350000>;
295 regulator-enable-ramp-delay = <176>;
296 regulator-ramp-delay = <27500>;
297 regulator-ramp-delay-scale = <350>;
301 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
302 maxim,active-fps-power-up-slot = <2>;
303 maxim,active-fps-power-down-slot = <5>;
307 regulator-name = "VDD_1V8";
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <1800000>;
310 regulator-enable-ramp-delay = <242>;
311 regulator-ramp-delay = <27500>;
312 regulator-ramp-delay-scale = <360>;
316 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
317 maxim,active-fps-power-up-slot = <3>;
318 maxim,active-fps-power-down-slot = <4>;
322 regulator-name = "AVDD_SYS_1V2";
323 regulator-min-microvolt = <1200000>;
324 regulator-max-microvolt = <1200000>;
325 regulator-enable-ramp-delay = <26>;
326 regulator-ramp-delay = <100000>;
327 regulator-ramp-delay-scale = <200>;
331 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
332 maxim,active-fps-power-up-slot = <0>;
333 maxim,active-fps-power-down-slot = <7>;
337 regulator-name = "VDD_PEX_1V05";
338 regulator-min-microvolt = <1050000>;
339 regulator-max-microvolt = <1050000>;
340 regulator-enable-ramp-delay = <22>;
341 regulator-ramp-delay = <100000>;
342 regulator-ramp-delay-scale = <200>;
344 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
345 maxim,active-fps-power-up-slot = <0>;
346 maxim,active-fps-power-down-slot = <7>;
350 regulator-name = "VDDIO_SDMMC";
351 regulator-min-microvolt = <1800000>;
352 regulator-max-microvolt = <3300000>;
353 regulator-enable-ramp-delay = <62>;
354 regulator-ramp-delay = <100000>;
355 regulator-ramp-delay-scale = <200>;
357 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
358 maxim,active-fps-power-up-slot = <0>;
359 maxim,active-fps-power-down-slot = <7>;
367 regulator-name = "VDD_RTC";
368 regulator-min-microvolt = <850000>;
369 regulator-max-microvolt = <1100000>;
370 regulator-enable-ramp-delay = <22>;
371 regulator-ramp-delay = <100000>;
372 regulator-ramp-delay-scale = <200>;
373 regulator-disable-active-discharge;
377 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
378 maxim,active-fps-power-up-slot = <1>;
379 maxim,active-fps-power-down-slot = <6>;
390 avdd_1v05_pll: ldo7 {
391 regulator-name = "AVDD_1V05_PLL";
392 regulator-min-microvolt = <1050000>;
393 regulator-max-microvolt = <1050000>;
394 regulator-enable-ramp-delay = <24>;
395 regulator-ramp-delay = <100000>;
396 regulator-ramp-delay-scale = <200>;
398 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
399 maxim,active-fps-power-up-slot = <3>;
400 maxim,active-fps-power-down-slot = <4>;
404 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
405 regulator-min-microvolt = <1050000>;
406 regulator-max-microvolt = <1050000>;
407 regulator-enable-ramp-delay = <22>;
408 regulator-ramp-delay = <100000>;
409 regulator-ramp-delay-scale = <200>;
411 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
412 maxim,active-fps-power-up-slot = <6>;
413 maxim,active-fps-power-down-slot = <1>;
420 nvidia,invert-interrupt;
421 nvidia,suspend-mode = <0>;
422 nvidia,cpu-pwr-good-time = <0>;
423 nvidia,cpu-pwr-off-time = <0>;
424 nvidia,core-pwr-good-time = <4587 3876>;
425 nvidia,core-pwr-off-time = <39065>;
426 nvidia,core-power-req-active-high;
427 nvidia,sys-clock-req-active-high;
431 nvidia,model = "NVIDIA Jetson Nano HDA";
437 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
438 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
439 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
440 <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
441 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
443 avdd-usb-supply = <&vdd_3v3_sys>;
444 dvddio-pex-supply = <&vdd_pex_1v05>;
445 hvddio-pex-supply = <&vdd_1v8>;
453 avdd-pll-utmip-supply = <&vdd_1v8>;
454 avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
455 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
456 hvdd-pex-pll-e-supply = <&vdd_1v8>;
464 nvidia,function = "xusb";
469 nvidia,function = "xusb";
474 nvidia,function = "xusb";
485 nvidia,function = "pcie-x1";
490 nvidia,function = "pcie-x4";
495 nvidia,function = "pcie-x4";
500 nvidia,function = "pcie-x4";
505 nvidia,function = "pcie-x4";
510 nvidia,function = "usb3-ss";
515 nvidia,function = "usb3-ss";
528 vbus-supply = <&vdd_5v0_usb>;
531 compatible = "gpio-usb-b-connector",
535 vbus-gpios = <&gpio TEGRA_GPIO(CC, 4)
552 nvidia,usb2-companion = <1>;
553 vbus-supply = <&vdd_hub_3v3>;
562 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
565 vqmmc-supply = <&vddio_sdmmc>;
566 vmmc-supply = <&vdd_3v3_sd>;
573 vqmmc-supply = <&vdd_1v8>;
574 vmmc-supply = <&vdd_3v3_sys>;
578 keep-power-in-suspend;
585 phy-names = "usb2-0";
586 avddio-usb-supply = <&vdd_3v3_sys>;
587 hvdd-usb-supply = <&vdd_1v8>;
596 nvidia,droop-ctrl = <0x00000f00>;
597 nvidia,force-mode = <1>;
598 nvidia,sample-rate = <25000>;
600 nvidia,pwm-min-microvolts = <708000>;
601 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
603 nvidia,pwm-tristate-microvolts = <1000000>;
604 nvidia,pwm-voltage-step-microvolts = <19200>;
606 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
607 pinctrl-0 = <&dvfs_pwm_active_state>;
608 pinctrl-1 = <&dvfs_pwm_inactive_state>;
614 dma-controller@702e2000 {
618 interrupt-controller@702f9000 {
633 #address-cells = <1>;
639 i2s3_cif_ep: endpoint {
640 remote-endpoint = <&xbar_i2s3_ep>;
647 i2s3_dap_ep: endpoint {
649 /* Placeholder for external Codec */
659 #address-cells = <1>;
665 i2s4_cif_ep: endpoint {
666 remote-endpoint = <&xbar_i2s4_ep>;
673 i2s4_dap_ep: endpoint {
675 /* Placeholder for external Codec */
685 #address-cells = <1>;
691 dmic1_cif_ep: endpoint {
692 remote-endpoint = <&xbar_dmic1_ep>;
699 dmic1_dap_ep: endpoint {
700 /* Placeholder for external Codec */
710 #address-cells = <1>;
716 dmic2_cif_ep: endpoint {
717 remote-endpoint = <&xbar_dmic2_ep>;
724 dmic2_dap_ep: endpoint {
725 /* Placeholder for external Codec */
735 #address-cells = <1>;
741 sfc1_cif_in_ep: endpoint {
742 remote-endpoint = <&xbar_sfc1_in_ep>;
746 sfc1_out_port: port@1 {
749 sfc1_cif_out_ep: endpoint {
750 remote-endpoint = <&xbar_sfc1_out_ep>;
760 #address-cells = <1>;
766 sfc2_cif_in_ep: endpoint {
767 remote-endpoint = <&xbar_sfc2_in_ep>;
771 sfc2_out_port: port@1 {
774 sfc2_cif_out_ep: endpoint {
775 remote-endpoint = <&xbar_sfc2_out_ep>;
785 #address-cells = <1>;
791 sfc3_cif_in_ep: endpoint {
792 remote-endpoint = <&xbar_sfc3_in_ep>;
796 sfc3_out_port: port@1 {
799 sfc3_cif_out_ep: endpoint {
800 remote-endpoint = <&xbar_sfc3_out_ep>;
810 #address-cells = <1>;
816 sfc4_cif_in_ep: endpoint {
817 remote-endpoint = <&xbar_sfc4_in_ep>;
821 sfc4_out_port: port@1 {
824 sfc4_cif_out_ep: endpoint {
825 remote-endpoint = <&xbar_sfc4_out_ep>;
835 #address-cells = <1>;
841 mvc1_cif_in_ep: endpoint {
842 remote-endpoint = <&xbar_mvc1_in_ep>;
846 mvc1_out_port: port@1 {
849 mvc1_cif_out_ep: endpoint {
850 remote-endpoint = <&xbar_mvc1_out_ep>;
860 #address-cells = <1>;
866 mvc2_cif_in_ep: endpoint {
867 remote-endpoint = <&xbar_mvc2_in_ep>;
871 mvc2_out_port: port@1 {
874 mvc2_cif_out_ep: endpoint {
875 remote-endpoint = <&xbar_mvc2_out_ep>;
885 #address-cells = <1>;
891 amx1_in1_ep: endpoint {
892 remote-endpoint = <&xbar_amx1_in1_ep>;
899 amx1_in2_ep: endpoint {
900 remote-endpoint = <&xbar_amx1_in2_ep>;
907 amx1_in3_ep: endpoint {
908 remote-endpoint = <&xbar_amx1_in3_ep>;
915 amx1_in4_ep: endpoint {
916 remote-endpoint = <&xbar_amx1_in4_ep>;
920 amx1_out_port: port@4 {
923 amx1_out_ep: endpoint {
924 remote-endpoint = <&xbar_amx1_out_ep>;
934 #address-cells = <1>;
940 amx2_in1_ep: endpoint {
941 remote-endpoint = <&xbar_amx2_in1_ep>;
948 amx2_in2_ep: endpoint {
949 remote-endpoint = <&xbar_amx2_in2_ep>;
953 amx2_in3_port: port@2 {
956 amx2_in3_ep: endpoint {
957 remote-endpoint = <&xbar_amx2_in3_ep>;
961 amx2_in4_port: port@3 {
964 amx2_in4_ep: endpoint {
965 remote-endpoint = <&xbar_amx2_in4_ep>;
969 amx2_out_port: port@4 {
972 amx2_out_ep: endpoint {
973 remote-endpoint = <&xbar_amx2_out_ep>;
983 #address-cells = <1>;
989 adx1_in_ep: endpoint {
990 remote-endpoint = <&xbar_adx1_in_ep>;
994 adx1_out1_port: port@1 {
997 adx1_out1_ep: endpoint {
998 remote-endpoint = <&xbar_adx1_out1_ep>;
1002 adx1_out2_port: port@2 {
1005 adx1_out2_ep: endpoint {
1006 remote-endpoint = <&xbar_adx1_out2_ep>;
1010 adx1_out3_port: port@3 {
1013 adx1_out3_ep: endpoint {
1014 remote-endpoint = <&xbar_adx1_out3_ep>;
1018 adx1_out4_port: port@4 {
1021 adx1_out4_ep: endpoint {
1022 remote-endpoint = <&xbar_adx1_out4_ep>;
1032 #address-cells = <1>;
1038 adx2_in_ep: endpoint {
1039 remote-endpoint = <&xbar_adx2_in_ep>;
1043 adx2_out1_port: port@1 {
1046 adx2_out1_ep: endpoint {
1047 remote-endpoint = <&xbar_adx2_out1_ep>;
1051 adx2_out2_port: port@2 {
1054 adx2_out2_ep: endpoint {
1055 remote-endpoint = <&xbar_adx2_out2_ep>;
1059 adx2_out3_port: port@3 {
1062 adx2_out3_ep: endpoint {
1063 remote-endpoint = <&xbar_adx2_out3_ep>;
1067 adx2_out4_port: port@4 {
1070 adx2_out4_ep: endpoint {
1071 remote-endpoint = <&xbar_adx2_out4_ep>;
1077 processing-engine@702d8000 {
1081 #address-cells = <1>;
1087 ope1_cif_in_ep: endpoint {
1088 remote-endpoint = <&xbar_ope1_in_ep>;
1092 ope1_out_port: port@1 {
1095 ope1_cif_out_ep: endpoint {
1096 remote-endpoint = <&xbar_ope1_out_ep>;
1102 processing-engine@702d8400 {
1106 #address-cells = <1>;
1112 ope2_cif_in_ep: endpoint {
1113 remote-endpoint = <&xbar_ope2_in_ep>;
1117 ope2_out_port: port@1 {
1120 ope2_cif_out_ep: endpoint {
1121 remote-endpoint = <&xbar_ope2_out_ep>;
1131 #address-cells = <1>;
1137 mixer_in1_ep: endpoint {
1138 remote-endpoint = <&xbar_mixer_in1_ep>;
1145 mixer_in2_ep: endpoint {
1146 remote-endpoint = <&xbar_mixer_in2_ep>;
1153 mixer_in3_ep: endpoint {
1154 remote-endpoint = <&xbar_mixer_in3_ep>;
1161 mixer_in4_ep: endpoint {
1162 remote-endpoint = <&xbar_mixer_in4_ep>;
1169 mixer_in5_ep: endpoint {
1170 remote-endpoint = <&xbar_mixer_in5_ep>;
1177 mixer_in6_ep: endpoint {
1178 remote-endpoint = <&xbar_mixer_in6_ep>;
1185 mixer_in7_ep: endpoint {
1186 remote-endpoint = <&xbar_mixer_in7_ep>;
1193 mixer_in8_ep: endpoint {
1194 remote-endpoint = <&xbar_mixer_in8_ep>;
1201 mixer_in9_ep: endpoint {
1202 remote-endpoint = <&xbar_mixer_in9_ep>;
1209 mixer_in10_ep: endpoint {
1210 remote-endpoint = <&xbar_mixer_in10_ep>;
1214 mixer_out1_port: port@a {
1217 mixer_out1_ep: endpoint {
1218 remote-endpoint = <&xbar_mixer_out1_ep>;
1222 mixer_out2_port: port@b {
1225 mixer_out2_ep: endpoint {
1226 remote-endpoint = <&xbar_mixer_out2_ep>;
1230 mixer_out3_port: port@c {
1233 mixer_out3_ep: endpoint {
1234 remote-endpoint = <&xbar_mixer_out3_ep>;
1238 mixer_out4_port: port@d {
1241 mixer_out4_ep: endpoint {
1242 remote-endpoint = <&xbar_mixer_out4_ep>;
1246 mixer_out5_port: port@e {
1249 mixer_out5_ep: endpoint {
1250 remote-endpoint = <&xbar_mixer_out5_ep>;
1257 xbar_i2s3_port: port@c {
1260 xbar_i2s3_ep: endpoint {
1261 remote-endpoint = <&i2s3_cif_ep>;
1265 xbar_i2s4_port: port@d {
1268 xbar_i2s4_ep: endpoint {
1269 remote-endpoint = <&i2s4_cif_ep>;
1273 xbar_dmic1_port: port@f {
1276 xbar_dmic1_ep: endpoint {
1277 remote-endpoint = <&dmic1_cif_ep>;
1281 xbar_dmic2_port: port@10 {
1284 xbar_dmic2_ep: endpoint {
1285 remote-endpoint = <&dmic2_cif_ep>;
1289 xbar_sfc1_in_port: port@12 {
1292 xbar_sfc1_in_ep: endpoint {
1293 remote-endpoint = <&sfc1_cif_in_ep>;
1300 xbar_sfc1_out_ep: endpoint {
1301 remote-endpoint = <&sfc1_cif_out_ep>;
1305 xbar_sfc2_in_port: port@14 {
1308 xbar_sfc2_in_ep: endpoint {
1309 remote-endpoint = <&sfc2_cif_in_ep>;
1316 xbar_sfc2_out_ep: endpoint {
1317 remote-endpoint = <&sfc2_cif_out_ep>;
1321 xbar_sfc3_in_port: port@16 {
1324 xbar_sfc3_in_ep: endpoint {
1325 remote-endpoint = <&sfc3_cif_in_ep>;
1332 xbar_sfc3_out_ep: endpoint {
1333 remote-endpoint = <&sfc3_cif_out_ep>;
1337 xbar_sfc4_in_port: port@18 {
1340 xbar_sfc4_in_ep: endpoint {
1341 remote-endpoint = <&sfc4_cif_in_ep>;
1348 xbar_sfc4_out_ep: endpoint {
1349 remote-endpoint = <&sfc4_cif_out_ep>;
1353 xbar_mvc1_in_port: port@1a {
1356 xbar_mvc1_in_ep: endpoint {
1357 remote-endpoint = <&mvc1_cif_in_ep>;
1364 xbar_mvc1_out_ep: endpoint {
1365 remote-endpoint = <&mvc1_cif_out_ep>;
1369 xbar_mvc2_in_port: port@1c {
1372 xbar_mvc2_in_ep: endpoint {
1373 remote-endpoint = <&mvc2_cif_in_ep>;
1380 xbar_mvc2_out_ep: endpoint {
1381 remote-endpoint = <&mvc2_cif_out_ep>;
1385 xbar_amx1_in1_port: port@1e {
1388 xbar_amx1_in1_ep: endpoint {
1389 remote-endpoint = <&amx1_in1_ep>;
1393 xbar_amx1_in2_port: port@1f {
1396 xbar_amx1_in2_ep: endpoint {
1397 remote-endpoint = <&amx1_in2_ep>;
1401 xbar_amx1_in3_port: port@20 {
1404 xbar_amx1_in3_ep: endpoint {
1405 remote-endpoint = <&amx1_in3_ep>;
1409 xbar_amx1_in4_port: port@21 {
1412 xbar_amx1_in4_ep: endpoint {
1413 remote-endpoint = <&amx1_in4_ep>;
1420 xbar_amx1_out_ep: endpoint {
1421 remote-endpoint = <&amx1_out_ep>;
1425 xbar_amx2_in1_port: port@23 {
1428 xbar_amx2_in1_ep: endpoint {
1429 remote-endpoint = <&amx2_in1_ep>;
1433 xbar_amx2_in2_port: port@24 {
1436 xbar_amx2_in2_ep: endpoint {
1437 remote-endpoint = <&amx2_in2_ep>;
1441 xbar_amx2_in3_port: port@25 {
1444 xbar_amx2_in3_ep: endpoint {
1445 remote-endpoint = <&amx2_in3_ep>;
1449 xbar_amx2_in4_port: port@26 {
1452 xbar_amx2_in4_ep: endpoint {
1453 remote-endpoint = <&amx2_in4_ep>;
1460 xbar_amx2_out_ep: endpoint {
1461 remote-endpoint = <&amx2_out_ep>;
1465 xbar_adx1_in_port: port@28 {
1468 xbar_adx1_in_ep: endpoint {
1469 remote-endpoint = <&adx1_in_ep>;
1476 xbar_adx1_out1_ep: endpoint {
1477 remote-endpoint = <&adx1_out1_ep>;
1484 xbar_adx1_out2_ep: endpoint {
1485 remote-endpoint = <&adx1_out2_ep>;
1492 xbar_adx1_out3_ep: endpoint {
1493 remote-endpoint = <&adx1_out3_ep>;
1500 xbar_adx1_out4_ep: endpoint {
1501 remote-endpoint = <&adx1_out4_ep>;
1505 xbar_adx2_in_port: port@2d {
1508 xbar_adx2_in_ep: endpoint {
1509 remote-endpoint = <&adx2_in_ep>;
1516 xbar_adx2_out1_ep: endpoint {
1517 remote-endpoint = <&adx2_out1_ep>;
1524 xbar_adx2_out2_ep: endpoint {
1525 remote-endpoint = <&adx2_out2_ep>;
1532 xbar_adx2_out3_ep: endpoint {
1533 remote-endpoint = <&adx2_out3_ep>;
1540 xbar_adx2_out4_ep: endpoint {
1541 remote-endpoint = <&adx2_out4_ep>;
1545 xbar_mixer_in1_port: port@32 {
1548 xbar_mixer_in1_ep: endpoint {
1549 remote-endpoint = <&mixer_in1_ep>;
1553 xbar_mixer_in2_port: port@33 {
1556 xbar_mixer_in2_ep: endpoint {
1557 remote-endpoint = <&mixer_in2_ep>;
1561 xbar_mixer_in3_port: port@34 {
1564 xbar_mixer_in3_ep: endpoint {
1565 remote-endpoint = <&mixer_in3_ep>;
1569 xbar_mixer_in4_port: port@35 {
1572 xbar_mixer_in4_ep: endpoint {
1573 remote-endpoint = <&mixer_in4_ep>;
1577 xbar_mixer_in5_port: port@36 {
1580 xbar_mixer_in5_ep: endpoint {
1581 remote-endpoint = <&mixer_in5_ep>;
1585 xbar_mixer_in6_port: port@37 {
1588 xbar_mixer_in6_ep: endpoint {
1589 remote-endpoint = <&mixer_in6_ep>;
1593 xbar_mixer_in7_port: port@38 {
1596 xbar_mixer_in7_ep: endpoint {
1597 remote-endpoint = <&mixer_in7_ep>;
1601 xbar_mixer_in8_port: port@39 {
1604 xbar_mixer_in8_ep: endpoint {
1605 remote-endpoint = <&mixer_in8_ep>;
1609 xbar_mixer_in9_port: port@3a {
1612 xbar_mixer_in9_ep: endpoint {
1613 remote-endpoint = <&mixer_in9_ep>;
1617 xbar_mixer_in10_port: port@3b {
1620 xbar_mixer_in10_ep: endpoint {
1621 remote-endpoint = <&mixer_in10_ep>;
1628 xbar_mixer_out1_ep: endpoint {
1629 remote-endpoint = <&mixer_out1_ep>;
1636 xbar_mixer_out2_ep: endpoint {
1637 remote-endpoint = <&mixer_out2_ep>;
1644 xbar_mixer_out3_ep: endpoint {
1645 remote-endpoint = <&mixer_out3_ep>;
1652 xbar_mixer_out4_ep: endpoint {
1653 remote-endpoint = <&mixer_out4_ep>;
1660 xbar_mixer_out5_ep: endpoint {
1661 remote-endpoint = <&mixer_out5_ep>;
1665 xbar_ope1_in_port: port@41 {
1668 xbar_ope1_in_ep: endpoint {
1669 remote-endpoint = <&ope1_cif_in_ep>;
1676 xbar_ope1_out_ep: endpoint {
1677 remote-endpoint = <&ope1_cif_out_ep>;
1681 xbar_ope2_in_port: port@43 {
1684 xbar_ope2_in_ep: endpoint {
1685 remote-endpoint = <&ope2_cif_in_ep>;
1692 xbar_ope2_out_ep: endpoint {
1693 remote-endpoint = <&ope2_cif_out_ep>;
1704 compatible = "jedec,spi-nor";
1706 spi-max-frequency = <104000000>;
1707 spi-tx-bus-width = <2>;
1708 spi-rx-bus-width = <2>;
1712 clk32k_in: clock-32k {
1713 compatible = "fixed-clock";
1714 clock-frequency = <32768>;
1720 enable-method = "psci";
1724 enable-method = "psci";
1728 enable-method = "psci";
1732 enable-method = "psci";
1743 compatible = "pwm-fan";
1744 pwms = <&pwm 3 45334>;
1746 cooling-levels = <0 64 128 255>;
1747 #cooling-cells = <2>;
1753 cpu_trip_critical: critical {
1754 temperature = <96500>;
1760 temperature = <70000>;
1761 hysteresis = <2000>;
1765 cpu_trip_active: active {
1766 temperature = <50000>;
1767 hysteresis = <2000>;
1771 cpu_trip_passive: passive {
1772 temperature = <30000>;
1773 hysteresis = <2000>;
1780 cooling-device = <&fan 3 3>;
1781 trip = <&cpu_trip_critical>;
1785 cooling-device = <&fan 2 2>;
1786 trip = <&cpu_trip_hot>;
1790 cooling-device = <&fan 1 1>;
1791 trip = <&cpu_trip_active>;
1795 cooling-device = <&fan 0 0>;
1796 trip = <&cpu_trip_passive>;
1803 compatible = "gpio-keys";
1807 gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>;
1808 linux,input-type = <EV_KEY>;
1809 linux,code = <KEY_POWER>;
1810 debounce-interval = <30>;
1811 wakeup-event-action = <EV_ACT_ASSERTED>;
1815 key-force-recovery {
1816 label = "Force Recovery";
1817 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
1818 linux,input-type = <EV_KEY>;
1819 linux,code = <BTN_1>;
1820 debounce-interval = <30>;
1825 compatible = "arm,psci-1.0";
1829 vdd_5v0_sys: regulator-vdd-5v0-sys {
1830 compatible = "regulator-fixed";
1832 regulator-name = "VDD_5V0_SYS";
1833 regulator-min-microvolt = <5000000>;
1834 regulator-max-microvolt = <5000000>;
1835 regulator-always-on;
1839 vdd_3v3_sys: regulator-vdd-3v3-sys {
1840 compatible = "regulator-fixed";
1842 regulator-name = "VDD_3V3_SYS";
1843 regulator-min-microvolt = <3300000>;
1844 regulator-max-microvolt = <3300000>;
1845 regulator-enable-ramp-delay = <240>;
1846 regulator-always-on;
1849 gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
1852 vin-supply = <&vdd_5v0_sys>;
1855 vdd_3v3_sd: regulator-vdd-3v3-sd {
1856 compatible = "regulator-fixed";
1858 regulator-name = "VDD_3V3_SD";
1859 regulator-min-microvolt = <3300000>;
1860 regulator-max-microvolt = <3300000>;
1862 gpio = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
1865 vin-supply = <&vdd_3v3_sys>;
1868 vdd_hdmi: regulator-vdd-hdmi-5v0 {
1869 compatible = "regulator-fixed";
1871 regulator-name = "VDD_HDMI_5V0";
1872 regulator-min-microvolt = <5000000>;
1873 regulator-max-microvolt = <5000000>;
1875 vin-supply = <&vdd_5v0_sys>;
1878 vdd_hub_3v3: regulator-vdd-hub-3v3 {
1879 compatible = "regulator-fixed";
1881 regulator-name = "VDD_HUB_3V3";
1882 regulator-min-microvolt = <3300000>;
1883 regulator-max-microvolt = <3300000>;
1885 gpio = <&gpio TEGRA_GPIO(A, 6) GPIO_ACTIVE_HIGH>;
1888 vin-supply = <&vdd_5v0_sys>;
1891 vdd_cpu: regulator-vdd-cpu {
1892 compatible = "regulator-fixed";
1894 regulator-name = "VDD_CPU";
1895 regulator-min-microvolt = <5000000>;
1896 regulator-max-microvolt = <5000000>;
1897 regulator-always-on;
1900 gpio = <&pmic 5 GPIO_ACTIVE_HIGH>;
1903 vin-supply = <&vdd_5v0_sys>;
1906 vdd_gpu: regulator-vdd-gpu {
1907 compatible = "pwm-regulator";
1908 pwms = <&pwm 1 8000>;
1910 regulator-name = "VDD_GPU";
1911 regulator-min-microvolt = <710000>;
1912 regulator-max-microvolt = <1320000>;
1913 regulator-ramp-delay = <80>;
1914 regulator-enable-ramp-delay = <2000>;
1915 regulator-settling-time-us = <160>;
1917 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
1918 vin-supply = <&vdd_5v0_sys>;
1921 avdd_io_edp_1v05: regulator-avdd-io-epd-1v05 {
1922 compatible = "regulator-fixed";
1924 regulator-name = "AVDD_IO_EDP_1V05";
1925 regulator-min-microvolt = <1050000>;
1926 regulator-max-microvolt = <1050000>;
1928 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1931 vin-supply = <&avdd_1v05_pll>;
1934 vdd_5v0_usb: regulator-vdd-5v-usb {
1935 compatible = "regulator-fixed";
1937 regulator-name = "VDD_5V_USB";
1938 regulator-min-microvolt = <50000000>;
1939 regulator-max-microvolt = <50000000>;
1941 vin-supply = <&vdd_5v0_sys>;
1945 compatible = "nvidia,tegra210-audio-graph-card";
1949 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
1950 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>,
1951 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>,
1954 <&xbar_i2s3_port>, <&xbar_i2s4_port>,
1955 <&xbar_dmic1_port>, <&xbar_dmic2_port>,
1956 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>,
1957 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>,
1958 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>,
1959 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>,
1960 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>,
1961 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>,
1962 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>,
1963 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>,
1964 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>,
1965 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>,
1966 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>,
1967 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>,
1968 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>,
1969 <&xbar_ope1_in_port>, <&xbar_ope2_in_port>,
1970 /* HW accelerators */
1971 <&sfc1_out_port>, <&sfc2_out_port>,
1972 <&sfc3_out_port>, <&sfc4_out_port>,
1973 <&mvc1_out_port>, <&mvc2_out_port>,
1974 <&amx1_out_port>, <&amx2_out_port>,
1975 <&adx1_out1_port>, <&adx1_out2_port>,
1976 <&adx1_out3_port>, <&adx1_out4_port>,
1977 <&adx2_out1_port>, <&adx2_out2_port>,
1978 <&adx2_out3_port>, <&adx2_out4_port>,
1979 <&mixer_out1_port>, <&mixer_out2_port>,
1980 <&mixer_out3_port>, <&mixer_out4_port>,
1982 <&ope1_out_port>, <&ope2_out_port>,
1984 <&i2s3_port>, <&i2s4_port>,
1985 <&dmic1_port>, <&dmic2_port>;
1987 label = "NVIDIA Jetson Nano APE";