1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/reset/tegra194-reset.h>
9 compatible = "nvidia,tegra194";
10 interrupt-parent = <&gic>;
14 /* control backbone */
16 compatible = "simple-bus";
19 ranges = <0x0 0x0 0x0 0x40000000>;
22 compatible = "nvidia,tegra194-gpio";
23 reg-names = "security", "gpio";
24 reg = <0x2200000 0x10000>,
26 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
27 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
32 #interrupt-cells = <2>;
39 compatible = "nvidia,tegra186-eqos",
40 "snps,dwc-qos-ethernet-4.10";
41 reg = <0x02490000 0x10000>;
42 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
44 <&bpmp TEGRA194_CLK_EQOS_AXI>,
45 <&bpmp TEGRA194_CLK_EQOS_RX>,
46 <&bpmp TEGRA194_CLK_EQOS_TX>,
47 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
48 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
49 resets = <&bpmp TEGRA194_RESET_EQOS>;
53 snps,write-requests = <1>;
54 snps,read-requests = <3>;
55 snps,burst-map = <0x7>;
60 uarta: serial@3100000 {
61 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
62 reg = <0x03100000 0x40>;
64 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&bpmp TEGRA194_CLK_UARTA>;
66 clock-names = "serial";
67 resets = <&bpmp TEGRA194_RESET_UARTA>;
68 reset-names = "serial";
72 uartb: serial@3110000 {
73 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
74 reg = <0x03110000 0x40>;
76 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&bpmp TEGRA194_CLK_UARTB>;
78 clock-names = "serial";
79 resets = <&bpmp TEGRA194_RESET_UARTB>;
80 reset-names = "serial";
84 uartd: serial@3130000 {
85 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
86 reg = <0x03130000 0x40>;
88 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&bpmp TEGRA194_CLK_UARTD>;
90 clock-names = "serial";
91 resets = <&bpmp TEGRA194_RESET_UARTD>;
92 reset-names = "serial";
96 uarte: serial@3140000 {
97 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
98 reg = <0x03140000 0x40>;
100 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&bpmp TEGRA194_CLK_UARTE>;
102 clock-names = "serial";
103 resets = <&bpmp TEGRA194_RESET_UARTE>;
104 reset-names = "serial";
108 uartf: serial@3150000 {
109 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
110 reg = <0x03150000 0x40>;
112 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&bpmp TEGRA194_CLK_UARTF>;
114 clock-names = "serial";
115 resets = <&bpmp TEGRA194_RESET_UARTF>;
116 reset-names = "serial";
120 gen1_i2c: i2c@3160000 {
121 compatible = "nvidia,tegra194-i2c";
122 reg = <0x03160000 0x10000>;
123 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
126 clocks = <&bpmp TEGRA194_CLK_I2C1>;
127 clock-names = "div-clk";
128 resets = <&bpmp TEGRA194_RESET_I2C1>;
133 uarth: serial@3170000 {
134 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
135 reg = <0x03170000 0x40>;
137 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&bpmp TEGRA194_CLK_UARTH>;
139 clock-names = "serial";
140 resets = <&bpmp TEGRA194_RESET_UARTH>;
141 reset-names = "serial";
145 cam_i2c: i2c@3180000 {
146 compatible = "nvidia,tegra194-i2c";
147 reg = <0x03180000 0x10000>;
148 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
149 #address-cells = <1>;
151 clocks = <&bpmp TEGRA194_CLK_I2C3>;
152 clock-names = "div-clk";
153 resets = <&bpmp TEGRA194_RESET_I2C3>;
158 /* shares pads with dpaux1 */
159 dp_aux_ch1_i2c: i2c@3190000 {
160 compatible = "nvidia,tegra194-i2c";
161 reg = <0x03190000 0x10000>;
162 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
163 #address-cells = <1>;
165 clocks = <&bpmp TEGRA194_CLK_I2C4>;
166 clock-names = "div-clk";
167 resets = <&bpmp TEGRA194_RESET_I2C4>;
172 /* shares pads with dpaux0 */
173 dp_aux_ch0_i2c: i2c@31b0000 {
174 compatible = "nvidia,tegra194-i2c";
175 reg = <0x031b0000 0x10000>;
176 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
177 #address-cells = <1>;
179 clocks = <&bpmp TEGRA194_CLK_I2C6>;
180 clock-names = "div-clk";
181 resets = <&bpmp TEGRA194_RESET_I2C6>;
186 gen7_i2c: i2c@31c0000 {
187 compatible = "nvidia,tegra194-i2c";
188 reg = <0x031c0000 0x10000>;
189 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
190 #address-cells = <1>;
192 clocks = <&bpmp TEGRA194_CLK_I2C7>;
193 clock-names = "div-clk";
194 resets = <&bpmp TEGRA194_RESET_I2C7>;
199 gen9_i2c: i2c@31e0000 {
200 compatible = "nvidia,tegra194-i2c";
201 reg = <0x031e0000 0x10000>;
202 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
203 #address-cells = <1>;
205 clocks = <&bpmp TEGRA194_CLK_I2C9>;
206 clock-names = "div-clk";
207 resets = <&bpmp TEGRA194_RESET_I2C9>;
212 sdmmc1: sdhci@3400000 {
213 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
214 reg = <0x03400000 0x10000>;
215 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
217 clock-names = "sdhci";
218 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
219 reset-names = "sdhci";
223 sdmmc3: sdhci@3440000 {
224 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
225 reg = <0x03440000 0x10000>;
226 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
228 clock-names = "sdhci";
229 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
230 reset-names = "sdhci";
234 sdmmc4: sdhci@3460000 {
235 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
236 reg = <0x03460000 0x10000>;
237 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
239 clock-names = "sdhci";
240 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
241 reset-names = "sdhci";
245 gic: interrupt-controller@3881000 {
246 compatible = "arm,gic-400";
247 #interrupt-cells = <3>;
248 interrupt-controller;
249 reg = <0x03881000 0x1000>,
253 interrupts = <GIC_PPI 9
254 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
255 interrupt-parent = <&gic>;
258 hsp_top0: hsp@3c00000 {
259 compatible = "nvidia,tegra186-hsp";
260 reg = <0x03c00000 0xa0000>;
261 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-names = "doorbell";
266 gen2_i2c: i2c@c240000 {
267 compatible = "nvidia,tegra194-i2c";
268 reg = <0x0c240000 0x10000>;
269 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
270 #address-cells = <1>;
272 clocks = <&bpmp TEGRA194_CLK_I2C2>;
273 clock-names = "div-clk";
274 resets = <&bpmp TEGRA194_RESET_I2C2>;
279 gen8_i2c: i2c@c250000 {
280 compatible = "nvidia,tegra194-i2c";
281 reg = <0x0c250000 0x10000>;
282 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <1>;
285 clocks = <&bpmp TEGRA194_CLK_I2C8>;
286 clock-names = "div-clk";
287 resets = <&bpmp TEGRA194_RESET_I2C8>;
292 uartc: serial@c280000 {
293 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
294 reg = <0x0c280000 0x40>;
296 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&bpmp TEGRA194_CLK_UARTC>;
298 clock-names = "serial";
299 resets = <&bpmp TEGRA194_RESET_UARTC>;
300 reset-names = "serial";
304 uartg: serial@c290000 {
305 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
306 reg = <0x0c290000 0x40>;
308 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&bpmp TEGRA194_CLK_UARTG>;
310 clock-names = "serial";
311 resets = <&bpmp TEGRA194_RESET_UARTG>;
312 reset-names = "serial";
317 compatible = "nvidia,tegra194-pmc";
318 reg = <0x0c360000 0x10000>,
319 <0x0c370000 0x10000>,
320 <0x0c380000 0x10000>,
321 <0x0c390000 0x10000>,
322 <0x0c3a0000 0x10000>;
323 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
328 compatible = "nvidia,tegra194-sysram", "mmio-sram";
329 reg = <0x0 0x40000000 0x0 0x50000>;
330 #address-cells = <1>;
332 ranges = <0x0 0x0 0x40000000 0x50000>;
334 cpu_bpmp_tx: shmem@4e000 {
335 compatible = "nvidia,tegra194-bpmp-shmem";
336 reg = <0x4e000 0x1000>;
337 label = "cpu-bpmp-tx";
341 cpu_bpmp_rx: shmem@4f000 {
342 compatible = "nvidia,tegra194-bpmp-shmem";
343 reg = <0x4f000 0x1000>;
344 label = "cpu-bpmp-rx";
350 compatible = "nvidia,tegra186-bpmp";
351 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
352 TEGRA_HSP_DB_MASTER_BPMP>;
353 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
356 #power-domain-cells = <1>;
359 compatible = "nvidia,tegra186-bpmp-i2c";
360 nvidia,bpmp-bus-id = <5>;
361 #address-cells = <1>;
365 bpmp_thermal: thermal {
366 compatible = "nvidia,tegra186-bpmp-thermal";
367 #thermal-sensor-cells = <1>;
372 #address-cells = <1>;
376 compatible = "nvidia,tegra194-carmel", "arm,armv8";
379 enable-method = "psci";
383 compatible = "nvidia,tegra194-carmel", "arm,armv8";
386 enable-method = "psci";
390 compatible = "nvidia,tegra194-carmel", "arm,armv8";
393 enable-method = "psci";
397 compatible = "nvidia,tegra194-carmel", "arm,armv8";
400 enable-method = "psci";
404 compatible = "nvidia,tegra194-carmel", "arm,armv8";
407 enable-method = "psci";
411 compatible = "nvidia,tegra194-carmel", "arm,armv8";
414 enable-method = "psci";
418 compatible = "nvidia,tegra194-carmel", "arm,armv8";
421 enable-method = "psci";
425 compatible = "nvidia,tegra194-carmel", "arm,armv8";
428 enable-method = "psci";
433 compatible = "arm,psci-1.0";
439 compatible = "arm,armv8-timer";
440 interrupts = <GIC_PPI 13
441 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
443 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
445 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
447 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
448 interrupt-parent = <&gic>;