arch/arm64/boot/dts/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/reset/tegra194-reset.h>
   9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
  10
  11 / {
  12         compatible = "nvidia,tegra194";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         /* control backbone */
  18         cbb {
  19                 compatible = "simple-bus";
  20                 #address-cells = <1>;
  21                 #size-cells = <1>;
  22                 ranges = <0x0 0x0 0x0 0x40000000>;
  23
  24                 gpio: gpio@2200000 {
  25                         compatible = "nvidia,tegra194-gpio";
  26                         reg-names = "security", "gpio";
  27                         reg = <0x2200000 0x10000>,
  28                               <0x2210000 0x10000>;
  29                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  30                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  31                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  32                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  33                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  34                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  35                         #interrupt-cells = <2>;
  36                         interrupt-controller;
  37                         #gpio-cells = <2>;
  38                         gpio-controller;
  39                 };
  40
  41                 ethernet@2490000 {
  42                         compatible = "nvidia,tegra186-eqos",
  43                                      "snps,dwc-qos-ethernet-4.10";
  44                         reg = <0x02490000 0x10000>;
  45                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  46                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  47                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  48                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  49                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  50                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  51                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  52                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  53                         reset-names = "eqos";
  54                         status = "disabled";
  55
  56                         snps,write-requests = <1>;
  57                         snps,read-requests = <3>;
  58                         snps,burst-map = <0x7>;
  59                         snps,txpbl = <16>;
  60                         snps,rxpbl = <8>;
  61                 };
  62
  63                 aconnect {
  64                         compatible = "nvidia,tegra194-aconnect",
  65                                      "nvidia,tegra210-aconnect";
  66                         clocks = <&bpmp TEGRA194_CLK_APE>,
  67                                  <&bpmp TEGRA194_CLK_APB2APE>;
  68                         clock-names = "ape", "apb2ape";
  69                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
  70                         #address-cells = <1>;
  71                         #size-cells = <1>;
  72                         ranges = <0x02900000 0x02900000 0x200000>;
  73                         status = "disabled";
  74
  75                         dma-controller@2930000 {
  76                                 compatible = "nvidia,tegra194-adma",
  77                                              "nvidia,tegra186-adma";
  78                                 reg = <0x02930000 0x20000>;
  79                                 interrupt-parent = <&agic>;
  80                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  81                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  82                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  83                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  84                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  85                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  86                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  87                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  88                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  89                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  90                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  91                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  92                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  93                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  94                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  95                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  96                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  97                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  98                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  99                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 100                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 101                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 102                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 103                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 104                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 105                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 106                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 107                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 108                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 109                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 110                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 111                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 112                                 #dma-cells = <1>;
 113                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 114                                 clock-names = "d_audio";
 115                                 status = "disabled";
 116                         };
 117
 118                         agic: interrupt-controller@2a40000 {
 119                                 compatible = "nvidia,tegra194-agic",
 120                                              "nvidia,tegra210-agic";
 121                                 #interrupt-cells = <3>;
 122                                 interrupt-controller;
 123                                 reg = <0x02a41000 0x1000>,
 124                                       <0x02a42000 0x2000>;
 125                                 interrupts = <GIC_SPI 145
 126                                               (GIC_CPU_MASK_SIMPLE(4) |
 127                                                IRQ_TYPE_LEVEL_HIGH)>;
 128                                 clocks = <&bpmp TEGRA194_CLK_APE>;
 129                                 clock-names = "clk";
 130                                 status = "disabled";
 131                         };
 132                 };
 133
 134                 pinmux: pinmux@2430000 {
 135                         compatible = "nvidia,tegra194-pinmux";
 136                         reg = <0x2430000 0x17000
 137                                0xc300000 0x4000>;
 138
 139                         status = "okay";
 140
 141                         pex_rst_c5_out_state: pex_rst_c5_out {
 142                                 pex_rst {
 143                                         nvidia,pins = "pex_l5_rst_n_pgg1";
 144                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 145                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 146                                         nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 147                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 148                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 149                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 150                                 };
 151                         };
 152
 153                         clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
 154                                 clkreq {
 155                                         nvidia,pins = "pex_l5_clkreq_n_pgg0";
 156                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 157                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 158                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 159                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 160                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 161                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 162                                 };
 163                         };
 164                 };
 165
 166                 uarta: serial@3100000 {
 167                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 168                         reg = <0x03100000 0x40>;
 169                         reg-shift = <2>;
 170                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 171                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
 172                         clock-names = "serial";
 173                         resets = <&bpmp TEGRA194_RESET_UARTA>;
 174                         reset-names = "serial";
 175                         status = "disabled";
 176                 };
 177
 178                 uartb: serial@3110000 {
 179                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 180                         reg = <0x03110000 0x40>;
 181                         reg-shift = <2>;
 182                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
 184                         clock-names = "serial";
 185                         resets = <&bpmp TEGRA194_RESET_UARTB>;
 186                         reset-names = "serial";
 187                         status = "disabled";
 188                 };
 189
 190                 uartd: serial@3130000 {
 191                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 192                         reg = <0x03130000 0x40>;
 193                         reg-shift = <2>;
 194                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 195                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
 196                         clock-names = "serial";
 197                         resets = <&bpmp TEGRA194_RESET_UARTD>;
 198                         reset-names = "serial";
 199                         status = "disabled";
 200                 };
 201
 202                 uarte: serial@3140000 {
 203                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 204                         reg = <0x03140000 0x40>;
 205                         reg-shift = <2>;
 206                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 208                         clock-names = "serial";
 209                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 210                         reset-names = "serial";
 211                         status = "disabled";
 212                 };
 213
 214                 uartf: serial@3150000 {
 215                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 216                         reg = <0x03150000 0x40>;
 217                         reg-shift = <2>;
 218                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 220                         clock-names = "serial";
 221                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 222                         reset-names = "serial";
 223                         status = "disabled";
 224                 };
 225
 226                 gen1_i2c: i2c@3160000 {
 227                         compatible = "nvidia,tegra194-i2c";
 228                         reg = <0x03160000 0x10000>;
 229                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 233                         clock-names = "div-clk";
 234                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 235                         reset-names = "i2c";
 236                         status = "disabled";
 237                 };
 238
 239                 uarth: serial@3170000 {
 240                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 241                         reg = <0x03170000 0x40>;
 242                         reg-shift = <2>;
 243                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 244                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 245                         clock-names = "serial";
 246                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 247                         reset-names = "serial";
 248                         status = "disabled";
 249                 };
 250
 251                 cam_i2c: i2c@3180000 {
 252                         compatible = "nvidia,tegra194-i2c";
 253                         reg = <0x03180000 0x10000>;
 254                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 258                         clock-names = "div-clk";
 259                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 260                         reset-names = "i2c";
 261                         status = "disabled";
 262                 };
 263
 264                 /* shares pads with dpaux1 */
 265                 dp_aux_ch1_i2c: i2c@3190000 {
 266                         compatible = "nvidia,tegra194-i2c";
 267                         reg = <0x03190000 0x10000>;
 268                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 272                         clock-names = "div-clk";
 273                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 274                         reset-names = "i2c";
 275                         status = "disabled";
 276                 };
 277
 278                 /* shares pads with dpaux0 */
 279                 dp_aux_ch0_i2c: i2c@31b0000 {
 280                         compatible = "nvidia,tegra194-i2c";
 281                         reg = <0x031b0000 0x10000>;
 282                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 286                         clock-names = "div-clk";
 287                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 288                         reset-names = "i2c";
 289                         status = "disabled";
 290                 };
 291
 292                 gen7_i2c: i2c@31c0000 {
 293                         compatible = "nvidia,tegra194-i2c";
 294                         reg = <0x031c0000 0x10000>;
 295                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 299                         clock-names = "div-clk";
 300                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 301                         reset-names = "i2c";
 302                         status = "disabled";
 303                 };
 304
 305                 gen9_i2c: i2c@31e0000 {
 306                         compatible = "nvidia,tegra194-i2c";
 307                         reg = <0x031e0000 0x10000>;
 308                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 309                         #address-cells = <1>;
 310                         #size-cells = <0>;
 311                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 312                         clock-names = "div-clk";
 313                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 314                         reset-names = "i2c";
 315                         status = "disabled";
 316                 };
 317
 318                 pwm1: pwm@3280000 {
 319                         compatible = "nvidia,tegra194-pwm",
 320                                      "nvidia,tegra186-pwm";
 321                         reg = <0x3280000 0x10000>;
 322                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 323                         clock-names = "pwm";
 324                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 325                         reset-names = "pwm";
 326                         status = "disabled";
 327                         #pwm-cells = <2>;
 328                 };
 329
 330                 pwm2: pwm@3290000 {
 331                         compatible = "nvidia,tegra194-pwm",
 332                                      "nvidia,tegra186-pwm";
 333                         reg = <0x3290000 0x10000>;
 334                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 335                         clock-names = "pwm";
 336                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 337                         reset-names = "pwm";
 338                         status = "disabled";
 339                         #pwm-cells = <2>;
 340                 };
 341
 342                 pwm3: pwm@32a0000 {
 343                         compatible = "nvidia,tegra194-pwm",
 344                                      "nvidia,tegra186-pwm";
 345                         reg = <0x32a0000 0x10000>;
 346                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 347                         clock-names = "pwm";
 348                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 349                         reset-names = "pwm";
 350                         status = "disabled";
 351                         #pwm-cells = <2>;
 352                 };
 353
 354                 pwm5: pwm@32c0000 {
 355                         compatible = "nvidia,tegra194-pwm",
 356                                      "nvidia,tegra186-pwm";
 357                         reg = <0x32c0000 0x10000>;
 358                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 359                         clock-names = "pwm";
 360                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 361                         reset-names = "pwm";
 362                         status = "disabled";
 363                         #pwm-cells = <2>;
 364                 };
 365
 366                 pwm6: pwm@32d0000 {
 367                         compatible = "nvidia,tegra194-pwm",
 368                                      "nvidia,tegra186-pwm";
 369                         reg = <0x32d0000 0x10000>;
 370                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 371                         clock-names = "pwm";
 372                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 373                         reset-names = "pwm";
 374                         status = "disabled";
 375                         #pwm-cells = <2>;
 376                 };
 377
 378                 pwm7: pwm@32e0000 {
 379                         compatible = "nvidia,tegra194-pwm",
 380                                      "nvidia,tegra186-pwm";
 381                         reg = <0x32e0000 0x10000>;
 382                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 383                         clock-names = "pwm";
 384                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 385                         reset-names = "pwm";
 386                         status = "disabled";
 387                         #pwm-cells = <2>;
 388                 };
 389
 390                 pwm8: pwm@32f0000 {
 391                         compatible = "nvidia,tegra194-pwm",
 392                                      "nvidia,tegra186-pwm";
 393                         reg = <0x32f0000 0x10000>;
 394                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 395                         clock-names = "pwm";
 396                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 397                         reset-names = "pwm";
 398                         status = "disabled";
 399                         #pwm-cells = <2>;
 400                 };
 401
 402                 sdmmc1: sdhci@3400000 {
 403                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 404                         reg = <0x03400000 0x10000>;
 405                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
 407                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 408                         clock-names = "sdhci", "tmclk";
 409                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 410                         reset-names = "sdhci";
 411                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 412                                                                         <0x07>;
 413                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 414                                                                         <0x07>;
 415                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 416                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 417                                                                         <0x07>;
 418                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 419                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 420                         nvidia,default-tap = <0x9>;
 421                         nvidia,default-trim = <0x5>;
 422                         status = "disabled";
 423                 };
 424
 425                 sdmmc3: sdhci@3440000 {
 426                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 427                         reg = <0x03440000 0x10000>;
 428                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
 430                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 431                         clock-names = "sdhci", "tmclk";
 432                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 433                         reset-names = "sdhci";
 434                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 435                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 436                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 437                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 438                                                                         <0x07>;
 439                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 440                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 441                                                                         <0x07>;
 442                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 443                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 444                         nvidia,default-tap = <0x9>;
 445                         nvidia,default-trim = <0x5>;
 446                         status = "disabled";
 447                 };
 448
 449                 sdmmc4: sdhci@3460000 {
 450                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 451                         reg = <0x03460000 0x10000>;
 452                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 454                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 455                         clock-names = "sdhci", "tmclk";
 456                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 457                                           <&bpmp TEGRA194_CLK_PLLC4>;
 458                         assigned-clock-parents =
 459                                           <&bpmp TEGRA194_CLK_PLLC4>;
 460                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 461                         reset-names = "sdhci";
 462                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 463                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 464                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 465                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 466                                                                         <0x0a>;
 467                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 468                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 469                                                                         <0x0a>;
 470                         nvidia,default-tap = <0x8>;
 471                         nvidia,default-trim = <0x14>;
 472                         nvidia,dqs-trim = <40>;
 473                         supports-cqe;
 474                         status = "disabled";
 475                 };
 476
 477                 hda@3510000 {
 478                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 479                         reg = <0x3510000 0x10000>;
 480                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 481                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 482                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
 483                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
 484                         clock-names = "hda", "hda2codec_2x", "hda2hdmi";
 485                         resets = <&bpmp TEGRA194_RESET_HDA>,
 486                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
 487                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
 488                         reset-names = "hda", "hda2codec_2x", "hda2hdmi";
 489                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 490                         status = "disabled";
 491                 };
 492
 493                 gic: interrupt-controller@3881000 {
 494                         compatible = "arm,gic-400";
 495                         #interrupt-cells = <3>;
 496                         interrupt-controller;
 497                         reg = <0x03881000 0x1000>,
 498                               <0x03882000 0x2000>,
 499                               <0x03884000 0x2000>,
 500                               <0x03886000 0x2000>;
 501                         interrupts = <GIC_PPI 9
 502                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 503                         interrupt-parent = <&gic>;
 504                 };
 505
 506                 cec@3960000 {
 507                         compatible = "nvidia,tegra194-cec";
 508                         reg = <0x03960000 0x10000>;
 509                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&bpmp TEGRA194_CLK_CEC>;
 511                         clock-names = "cec";
 512                         status = "disabled";
 513                 };
 514
 515                 hsp_top0: hsp@3c00000 {
 516                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 517                         reg = <0x03c00000 0xa0000>;
 518                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 520                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 521                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 522                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 523                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 524                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 525                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 526                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 527                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
 528                                           "shared3", "shared4", "shared5", "shared6",
 529                                           "shared7";
 530                         #mbox-cells = <2>;
 531                 };
 532
 533                 p2u_hsio_0: phy@3e10000 {
 534                         compatible = "nvidia,tegra194-p2u";
 535                         reg = <0x03e10000 0x10000>;
 536                         reg-names = "ctl";
 537
 538                         #phy-cells = <0>;
 539                 };
 540
 541                 p2u_hsio_1: phy@3e20000 {
 542                         compatible = "nvidia,tegra194-p2u";
 543                         reg = <0x03e20000 0x10000>;
 544                         reg-names = "ctl";
 545
 546                         #phy-cells = <0>;
 547                 };
 548
 549                 p2u_hsio_2: phy@3e30000 {
 550                         compatible = "nvidia,tegra194-p2u";
 551                         reg = <0x03e30000 0x10000>;
 552                         reg-names = "ctl";
 553
 554                         #phy-cells = <0>;
 555                 };
 556
 557                 p2u_hsio_3: phy@3e40000 {
 558                         compatible = "nvidia,tegra194-p2u";
 559                         reg = <0x03e40000 0x10000>;
 560                         reg-names = "ctl";
 561
 562                         #phy-cells = <0>;
 563                 };
 564
 565                 p2u_hsio_4: phy@3e50000 {
 566                         compatible = "nvidia,tegra194-p2u";
 567                         reg = <0x03e50000 0x10000>;
 568                         reg-names = "ctl";
 569
 570                         #phy-cells = <0>;
 571                 };
 572
 573                 p2u_hsio_5: phy@3e60000 {
 574                         compatible = "nvidia,tegra194-p2u";
 575                         reg = <0x03e60000 0x10000>;
 576                         reg-names = "ctl";
 577
 578                         #phy-cells = <0>;
 579                 };
 580
 581                 p2u_hsio_6: phy@3e70000 {
 582                         compatible = "nvidia,tegra194-p2u";
 583                         reg = <0x03e70000 0x10000>;
 584                         reg-names = "ctl";
 585
 586                         #phy-cells = <0>;
 587                 };
 588
 589                 p2u_hsio_7: phy@3e80000 {
 590                         compatible = "nvidia,tegra194-p2u";
 591                         reg = <0x03e80000 0x10000>;
 592                         reg-names = "ctl";
 593
 594                         #phy-cells = <0>;
 595                 };
 596
 597                 p2u_hsio_8: phy@3e90000 {
 598                         compatible = "nvidia,tegra194-p2u";
 599                         reg = <0x03e90000 0x10000>;
 600                         reg-names = "ctl";
 601
 602                         #phy-cells = <0>;
 603                 };
 604
 605                 p2u_hsio_9: phy@3ea0000 {
 606                         compatible = "nvidia,tegra194-p2u";
 607                         reg = <0x03ea0000 0x10000>;
 608                         reg-names = "ctl";
 609
 610                         #phy-cells = <0>;
 611                 };
 612
 613                 p2u_nvhs_0: phy@3eb0000 {
 614                         compatible = "nvidia,tegra194-p2u";
 615                         reg = <0x03eb0000 0x10000>;
 616                         reg-names = "ctl";
 617
 618                         #phy-cells = <0>;
 619                 };
 620
 621                 p2u_nvhs_1: phy@3ec0000 {
 622                         compatible = "nvidia,tegra194-p2u";
 623                         reg = <0x03ec0000 0x10000>;
 624                         reg-names = "ctl";
 625
 626                         #phy-cells = <0>;
 627                 };
 628
 629                 p2u_nvhs_2: phy@3ed0000 {
 630                         compatible = "nvidia,tegra194-p2u";
 631                         reg = <0x03ed0000 0x10000>;
 632                         reg-names = "ctl";
 633
 634                         #phy-cells = <0>;
 635                 };
 636
 637                 p2u_nvhs_3: phy@3ee0000 {
 638                         compatible = "nvidia,tegra194-p2u";
 639                         reg = <0x03ee0000 0x10000>;
 640                         reg-names = "ctl";
 641
 642                         #phy-cells = <0>;
 643                 };
 644
 645                 p2u_nvhs_4: phy@3ef0000 {
 646                         compatible = "nvidia,tegra194-p2u";
 647                         reg = <0x03ef0000 0x10000>;
 648                         reg-names = "ctl";
 649
 650                         #phy-cells = <0>;
 651                 };
 652
 653                 p2u_nvhs_5: phy@3f00000 {
 654                         compatible = "nvidia,tegra194-p2u";
 655                         reg = <0x03f00000 0x10000>;
 656                         reg-names = "ctl";
 657
 658                         #phy-cells = <0>;
 659                 };
 660
 661                 p2u_nvhs_6: phy@3f10000 {
 662                         compatible = "nvidia,tegra194-p2u";
 663                         reg = <0x03f10000 0x10000>;
 664                         reg-names = "ctl";
 665
 666                         #phy-cells = <0>;
 667                 };
 668
 669                 p2u_nvhs_7: phy@3f20000 {
 670                         compatible = "nvidia,tegra194-p2u";
 671                         reg = <0x03f20000 0x10000>;
 672                         reg-names = "ctl";
 673
 674                         #phy-cells = <0>;
 675                 };
 676
 677                 p2u_hsio_10: phy@3f30000 {
 678                         compatible = "nvidia,tegra194-p2u";
 679                         reg = <0x03f30000 0x10000>;
 680                         reg-names = "ctl";
 681
 682                         #phy-cells = <0>;
 683                 };
 684
 685                 p2u_hsio_11: phy@3f40000 {
 686                         compatible = "nvidia,tegra194-p2u";
 687                         reg = <0x03f40000 0x10000>;
 688                         reg-names = "ctl";
 689
 690                         #phy-cells = <0>;
 691                 };
 692
 693                 hsp_aon: hsp@c150000 {
 694                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 695                         reg = <0x0c150000 0x90000>;
 696                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 698                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 699                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 700                         /*
 701                          * Shared interrupt 0 is routed only to AON/SPE, so
 702                          * we only have 4 shared interrupts for the CCPLEX.
 703                          */
 704                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
 705                         #mbox-cells = <2>;
 706                 };
 707
 708                 gen2_i2c: i2c@c240000 {
 709                         compatible = "nvidia,tegra194-i2c";
 710                         reg = <0x0c240000 0x10000>;
 711                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 712                         #address-cells = <1>;
 713                         #size-cells = <0>;
 714                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
 715                         clock-names = "div-clk";
 716                         resets = <&bpmp TEGRA194_RESET_I2C2>;
 717                         reset-names = "i2c";
 718                         status = "disabled";
 719                 };
 720
 721                 gen8_i2c: i2c@c250000 {
 722                         compatible = "nvidia,tegra194-i2c";
 723                         reg = <0x0c250000 0x10000>;
 724                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 725                         #address-cells = <1>;
 726                         #size-cells = <0>;
 727                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
 728                         clock-names = "div-clk";
 729                         resets = <&bpmp TEGRA194_RESET_I2C8>;
 730                         reset-names = "i2c";
 731                         status = "disabled";
 732                 };
 733
 734                 uartc: serial@c280000 {
 735                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 736                         reg = <0x0c280000 0x40>;
 737                         reg-shift = <2>;
 738                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 739                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
 740                         clock-names = "serial";
 741                         resets = <&bpmp TEGRA194_RESET_UARTC>;
 742                         reset-names = "serial";
 743                         status = "disabled";
 744                 };
 745
 746                 uartg: serial@c290000 {
 747                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 748                         reg = <0x0c290000 0x40>;
 749                         reg-shift = <2>;
 750                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 751                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
 752                         clock-names = "serial";
 753                         resets = <&bpmp TEGRA194_RESET_UARTG>;
 754                         reset-names = "serial";
 755                         status = "disabled";
 756                 };
 757
 758                 rtc: rtc@c2a0000 {
 759                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
 760                         reg = <0x0c2a0000 0x10000>;
 761                         interrupt-parent = <&pmc>;
 762                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 763                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
 764                         clock-names = "rtc";
 765                         status = "disabled";
 766                 };
 767
 768                 gpio_aon: gpio@c2f0000 {
 769                         compatible = "nvidia,tegra194-gpio-aon";
 770                         reg-names = "security", "gpio";
 771                         reg = <0xc2f0000 0x1000>,
 772                               <0xc2f1000 0x1000>;
 773                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 774                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 775                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 777                         gpio-controller;
 778                         #gpio-cells = <2>;
 779                         interrupt-controller;
 780                         #interrupt-cells = <2>;
 781                 };
 782
 783                 pwm4: pwm@c340000 {
 784                         compatible = "nvidia,tegra194-pwm",
 785                                      "nvidia,tegra186-pwm";
 786                         reg = <0xc340000 0x10000>;
 787                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
 788                         clock-names = "pwm";
 789                         resets = <&bpmp TEGRA194_RESET_PWM4>;
 790                         reset-names = "pwm";
 791                         status = "disabled";
 792                         #pwm-cells = <2>;
 793                 };
 794
 795                 pmc: pmc@c360000 {
 796                         compatible = "nvidia,tegra194-pmc";
 797                         reg = <0x0c360000 0x10000>,
 798                               <0x0c370000 0x10000>,
 799                               <0x0c380000 0x10000>,
 800                               <0x0c390000 0x10000>,
 801                               <0x0c3a0000 0x10000>;
 802                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
 803
 804                         #interrupt-cells = <2>;
 805                         interrupt-controller;
 806                 };
 807
 808                 host1x@13e00000 {
 809                         compatible = "nvidia,tegra194-host1x", "simple-bus";
 810                         reg = <0x13e00000 0x10000>,
 811                               <0x13e10000 0x10000>;
 812                         reg-names = "hypervisor", "vm";
 813                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 814                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 815                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
 816                         clock-names = "host1x";
 817                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
 818                         reset-names = "host1x";
 819
 820                         #address-cells = <1>;
 821                         #size-cells = <1>;
 822
 823                         ranges = <0x15000000 0x15000000 0x01000000>;
 824
 825                         display-hub@15200000 {
 826                                 compatible = "nvidia,tegra194-display", "simple-bus";
 827                                 reg = <0x15200000 0x00040000>;
 828                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
 829                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
 830                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
 831                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
 832                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
 833                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
 834                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
 835                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 836                                               "wgrp3", "wgrp4", "wgrp5";
 837                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
 838                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
 839                                 clock-names = "disp", "hub";
 840                                 status = "disabled";
 841
 842                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 843
 844                                 #address-cells = <1>;
 845                                 #size-cells = <1>;
 846
 847                                 ranges = <0x15200000 0x15200000 0x40000>;
 848
 849                                 display@15200000 {
 850                                         compatible = "nvidia,tegra194-dc";
 851                                         reg = <0x15200000 0x10000>;
 852                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 853                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
 854                                         clock-names = "dc";
 855                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
 856                                         reset-names = "dc";
 857
 858                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 859
 860                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 861                                         nvidia,head = <0>;
 862                                 };
 863
 864                                 display@15210000 {
 865                                         compatible = "nvidia,tegra194-dc";
 866                                         reg = <0x15210000 0x10000>;
 867                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 868                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
 869                                         clock-names = "dc";
 870                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
 871                                         reset-names = "dc";
 872
 873                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
 874
 875                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 876                                         nvidia,head = <1>;
 877                                 };
 878
 879                                 display@15220000 {
 880                                         compatible = "nvidia,tegra194-dc";
 881                                         reg = <0x15220000 0x10000>;
 882                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 883                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
 884                                         clock-names = "dc";
 885                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
 886                                         reset-names = "dc";
 887
 888                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 889
 890                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 891                                         nvidia,head = <2>;
 892                                 };
 893
 894                                 display@15230000 {
 895                                         compatible = "nvidia,tegra194-dc";
 896                                         reg = <0x15230000 0x10000>;
 897                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 898                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
 899                                         clock-names = "dc";
 900                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
 901                                         reset-names = "dc";
 902
 903                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 904
 905                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 906                                         nvidia,head = <3>;
 907                                 };
 908                         };
 909
 910                         vic@15340000 {
 911                                 compatible = "nvidia,tegra194-vic";
 912                                 reg = <0x15340000 0x00040000>;
 913                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 914                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
 915                                 clock-names = "vic";
 916                                 resets = <&bpmp TEGRA194_RESET_VIC>;
 917                                 reset-names = "vic";
 918
 919                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
 920                         };
 921
 922                         dpaux0: dpaux@155c0000 {
 923                                 compatible = "nvidia,tegra194-dpaux";
 924                                 reg = <0x155c0000 0x10000>;
 925                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 926                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
 927                                          <&bpmp TEGRA194_CLK_PLLDP>;
 928                                 clock-names = "dpaux", "parent";
 929                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
 930                                 reset-names = "dpaux";
 931                                 status = "disabled";
 932
 933                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 934
 935                                 state_dpaux0_aux: pinmux-aux {
 936                                         groups = "dpaux-io";
 937                                         function = "aux";
 938                                 };
 939
 940                                 state_dpaux0_i2c: pinmux-i2c {
 941                                         groups = "dpaux-io";
 942                                         function = "i2c";
 943                                 };
 944
 945                                 state_dpaux0_off: pinmux-off {
 946                                         groups = "dpaux-io";
 947                                         function = "off";
 948                                 };
 949
 950                                 i2c-bus {
 951                                         #address-cells = <1>;
 952                                         #size-cells = <0>;
 953                                 };
 954                         };
 955
 956                         dpaux1: dpaux@155d0000 {
 957                                 compatible = "nvidia,tegra194-dpaux";
 958                                 reg = <0x155d0000 0x10000>;
 959                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 960                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
 961                                          <&bpmp TEGRA194_CLK_PLLDP>;
 962                                 clock-names = "dpaux", "parent";
 963                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
 964                                 reset-names = "dpaux";
 965                                 status = "disabled";
 966
 967                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 968
 969                                 state_dpaux1_aux: pinmux-aux {
 970                                         groups = "dpaux-io";
 971                                         function = "aux";
 972                                 };
 973
 974                                 state_dpaux1_i2c: pinmux-i2c {
 975                                         groups = "dpaux-io";
 976                                         function = "i2c";
 977                                 };
 978
 979                                 state_dpaux1_off: pinmux-off {
 980                                         groups = "dpaux-io";
 981                                         function = "off";
 982                                 };
 983
 984                                 i2c-bus {
 985                                         #address-cells = <1>;
 986                                         #size-cells = <0>;
 987                                 };
 988                         };
 989
 990                         dpaux2: dpaux@155e0000 {
 991                                 compatible = "nvidia,tegra194-dpaux";
 992                                 reg = <0x155e0000 0x10000>;
 993                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
 994                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
 995                                          <&bpmp TEGRA194_CLK_PLLDP>;
 996                                 clock-names = "dpaux", "parent";
 997                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
 998                                 reset-names = "dpaux";
 999                                 status = "disabled";
1000
1001                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1002
1003                                 state_dpaux2_aux: pinmux-aux {
1004                                         groups = "dpaux-io";
1005                                         function = "aux";
1006                                 };
1007
1008                                 state_dpaux2_i2c: pinmux-i2c {
1009                                         groups = "dpaux-io";
1010                                         function = "i2c";
1011                                 };
1012
1013                                 state_dpaux2_off: pinmux-off {
1014                                         groups = "dpaux-io";
1015                                         function = "off";
1016                                 };
1017
1018                                 i2c-bus {
1019                                         #address-cells = <1>;
1020                                         #size-cells = <0>;
1021                                 };
1022                         };
1023
1024                         dpaux3: dpaux@155f0000 {
1025                                 compatible = "nvidia,tegra194-dpaux";
1026                                 reg = <0x155f0000 0x10000>;
1027                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1028                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1029                                          <&bpmp TEGRA194_CLK_PLLDP>;
1030                                 clock-names = "dpaux", "parent";
1031                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1032                                 reset-names = "dpaux";
1033                                 status = "disabled";
1034
1035                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1036
1037                                 state_dpaux3_aux: pinmux-aux {
1038                                         groups = "dpaux-io";
1039                                         function = "aux";
1040                                 };
1041
1042                                 state_dpaux3_i2c: pinmux-i2c {
1043                                         groups = "dpaux-io";
1044                                         function = "i2c";
1045                                 };
1046
1047                                 state_dpaux3_off: pinmux-off {
1048                                         groups = "dpaux-io";
1049                                         function = "off";
1050                                 };
1051
1052                                 i2c-bus {
1053                                         #address-cells = <1>;
1054                                         #size-cells = <0>;
1055                                 };
1056                         };
1057
1058                         sor0: sor@15b00000 {
1059                                 compatible = "nvidia,tegra194-sor";
1060                                 reg = <0x15b00000 0x40000>;
1061                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1062                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1063                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
1064                                          <&bpmp TEGRA194_CLK_PLLD>,
1065                                          <&bpmp TEGRA194_CLK_PLLDP>,
1066                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1067                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1068                                 clock-names = "sor", "out", "parent", "dp", "safe",
1069                                               "pad";
1070                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
1071                                 reset-names = "sor";
1072                                 pinctrl-0 = <&state_dpaux0_aux>;
1073                                 pinctrl-1 = <&state_dpaux0_i2c>;
1074                                 pinctrl-2 = <&state_dpaux0_off>;
1075                                 pinctrl-names = "aux", "i2c", "off";
1076                                 status = "disabled";
1077
1078                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1079                                 nvidia,interface = <0>;
1080                         };
1081
1082                         sor1: sor@15b40000 {
1083                                 compatible = "nvidia,tegra194-sor";
1084                                 reg = <0x155c0000 0x40000>;
1085                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1086                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1087                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
1088                                          <&bpmp TEGRA194_CLK_PLLD2>,
1089                                          <&bpmp TEGRA194_CLK_PLLDP>,
1090                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1091                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1092                                 clock-names = "sor", "out", "parent", "dp", "safe",
1093                                               "pad";
1094                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
1095                                 reset-names = "sor";
1096                                 pinctrl-0 = <&state_dpaux1_aux>;
1097                                 pinctrl-1 = <&state_dpaux1_i2c>;
1098                                 pinctrl-2 = <&state_dpaux1_off>;
1099                                 pinctrl-names = "aux", "i2c", "off";
1100                                 status = "disabled";
1101
1102                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1103                                 nvidia,interface = <1>;
1104                         };
1105
1106                         sor2: sor@15b80000 {
1107                                 compatible = "nvidia,tegra194-sor";
1108                                 reg = <0x15b80000 0x40000>;
1109                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1110                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1111                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
1112                                          <&bpmp TEGRA194_CLK_PLLD3>,
1113                                          <&bpmp TEGRA194_CLK_PLLDP>,
1114                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1115                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1116                                 clock-names = "sor", "out", "parent", "dp", "safe",
1117                                               "pad";
1118                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
1119                                 reset-names = "sor";
1120                                 pinctrl-0 = <&state_dpaux2_aux>;
1121                                 pinctrl-1 = <&state_dpaux2_i2c>;
1122                                 pinctrl-2 = <&state_dpaux2_off>;
1123                                 pinctrl-names = "aux", "i2c", "off";
1124                                 status = "disabled";
1125
1126                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1127                                 nvidia,interface = <2>;
1128                         };
1129
1130                         sor3: sor@15bc0000 {
1131                                 compatible = "nvidia,tegra194-sor";
1132                                 reg = <0x15bc0000 0x40000>;
1133                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1134                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1135                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
1136                                          <&bpmp TEGRA194_CLK_PLLD4>,
1137                                          <&bpmp TEGRA194_CLK_PLLDP>,
1138                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1139                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1140                                 clock-names = "sor", "out", "parent", "dp", "safe",
1141                                               "pad";
1142                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
1143                                 reset-names = "sor";
1144                                 pinctrl-0 = <&state_dpaux3_aux>;
1145                                 pinctrl-1 = <&state_dpaux3_i2c>;
1146                                 pinctrl-2 = <&state_dpaux3_off>;
1147                                 pinctrl-names = "aux", "i2c", "off";
1148                                 status = "disabled";
1149
1150                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1151                                 nvidia,interface = <3>;
1152                         };
1153                 };
1154         };
1155
1156         pcie@14100000 {
1157                 compatible = "nvidia,tegra194-pcie";
1158                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1159                 reg = <0x00 0x14100000 0x0 0x00020000   /* appl registers (128K)      */
1160                        0x00 0x30000000 0x0 0x00040000   /* configuration space (256K) */
1161                        0x00 0x30040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1162                        0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1163                 reg-names = "appl", "config", "atu_dma", "dbi";
1164
1165                 status = "disabled";
1166
1167                 #address-cells = <3>;
1168                 #size-cells = <2>;
1169                 device_type = "pci";
1170                 num-lanes = <1>;
1171                 num-viewport = <8>;
1172                 linux,pci-domain = <1>;
1173
1174                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1175                 clock-names = "core";
1176
1177                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1178                          <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1179                 reset-names = "apb", "core";
1180
1181                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1182                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1183                 interrupt-names = "intr", "msi";
1184
1185                 #interrupt-cells = <1>;
1186                 interrupt-map-mask = <0 0 0 0>;
1187                 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1188
1189                 nvidia,bpmp = <&bpmp 1>;
1190
1191                 supports-clkreq;
1192                 nvidia,aspm-cmrt-us = <60>;
1193                 nvidia,aspm-pwr-on-t-us = <20>;
1194                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1195
1196                 bus-range = <0x0 0xff>;
1197                 ranges = <0x81000000 0x0  0x30100000 0x0  0x30100000 0x0 0x00100000   /* downstream I/O (1MB) */
1198                           0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1199                           0x82000000 0x0  0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1200         };
1201
1202         pcie@14120000 {
1203                 compatible = "nvidia,tegra194-pcie";
1204                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1205                 reg = <0x00 0x14120000 0x0 0x00020000   /* appl registers (128K)      */
1206                        0x00 0x32000000 0x0 0x00040000   /* configuration space (256K) */
1207                        0x00 0x32040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1208                        0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1209                 reg-names = "appl", "config", "atu_dma", "dbi";
1210
1211                 status = "disabled";
1212
1213                 #address-cells = <3>;
1214                 #size-cells = <2>;
1215                 device_type = "pci";
1216                 num-lanes = <1>;
1217                 num-viewport = <8>;
1218                 linux,pci-domain = <2>;
1219
1220                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1221                 clock-names = "core";
1222
1223                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1224                          <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1225                 reset-names = "apb", "core";
1226
1227                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1228                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1229                 interrupt-names = "intr", "msi";
1230
1231                 #interrupt-cells = <1>;
1232                 interrupt-map-mask = <0 0 0 0>;
1233                 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1234
1235                 nvidia,bpmp = <&bpmp 2>;
1236
1237                 supports-clkreq;
1238                 nvidia,aspm-cmrt-us = <60>;
1239                 nvidia,aspm-pwr-on-t-us = <20>;
1240                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1241
1242                 bus-range = <0x0 0xff>;
1243                 ranges = <0x81000000 0x0  0x32100000 0x0  0x32100000 0x0 0x00100000   /* downstream I/O (1MB) */
1244                           0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1245                           0x82000000 0x0  0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1246         };
1247
1248         pcie@14140000 {
1249                 compatible = "nvidia,tegra194-pcie";
1250                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1251                 reg = <0x00 0x14140000 0x0 0x00020000   /* appl registers (128K)      */
1252                        0x00 0x34000000 0x0 0x00040000   /* configuration space (256K) */
1253                        0x00 0x34040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1254                        0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1255                 reg-names = "appl", "config", "atu_dma", "dbi";
1256
1257                 status = "disabled";
1258
1259                 #address-cells = <3>;
1260                 #size-cells = <2>;
1261                 device_type = "pci";
1262                 num-lanes = <1>;
1263                 num-viewport = <8>;
1264                 linux,pci-domain = <3>;
1265
1266                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1267                 clock-names = "core";
1268
1269                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1270                          <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1271                 reset-names = "apb", "core";
1272
1273                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1274                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1275                 interrupt-names = "intr", "msi";
1276
1277                 #interrupt-cells = <1>;
1278                 interrupt-map-mask = <0 0 0 0>;
1279                 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1280
1281                 nvidia,bpmp = <&bpmp 3>;
1282
1283                 supports-clkreq;
1284                 nvidia,aspm-cmrt-us = <60>;
1285                 nvidia,aspm-pwr-on-t-us = <20>;
1286                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1287
1288                 bus-range = <0x0 0xff>;
1289                 ranges = <0x81000000 0x0  0x34100000 0x0  0x34100000 0x0 0x00100000   /* downstream I/O (1MB) */
1290                           0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1291                           0x82000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1292         };
1293
1294         pcie@14160000 {
1295                 compatible = "nvidia,tegra194-pcie";
1296                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1297                 reg = <0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */
1298                        0x00 0x36000000 0x0 0x00040000   /* configuration space (256K) */
1299                        0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1300                        0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1301                 reg-names = "appl", "config", "atu_dma", "dbi";
1302
1303                 status = "disabled";
1304
1305                 #address-cells = <3>;
1306                 #size-cells = <2>;
1307                 device_type = "pci";
1308                 num-lanes = <4>;
1309                 num-viewport = <8>;
1310                 linux,pci-domain = <4>;
1311
1312                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1313                 clock-names = "core";
1314
1315                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1316                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1317                 reset-names = "apb", "core";
1318
1319                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1320                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1321                 interrupt-names = "intr", "msi";
1322
1323                 #interrupt-cells = <1>;
1324                 interrupt-map-mask = <0 0 0 0>;
1325                 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1326
1327                 nvidia,bpmp = <&bpmp 4>;
1328
1329                 supports-clkreq;
1330                 nvidia,aspm-cmrt-us = <60>;
1331                 nvidia,aspm-pwr-on-t-us = <20>;
1332                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1333
1334                 bus-range = <0x0 0xff>;
1335                 ranges = <0x81000000 0x0  0x36100000 0x0  0x36100000 0x0 0x00100000   /* downstream I/O (1MB) */
1336                           0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1337                           0x82000000 0x0  0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1338         };
1339
1340         pcie@14180000 {
1341                 compatible = "nvidia,tegra194-pcie";
1342                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1343                 reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
1344                        0x00 0x38000000 0x0 0x00040000   /* configuration space (256K) */
1345                        0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1346                        0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1347                 reg-names = "appl", "config", "atu_dma", "dbi";
1348
1349                 status = "disabled";
1350
1351                 #address-cells = <3>;
1352                 #size-cells = <2>;
1353                 device_type = "pci";
1354                 num-lanes = <8>;
1355                 num-viewport = <8>;
1356                 linux,pci-domain = <0>;
1357
1358                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1359                 clock-names = "core";
1360
1361                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1362                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1363                 reset-names = "apb", "core";
1364
1365                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1366                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1367                 interrupt-names = "intr", "msi";
1368
1369                 #interrupt-cells = <1>;
1370                 interrupt-map-mask = <0 0 0 0>;
1371                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1372
1373                 nvidia,bpmp = <&bpmp 0>;
1374
1375                 supports-clkreq;
1376                 nvidia,aspm-cmrt-us = <60>;
1377                 nvidia,aspm-pwr-on-t-us = <20>;
1378                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1379
1380                 bus-range = <0x0 0xff>;
1381                 ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000   /* downstream I/O (1MB) */
1382                           0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1383                           0x82000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1384         };
1385
1386         pcie@141a0000 {
1387                 compatible = "nvidia,tegra194-pcie";
1388                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1389                 reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
1390                        0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
1391                        0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1392                        0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1393                 reg-names = "appl", "config", "atu_dma", "dbi";
1394
1395                 status = "disabled";
1396
1397                 #address-cells = <3>;
1398                 #size-cells = <2>;
1399                 device_type = "pci";
1400                 num-lanes = <8>;
1401                 num-viewport = <8>;
1402                 linux,pci-domain = <5>;
1403
1404                 pinctrl-names = "default";
1405                 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1406
1407                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1408                         <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1409                 clock-names = "core", "core_m";
1410
1411                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1412                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1413                 reset-names = "apb", "core";
1414
1415                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1416                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1417                 interrupt-names = "intr", "msi";
1418
1419                 nvidia,bpmp = <&bpmp 5>;
1420
1421                 #interrupt-cells = <1>;
1422                 interrupt-map-mask = <0 0 0 0>;
1423                 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1424
1425                 supports-clkreq;
1426                 nvidia,aspm-cmrt-us = <60>;
1427                 nvidia,aspm-pwr-on-t-us = <20>;
1428                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1429
1430                 bus-range = <0x0 0xff>;
1431                 ranges = <0x81000000 0x0  0x3a100000 0x0  0x3a100000 0x0 0x00100000   /* downstream I/O (1MB) */
1432                           0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1433                           0x82000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1434         };
1435
1436         pcie_ep@14160000 {
1437                 compatible = "nvidia,tegra194-pcie-ep";
1438                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1439                 reg = <0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */
1440                        0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1441                        0x00 0x36080000 0x0 0x00040000   /* DBI reg space (256K)       */
1442                        0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1443                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1444
1445                 status = "disabled";
1446
1447                 num-lanes = <4>;
1448                 num-ib-windows = <2>;
1449                 num-ob-windows = <8>;
1450
1451                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1452                 clock-names = "core";
1453
1454                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1455                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1456                 reset-names = "apb", "core";
1457
1458                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
1459                 interrupt-names = "intr";
1460
1461                 nvidia,bpmp = <&bpmp 4>;
1462
1463                 nvidia,aspm-cmrt-us = <60>;
1464                 nvidia,aspm-pwr-on-t-us = <20>;
1465                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1466         };
1467
1468         pcie_ep@14180000 {
1469                 compatible = "nvidia,tegra194-pcie-ep";
1470                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1471                 reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
1472                        0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1473                        0x00 0x38080000 0x0 0x00040000   /* DBI reg space (256K)       */
1474                        0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1475                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1476
1477                 status = "disabled";
1478
1479                 num-lanes = <8>;
1480                 num-ib-windows = <2>;
1481                 num-ob-windows = <8>;
1482
1483                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1484                 clock-names = "core";
1485
1486                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1487                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1488                 reset-names = "apb", "core";
1489
1490                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
1491                 interrupt-names = "intr";
1492
1493                 nvidia,bpmp = <&bpmp 0>;
1494
1495                 nvidia,aspm-cmrt-us = <60>;
1496                 nvidia,aspm-pwr-on-t-us = <20>;
1497                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1498         };
1499
1500         pcie_ep@141a0000 {
1501                 compatible = "nvidia,tegra194-pcie-ep";
1502                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1503                 reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
1504                        0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1505                        0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
1506                        0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1507                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1508
1509                 status = "disabled";
1510
1511                 num-lanes = <8>;
1512                 num-ib-windows = <2>;
1513                 num-ob-windows = <8>;
1514
1515                 pinctrl-names = "default";
1516                 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
1517
1518                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
1519                 clock-names = "core";
1520
1521                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1522                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1523                 reset-names = "apb", "core";
1524
1525                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
1526                 interrupt-names = "intr";
1527
1528                 nvidia,bpmp = <&bpmp 5>;
1529
1530                 nvidia,aspm-cmrt-us = <60>;
1531                 nvidia,aspm-pwr-on-t-us = <20>;
1532                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1533         };
1534
1535         sysram@40000000 {
1536                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
1537                 reg = <0x0 0x40000000 0x0 0x50000>;
1538                 #address-cells = <1>;
1539                 #size-cells = <1>;
1540                 ranges = <0x0 0x0 0x40000000 0x50000>;
1541
1542                 cpu_bpmp_tx: shmem@4e000 {
1543                         compatible = "nvidia,tegra194-bpmp-shmem";
1544                         reg = <0x4e000 0x1000>;
1545                         label = "cpu-bpmp-tx";
1546                         pool;
1547                 };
1548
1549                 cpu_bpmp_rx: shmem@4f000 {
1550                         compatible = "nvidia,tegra194-bpmp-shmem";
1551                         reg = <0x4f000 0x1000>;
1552                         label = "cpu-bpmp-rx";
1553                         pool;
1554                 };
1555         };
1556
1557         bpmp: bpmp {
1558                 compatible = "nvidia,tegra186-bpmp";
1559                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1560                                     TEGRA_HSP_DB_MASTER_BPMP>;
1561                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1562                 #clock-cells = <1>;
1563                 #reset-cells = <1>;
1564                 #power-domain-cells = <1>;
1565
1566                 bpmp_i2c: i2c {
1567                         compatible = "nvidia,tegra186-bpmp-i2c";
1568                         nvidia,bpmp-bus-id = <5>;
1569                         #address-cells = <1>;
1570                         #size-cells = <0>;
1571                 };
1572
1573                 bpmp_thermal: thermal {
1574                         compatible = "nvidia,tegra186-bpmp-thermal";
1575                         #thermal-sensor-cells = <1>;
1576                 };
1577         };
1578
1579         cpus {
1580                 #address-cells = <1>;
1581                 #size-cells = <0>;
1582
1583                 cpu@0 {
1584                         compatible = "nvidia,tegra194-carmel";
1585                         device_type = "cpu";
1586                         reg = <0x10000>;
1587                         enable-method = "psci";
1588                 };
1589
1590                 cpu@1 {
1591                         compatible = "nvidia,tegra194-carmel";
1592                         device_type = "cpu";
1593                         reg = <0x10001>;
1594                         enable-method = "psci";
1595                 };
1596
1597                 cpu@2 {
1598                         compatible = "nvidia,tegra194-carmel";
1599                         device_type = "cpu";
1600                         reg = <0x100>;
1601                         enable-method = "psci";
1602                 };
1603
1604                 cpu@3 {
1605                         compatible = "nvidia,tegra194-carmel";
1606                         device_type = "cpu";
1607                         reg = <0x101>;
1608                         enable-method = "psci";
1609                 };
1610
1611                 cpu@4 {
1612                         compatible = "nvidia,tegra194-carmel";
1613                         device_type = "cpu";
1614                         reg = <0x200>;
1615                         enable-method = "psci";
1616                 };
1617
1618                 cpu@5 {
1619                         compatible = "nvidia,tegra194-carmel";
1620                         device_type = "cpu";
1621                         reg = <0x201>;
1622                         enable-method = "psci";
1623                 };
1624
1625                 cpu@6 {
1626                         compatible = "nvidia,tegra194-carmel";
1627                         device_type = "cpu";
1628                         reg = <0x10300>;
1629                         enable-method = "psci";
1630                 };
1631
1632                 cpu@7 {
1633                         compatible = "nvidia,tegra194-carmel";
1634                         device_type = "cpu";
1635                         reg = <0x10301>;
1636                         enable-method = "psci";
1637                 };
1638         };
1639
1640         psci {
1641                 compatible = "arm,psci-1.0";
1642                 status = "okay";
1643                 method = "smc";
1644         };
1645
1646         tcu: tcu {
1647                 compatible = "nvidia,tegra194-tcu";
1648                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
1649                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
1650                 mbox-names = "rx", "tx";
1651         };
1652
1653         thermal-zones {
1654                 cpu {
1655                         thermal-sensors = <&{/bpmp/thermal}
1656                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
1657                         status = "disabled";
1658                 };
1659
1660                 gpu {
1661                         thermal-sensors = <&{/bpmp/thermal}
1662                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
1663                         status = "disabled";
1664                 };
1665
1666                 aux {
1667                         thermal-sensors = <&{/bpmp/thermal}
1668                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
1669                         status = "disabled";
1670                 };
1671
1672                 pllx {
1673                         thermal-sensors = <&{/bpmp/thermal}
1674                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
1675                         status = "disabled";
1676                 };
1677
1678                 ao {
1679                         thermal-sensors = <&{/bpmp/thermal}
1680                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
1681                         status = "disabled";
1682                 };
1683
1684                 tj {
1685                         thermal-sensors = <&{/bpmp/thermal}
1686                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
1687                         status = "disabled";
1688                 };
1689         };
1690
1691         timer {
1692                 compatible = "arm,armv8-timer";
1693                 interrupts = <GIC_PPI 13
1694                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1695                              <GIC_PPI 14
1696                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1697                              <GIC_PPI 11
1698                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1699                              <GIC_PPI 10
1700                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1701                 interrupt-parent = <&gic>;
1702                 always-on;
1703         };
1704 };