arch/arm64/boot/dts/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   8 #include <dt-bindings/power/tegra194-powergate.h>
   9 #include <dt-bindings/reset/tegra194-reset.h>
  10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
  11 #include <dt-bindings/memory/tegra194-mc.h>
  12
  13 / {
  14         compatible = "nvidia,tegra194";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         /* control backbone */
  20         bus@0 {
  21                 compatible = "simple-bus";
  22
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
  26
  27                 apbmisc: misc@100000 {
  28                         compatible = "nvidia,tegra194-misc";
  29                         reg = <0x0 0x00100000 0x0 0xf000>,
  30                               <0x0 0x0010f000 0x0 0x1000>;
  31                 };
  32
  33                 gpio: gpio@2200000 {
  34                         compatible = "nvidia,tegra194-gpio";
  35                         reg-names = "security", "gpio";
  36                         reg = <0x0 0x2200000 0x0 0x10000>,
  37                               <0x0 0x2210000 0x0 0x10000>;
  38                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
  42                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
  43                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
  44                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
  45                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
  46                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  47                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
  48                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
  49                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
  50                                      <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
  51                                      <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
  52                                      <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
  53                                      <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
  54                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  55                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
  56                                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
  57                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
  58                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  59                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  60                                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  61                                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  62                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  63                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  64                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  65                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  66                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  67                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  68                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
  69                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  71                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
  72                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
  73                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
  74                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
  75                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
  76                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
  77                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
  78                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
  79                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
  80                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
  81                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
  82                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
  83                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
  84                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
  85                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
  86                         #interrupt-cells = <2>;
  87                         interrupt-controller;
  88                         #gpio-cells = <2>;
  89                         gpio-controller;
  90                         gpio-ranges = <&pinmux 0 0 169>;
  91                 };
  92
  93                 cbb-noc@2300000 {
  94                         compatible = "nvidia,tegra194-cbb-noc";
  95                         reg = <0x0 0x02300000 0x0 0x1000>;
  96                         interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
  97                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
  98                         nvidia,axi2apb = <&axi2apb>;
  99                         nvidia,apbmisc = <&apbmisc>;
 100                         status = "okay";
 101                 };
 102
 103                 axi2apb: axi2apb@2390000 {
 104                         compatible = "nvidia,tegra194-axi2apb";
 105                         reg = <0x0 0x2390000 0x0 0x1000>,
 106                               <0x0 0x23a0000 0x0 0x1000>,
 107                               <0x0 0x23b0000 0x0 0x1000>,
 108                               <0x0 0x23c0000 0x0 0x1000>,
 109                               <0x0 0x23d0000 0x0 0x1000>,
 110                               <0x0 0x23e0000 0x0 0x1000>;
 111                         status = "okay";
 112                 };
 113
 114                 pinmux: pinmux@2430000 {
 115                         compatible = "nvidia,tegra194-pinmux";
 116                         reg = <0x0 0x2430000 0x0 0x17000>;
 117                         status = "okay";
 118
 119                         pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {
 120                                 clkreq {
 121                                         nvidia,pins = "pex_l5_clkreq_n_pgg0";
 122                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 123                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 124                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 125                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 126                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 127                                 };
 128                         };
 129
 130                         pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
 131                                 pex_rst {
 132                                         nvidia,pins = "pex_l5_rst_n_pgg1";
 133                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 134                                         nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 135                                         nvidia,io-hv = <TEGRA_PIN_ENABLE>;
 136                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 137                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 138                                 };
 139                         };
 140                 };
 141
 142                 ethernet@2490000 {
 143                         compatible = "nvidia,tegra194-eqos",
 144                                      "nvidia,tegra186-eqos",
 145                                      "snps,dwc-qos-ethernet-4.10";
 146                         reg = <0x0 0x02490000 0x0 0x10000>;
 147                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 148                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
 149                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
 150                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
 151                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
 152                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
 153                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
 154                         resets = <&bpmp TEGRA194_RESET_EQOS>;
 155                         reset-names = "eqos";
 156                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
 157                                         <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
 158                         interconnect-names = "dma-mem", "write";
 159                         iommus = <&smmu TEGRA194_SID_EQOS>;
 160                         status = "disabled";
 161
 162                         snps,write-requests = <1>;
 163                         snps,read-requests = <3>;
 164                         snps,burst-map = <0x7>;
 165                         snps,txpbl = <16>;
 166                         snps,rxpbl = <8>;
 167                 };
 168
 169                 gpcdma: dma-controller@2600000 {
 170                         compatible = "nvidia,tegra194-gpcdma",
 171                                      "nvidia,tegra186-gpcdma";
 172                         reg = <0x0 0x2600000 0x0 0x210000>;
 173                         resets = <&bpmp TEGRA194_RESET_GPCDMA>;
 174                         reset-names = "gpcdma";
 175                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 177                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 189                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 197                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 207                         #dma-cells = <1>;
 208                         iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
 209                         dma-coherent;
 210                         dma-channel-mask = <0xfffffffe>;
 211                         status = "okay";
 212                 };
 213
 214                 aconnect@2900000 {
 215                         compatible = "nvidia,tegra194-aconnect",
 216                                      "nvidia,tegra210-aconnect";
 217                         clocks = <&bpmp TEGRA194_CLK_APE>,
 218                                  <&bpmp TEGRA194_CLK_APB2APE>;
 219                         clock-names = "ape", "apb2ape";
 220                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
 221                         status = "disabled";
 222
 223                         #address-cells = <2>;
 224                         #size-cells = <2>;
 225                         ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
 226
 227                         tegra_ahub: ahub@2900800 {
 228                                 compatible = "nvidia,tegra194-ahub",
 229                                              "nvidia,tegra186-ahub";
 230                                 reg = <0x0 0x02900800 0x0 0x800>;
 231                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 232                                 clock-names = "ahub";
 233                                 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
 234                                 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
 235                                 assigned-clock-rates = <81600000>;
 236                                 status = "disabled";
 237
 238                                 #address-cells = <2>;
 239                                 #size-cells = <2>;
 240                                 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
 241
 242                                 tegra_i2s1: i2s@2901000 {
 243                                         compatible = "nvidia,tegra194-i2s",
 244                                                      "nvidia,tegra210-i2s";
 245                                         reg = <0x0 0x2901000 0x0 0x100>;
 246                                         clocks = <&bpmp TEGRA194_CLK_I2S1>,
 247                                                  <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
 248                                         clock-names = "i2s", "sync_input";
 249                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
 250                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 251                                         assigned-clock-rates = <1536000>;
 252                                         sound-name-prefix = "I2S1";
 253                                         status = "disabled";
 254                                 };
 255
 256                                 tegra_i2s2: i2s@2901100 {
 257                                         compatible = "nvidia,tegra194-i2s",
 258                                                      "nvidia,tegra210-i2s";
 259                                         reg = <0x0 0x2901100 0x0 0x100>;
 260                                         clocks = <&bpmp TEGRA194_CLK_I2S2>,
 261                                                  <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
 262                                         clock-names = "i2s", "sync_input";
 263                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
 264                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 265                                         assigned-clock-rates = <1536000>;
 266                                         sound-name-prefix = "I2S2";
 267                                         status = "disabled";
 268                                 };
 269
 270                                 tegra_i2s3: i2s@2901200 {
 271                                         compatible = "nvidia,tegra194-i2s",
 272                                                      "nvidia,tegra210-i2s";
 273                                         reg = <0x0 0x2901200 0x0 0x100>;
 274                                         clocks = <&bpmp TEGRA194_CLK_I2S3>,
 275                                                  <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
 276                                         clock-names = "i2s", "sync_input";
 277                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
 278                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 279                                         assigned-clock-rates = <1536000>;
 280                                         sound-name-prefix = "I2S3";
 281                                         status = "disabled";
 282                                 };
 283
 284                                 tegra_i2s4: i2s@2901300 {
 285                                         compatible = "nvidia,tegra194-i2s",
 286                                                      "nvidia,tegra210-i2s";
 287                                         reg = <0x0 0x2901300 0x0 0x100>;
 288                                         clocks = <&bpmp TEGRA194_CLK_I2S4>,
 289                                                  <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
 290                                         clock-names = "i2s", "sync_input";
 291                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
 292                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 293                                         assigned-clock-rates = <1536000>;
 294                                         sound-name-prefix = "I2S4";
 295                                         status = "disabled";
 296                                 };
 297
 298                                 tegra_i2s5: i2s@2901400 {
 299                                         compatible = "nvidia,tegra194-i2s",
 300                                                      "nvidia,tegra210-i2s";
 301                                         reg = <0x0 0x2901400 0x0 0x100>;
 302                                         clocks = <&bpmp TEGRA194_CLK_I2S5>,
 303                                                  <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
 304                                         clock-names = "i2s", "sync_input";
 305                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
 306                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 307                                         assigned-clock-rates = <1536000>;
 308                                         sound-name-prefix = "I2S5";
 309                                         status = "disabled";
 310                                 };
 311
 312                                 tegra_i2s6: i2s@2901500 {
 313                                         compatible = "nvidia,tegra194-i2s",
 314                                                      "nvidia,tegra210-i2s";
 315                                         reg = <0x0 0x2901500 0x0 0x100>;
 316                                         clocks = <&bpmp TEGRA194_CLK_I2S6>,
 317                                                  <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
 318                                         clock-names = "i2s", "sync_input";
 319                                         assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
 320                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 321                                         assigned-clock-rates = <1536000>;
 322                                         sound-name-prefix = "I2S6";
 323                                         status = "disabled";
 324                                 };
 325
 326                                 tegra_sfc1: sfc@2902000 {
 327                                         compatible = "nvidia,tegra194-sfc",
 328                                                      "nvidia,tegra210-sfc";
 329                                         reg = <0x0 0x2902000 0x0 0x200>;
 330                                         sound-name-prefix = "SFC1";
 331                                         status = "disabled";
 332                                 };
 333
 334                                 tegra_sfc2: sfc@2902200 {
 335                                         compatible = "nvidia,tegra194-sfc",
 336                                                      "nvidia,tegra210-sfc";
 337                                         reg = <0x0 0x2902200 0x0 0x200>;
 338                                         sound-name-prefix = "SFC2";
 339                                         status = "disabled";
 340                                 };
 341
 342                                 tegra_sfc3: sfc@2902400 {
 343                                         compatible = "nvidia,tegra194-sfc",
 344                                                      "nvidia,tegra210-sfc";
 345                                         reg = <0x0 0x2902400 0x0 0x200>;
 346                                         sound-name-prefix = "SFC3";
 347                                         status = "disabled";
 348                                 };
 349
 350                                 tegra_sfc4: sfc@2902600 {
 351                                         compatible = "nvidia,tegra194-sfc",
 352                                                      "nvidia,tegra210-sfc";
 353                                         reg = <0x0 0x2902600 0x0 0x200>;
 354                                         sound-name-prefix = "SFC4";
 355                                         status = "disabled";
 356                                 };
 357
 358                                 tegra_amx1: amx@2903000 {
 359                                         compatible = "nvidia,tegra194-amx";
 360                                         reg = <0x0 0x2903000 0x0 0x100>;
 361                                         sound-name-prefix = "AMX1";
 362                                         status = "disabled";
 363                                 };
 364
 365                                 tegra_amx2: amx@2903100 {
 366                                         compatible = "nvidia,tegra194-amx";
 367                                         reg = <0x0 0x2903100 0x0 0x100>;
 368                                         sound-name-prefix = "AMX2";
 369                                         status = "disabled";
 370                                 };
 371
 372                                 tegra_amx3: amx@2903200 {
 373                                         compatible = "nvidia,tegra194-amx";
 374                                         reg = <0x0 0x2903200 0x0 0x100>;
 375                                         sound-name-prefix = "AMX3";
 376                                         status = "disabled";
 377                                 };
 378
 379                                 tegra_amx4: amx@2903300 {
 380                                         compatible = "nvidia,tegra194-amx";
 381                                         reg = <0x0 0x2903300 0x0 0x100>;
 382                                         sound-name-prefix = "AMX4";
 383                                         status = "disabled";
 384                                 };
 385
 386                                 tegra_adx1: adx@2903800 {
 387                                         compatible = "nvidia,tegra194-adx",
 388                                                      "nvidia,tegra210-adx";
 389                                         reg = <0x0 0x2903800 0x0 0x100>;
 390                                         sound-name-prefix = "ADX1";
 391                                         status = "disabled";
 392                                 };
 393
 394                                 tegra_adx2: adx@2903900 {
 395                                         compatible = "nvidia,tegra194-adx",
 396                                                      "nvidia,tegra210-adx";
 397                                         reg = <0x0 0x2903900 0x0 0x100>;
 398                                         sound-name-prefix = "ADX2";
 399                                         status = "disabled";
 400                                 };
 401
 402                                 tegra_adx3: adx@2903a00 {
 403                                         compatible = "nvidia,tegra194-adx",
 404                                                      "nvidia,tegra210-adx";
 405                                         reg = <0x0 0x2903a00 0x0 0x100>;
 406                                         sound-name-prefix = "ADX3";
 407                                         status = "disabled";
 408                                 };
 409
 410                                 tegra_adx4: adx@2903b00 {
 411                                         compatible = "nvidia,tegra194-adx",
 412                                                      "nvidia,tegra210-adx";
 413                                         reg = <0x0 0x2903b00 0x0 0x100>;
 414                                         sound-name-prefix = "ADX4";
 415                                         status = "disabled";
 416                                 };
 417
 418                                 tegra_dmic1: dmic@2904000 {
 419                                         compatible = "nvidia,tegra194-dmic",
 420                                                      "nvidia,tegra210-dmic";
 421                                         reg = <0x0 0x2904000 0x0 0x100>;
 422                                         clocks = <&bpmp TEGRA194_CLK_DMIC1>;
 423                                         clock-names = "dmic";
 424                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
 425                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 426                                         assigned-clock-rates = <3072000>;
 427                                         sound-name-prefix = "DMIC1";
 428                                         status = "disabled";
 429                                 };
 430
 431                                 tegra_dmic2: dmic@2904100 {
 432                                         compatible = "nvidia,tegra194-dmic",
 433                                                      "nvidia,tegra210-dmic";
 434                                         reg = <0x0 0x2904100 0x0 0x100>;
 435                                         clocks = <&bpmp TEGRA194_CLK_DMIC2>;
 436                                         clock-names = "dmic";
 437                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
 438                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 439                                         assigned-clock-rates = <3072000>;
 440                                         sound-name-prefix = "DMIC2";
 441                                         status = "disabled";
 442                                 };
 443
 444                                 tegra_dmic3: dmic@2904200 {
 445                                         compatible = "nvidia,tegra194-dmic",
 446                                                      "nvidia,tegra210-dmic";
 447                                         reg = <0x0 0x2904200 0x0 0x100>;
 448                                         clocks = <&bpmp TEGRA194_CLK_DMIC3>;
 449                                         clock-names = "dmic";
 450                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
 451                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 452                                         assigned-clock-rates = <3072000>;
 453                                         sound-name-prefix = "DMIC3";
 454                                         status = "disabled";
 455                                 };
 456
 457                                 tegra_dmic4: dmic@2904300 {
 458                                         compatible = "nvidia,tegra194-dmic",
 459                                                      "nvidia,tegra210-dmic";
 460                                         reg = <0x0 0x2904300 0x0 0x100>;
 461                                         clocks = <&bpmp TEGRA194_CLK_DMIC4>;
 462                                         clock-names = "dmic";
 463                                         assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
 464                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 465                                         assigned-clock-rates = <3072000>;
 466                                         sound-name-prefix = "DMIC4";
 467                                         status = "disabled";
 468                                 };
 469
 470                                 tegra_dspk1: dspk@2905000 {
 471                                         compatible = "nvidia,tegra194-dspk",
 472                                                      "nvidia,tegra186-dspk";
 473                                         reg = <0x0 0x2905000 0x0 0x100>;
 474                                         clocks = <&bpmp TEGRA194_CLK_DSPK1>;
 475                                         clock-names = "dspk";
 476                                         assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
 477                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 478                                         assigned-clock-rates = <12288000>;
 479                                         sound-name-prefix = "DSPK1";
 480                                         status = "disabled";
 481                                 };
 482
 483                                 tegra_dspk2: dspk@2905100 {
 484                                         compatible = "nvidia,tegra194-dspk",
 485                                                      "nvidia,tegra186-dspk";
 486                                         reg = <0x0 0x2905100 0x0 0x100>;
 487                                         clocks = <&bpmp TEGRA194_CLK_DSPK2>;
 488                                         clock-names = "dspk";
 489                                         assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
 490                                         assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
 491                                         assigned-clock-rates = <12288000>;
 492                                         sound-name-prefix = "DSPK2";
 493                                         status = "disabled";
 494                                 };
 495
 496                                 tegra_ope1: processing-engine@2908000 {
 497                                         compatible = "nvidia,tegra194-ope",
 498                                                      "nvidia,tegra210-ope";
 499                                         reg = <0x0 0x2908000 0x0 0x100>;
 500                                         sound-name-prefix = "OPE1";
 501                                         status = "disabled";
 502
 503                                         #address-cells = <2>;
 504                                         #size-cells = <2>;
 505                                         ranges;
 506
 507                                         equalizer@2908100 {
 508                                                 compatible = "nvidia,tegra194-peq",
 509                                                              "nvidia,tegra210-peq";
 510                                                 reg = <0x0 0x2908100 0x0 0x100>;
 511                                         };
 512
 513                                         dynamic-range-compressor@2908200 {
 514                                                 compatible = "nvidia,tegra194-mbdrc",
 515                                                              "nvidia,tegra210-mbdrc";
 516                                                 reg = <0x0 0x2908200 0x0 0x200>;
 517                                         };
 518                                 };
 519
 520                                 tegra_mvc1: mvc@290a000 {
 521                                         compatible = "nvidia,tegra194-mvc",
 522                                                      "nvidia,tegra210-mvc";
 523                                         reg = <0x0 0x290a000 0x0 0x200>;
 524                                         sound-name-prefix = "MVC1";
 525                                         status = "disabled";
 526                                 };
 527
 528                                 tegra_mvc2: mvc@290a200 {
 529                                         compatible = "nvidia,tegra194-mvc",
 530                                                      "nvidia,tegra210-mvc";
 531                                         reg = <0x0 0x290a200 0x0 0x200>;
 532                                         sound-name-prefix = "MVC2";
 533                                         status = "disabled";
 534                                 };
 535
 536                                 tegra_amixer: amixer@290bb00 {
 537                                         compatible = "nvidia,tegra194-amixer",
 538                                                      "nvidia,tegra210-amixer";
 539                                         reg = <0x0 0x290bb00 0x0 0x800>;
 540                                         sound-name-prefix = "MIXER1";
 541                                         status = "disabled";
 542                                 };
 543
 544                                 tegra_admaif: admaif@290f000 {
 545                                         compatible = "nvidia,tegra194-admaif",
 546                                                      "nvidia,tegra186-admaif";
 547                                         reg = <0x0 0x0290f000 0x0 0x1000>;
 548                                         dmas = <&adma 1>, <&adma 1>,
 549                                                <&adma 2>, <&adma 2>,
 550                                                <&adma 3>, <&adma 3>,
 551                                                <&adma 4>, <&adma 4>,
 552                                                <&adma 5>, <&adma 5>,
 553                                                <&adma 6>, <&adma 6>,
 554                                                <&adma 7>, <&adma 7>,
 555                                                <&adma 8>, <&adma 8>,
 556                                                <&adma 9>, <&adma 9>,
 557                                                <&adma 10>, <&adma 10>,
 558                                                <&adma 11>, <&adma 11>,
 559                                                <&adma 12>, <&adma 12>,
 560                                                <&adma 13>, <&adma 13>,
 561                                                <&adma 14>, <&adma 14>,
 562                                                <&adma 15>, <&adma 15>,
 563                                                <&adma 16>, <&adma 16>,
 564                                                <&adma 17>, <&adma 17>,
 565                                                <&adma 18>, <&adma 18>,
 566                                                <&adma 19>, <&adma 19>,
 567                                                <&adma 20>, <&adma 20>;
 568                                         dma-names = "rx1", "tx1",
 569                                                     "rx2", "tx2",
 570                                                     "rx3", "tx3",
 571                                                     "rx4", "tx4",
 572                                                     "rx5", "tx5",
 573                                                     "rx6", "tx6",
 574                                                     "rx7", "tx7",
 575                                                     "rx8", "tx8",
 576                                                     "rx9", "tx9",
 577                                                     "rx10", "tx10",
 578                                                     "rx11", "tx11",
 579                                                     "rx12", "tx12",
 580                                                     "rx13", "tx13",
 581                                                     "rx14", "tx14",
 582                                                     "rx15", "tx15",
 583                                                     "rx16", "tx16",
 584                                                     "rx17", "tx17",
 585                                                     "rx18", "tx18",
 586                                                     "rx19", "tx19",
 587                                                     "rx20", "tx20";
 588                                         status = "disabled";
 589                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>,
 590                                                         <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>;
 591                                         interconnect-names = "dma-mem", "write";
 592                                         iommus = <&smmu TEGRA194_SID_APE>;
 593                                 };
 594
 595                                 tegra_asrc: asrc@2910000 {
 596                                         compatible = "nvidia,tegra194-asrc",
 597                                                      "nvidia,tegra186-asrc";
 598                                         reg = <0x0 0x2910000 0x0 0x2000>;
 599                                         sound-name-prefix = "ASRC1";
 600                                         status = "disabled";
 601                                 };
 602                         };
 603
 604                         adma: dma-controller@2930000 {
 605                                 compatible = "nvidia,tegra194-adma",
 606                                              "nvidia,tegra186-adma";
 607                                 reg = <0x0 0x02930000 0x0 0x20000>;
 608                                 interrupt-parent = <&agic>;
 609                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 610                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 611                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 612                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 613                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 614                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 615                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 616                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 617                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 618                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 619                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 620                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 621                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 622                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 623                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 624                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 625                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 626                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 627                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 628                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 629                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 630                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 631                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 632                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 633                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 634                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 635                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 636                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 637                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 638                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 639                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 640                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 641                                 #dma-cells = <1>;
 642                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 643                                 clock-names = "d_audio";
 644                                 status = "disabled";
 645                         };
 646
 647                         agic: interrupt-controller@2a40000 {
 648                                 compatible = "nvidia,tegra194-agic",
 649                                              "nvidia,tegra210-agic";
 650                                 #interrupt-cells = <3>;
 651                                 interrupt-controller;
 652                                 reg = <0x0 0x02a41000 0x0 0x1000>,
 653                                       <0x0 0x02a42000 0x0 0x2000>;
 654                                 interrupts = <GIC_SPI 145
 655                                               (GIC_CPU_MASK_SIMPLE(4) |
 656                                                IRQ_TYPE_LEVEL_HIGH)>;
 657                                 clocks = <&bpmp TEGRA194_CLK_APE>;
 658                                 clock-names = "clk";
 659                                 status = "disabled";
 660                         };
 661                 };
 662
 663                 mc: memory-controller@2c00000 {
 664                         compatible = "nvidia,tegra194-mc";
 665                         reg = <0x0 0x02c00000 0x0 0x10000>,   /* MC-SID */
 666                               <0x0 0x02c10000 0x0 0x10000>,   /* MC Broadcast*/
 667                               <0x0 0x02c20000 0x0 0x10000>,   /* MC0 */
 668                               <0x0 0x02c30000 0x0 0x10000>,   /* MC1 */
 669                               <0x0 0x02c40000 0x0 0x10000>,   /* MC2 */
 670                               <0x0 0x02c50000 0x0 0x10000>,   /* MC3 */
 671                               <0x0 0x02b80000 0x0 0x10000>,   /* MC4 */
 672                               <0x0 0x02b90000 0x0 0x10000>,   /* MC5 */
 673                               <0x0 0x02ba0000 0x0 0x10000>,   /* MC6 */
 674                               <0x0 0x02bb0000 0x0 0x10000>,   /* MC7 */
 675                               <0x0 0x01700000 0x0 0x10000>,   /* MC8 */
 676                               <0x0 0x01710000 0x0 0x10000>,   /* MC9 */
 677                               <0x0 0x01720000 0x0 0x10000>,   /* MC10 */
 678                               <0x0 0x01730000 0x0 0x10000>,   /* MC11 */
 679                               <0x0 0x01740000 0x0 0x10000>,   /* MC12 */
 680                               <0x0 0x01750000 0x0 0x10000>,   /* MC13 */
 681                               <0x0 0x01760000 0x0 0x10000>,   /* MC14 */
 682                               <0x0 0x01770000 0x0 0x10000>;   /* MC15 */
 683                         reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
 684                                     "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
 685                                     "ch11", "ch12", "ch13", "ch14", "ch15";
 686                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 687                         #interconnect-cells = <1>;
 688                         status = "disabled";
 689
 690                         #address-cells = <2>;
 691                         #size-cells = <2>;
 692                         ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
 693                                  <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
 694                                  <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
 695
 696                         /*
 697                          * Bit 39 of addresses passing through the memory
 698                          * controller selects the XBAR format used when memory
 699                          * is accessed. This is used to transparently access
 700                          * memory in the XBAR format used by the discrete GPU
 701                          * (bit 39 set) or Tegra (bit 39 clear).
 702                          *
 703                          * As a consequence, the operating system must ensure
 704                          * that bit 39 is never used implicitly, for example
 705                          * via an I/O virtual address mapping of an IOMMU. If
 706                          * devices require access to the XBAR switch, their
 707                          * drivers must set this bit explicitly.
 708                          *
 709                          * Limit the DMA range for memory clients to [38:0].
 710                          */
 711                         dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
 712
 713                         emc: external-memory-controller@2c60000 {
 714                                 compatible = "nvidia,tegra194-emc";
 715                                 reg = <0x0 0x02c60000 0x0 0x90000>,
 716                                       <0x0 0x01780000 0x0 0x80000>;
 717                                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 718                                 clocks = <&bpmp TEGRA194_CLK_EMC>;
 719                                 clock-names = "emc";
 720
 721                                 #interconnect-cells = <0>;
 722
 723                                 nvidia,bpmp = <&bpmp>;
 724                         };
 725                 };
 726
 727                 timer@3010000 {
 728                         compatible = "nvidia,tegra186-timer";
 729                         reg = <0x0 0x03010000 0x0 0x000e0000>;
 730                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 740                         status = "okay";
 741                 };
 742
 743                 uarta: serial@3100000 {
 744                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 745                         reg = <0x0 0x03100000 0x0 0x40>;
 746                         reg-shift = <2>;
 747                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 748                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
 749                         resets = <&bpmp TEGRA194_RESET_UARTA>;
 750                         status = "disabled";
 751                 };
 752
 753                 uartb: serial@3110000 {
 754                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 755                         reg = <0x0 0x03110000 0x0 0x40>;
 756                         reg-shift = <2>;
 757                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 758                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
 759                         resets = <&bpmp TEGRA194_RESET_UARTB>;
 760                         status = "disabled";
 761                 };
 762
 763                 uartd: serial@3130000 {
 764                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 765                         reg = <0x0 0x03130000 0x0 0x40>;
 766                         reg-shift = <2>;
 767                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 768                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
 769                         clock-names = "serial";
 770                         resets = <&bpmp TEGRA194_RESET_UARTD>;
 771                         reset-names = "serial";
 772                         status = "disabled";
 773                 };
 774
 775                 uarte: serial@3140000 {
 776                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 777                         reg = <0x0 0x03140000 0x0 0x40>;
 778                         reg-shift = <2>;
 779                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 780                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 781                         clock-names = "serial";
 782                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 783                         reset-names = "serial";
 784                         status = "disabled";
 785                 };
 786
 787                 uartf: serial@3150000 {
 788                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 789                         reg = <0x0 0x03150000 0x0 0x40>;
 790                         reg-shift = <2>;
 791                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 792                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 793                         clock-names = "serial";
 794                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 795                         reset-names = "serial";
 796                         status = "disabled";
 797                 };
 798
 799                 gen1_i2c: i2c@3160000 {
 800                         compatible = "nvidia,tegra194-i2c";
 801                         reg = <0x0 0x03160000 0x0 0x10000>;
 802                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 803                         #address-cells = <1>;
 804                         #size-cells = <0>;
 805                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 806                         clock-names = "div-clk";
 807                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 808                         reset-names = "i2c";
 809                         dmas = <&gpcdma 21>, <&gpcdma 21>;
 810                         dma-names = "rx", "tx";
 811                         status = "disabled";
 812                 };
 813
 814                 uarth: serial@3170000 {
 815                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 816                         reg = <0x0 0x03170000 0x0 0x40>;
 817                         reg-shift = <2>;
 818                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 819                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 820                         clock-names = "serial";
 821                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 822                         reset-names = "serial";
 823                         status = "disabled";
 824                 };
 825
 826                 cam_i2c: i2c@3180000 {
 827                         compatible = "nvidia,tegra194-i2c";
 828                         reg = <0x0 0x03180000 0x0 0x10000>;
 829                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 830                         #address-cells = <1>;
 831                         #size-cells = <0>;
 832                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 833                         clock-names = "div-clk";
 834                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 835                         reset-names = "i2c";
 836                         dmas = <&gpcdma 23>, <&gpcdma 23>;
 837                         dma-names = "rx", "tx";
 838                         status = "disabled";
 839                 };
 840
 841                 /* shares pads with dpaux1 */
 842                 dp_aux_ch1_i2c: i2c@3190000 {
 843                         compatible = "nvidia,tegra194-i2c";
 844                         reg = <0x0 0x03190000 0x0 0x10000>;
 845                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 846                         #address-cells = <1>;
 847                         #size-cells = <0>;
 848                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 849                         clock-names = "div-clk";
 850                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 851                         reset-names = "i2c";
 852                         pinctrl-0 = <&state_dpaux1_i2c>;
 853                         pinctrl-1 = <&state_dpaux1_off>;
 854                         pinctrl-names = "default", "idle";
 855                         dmas = <&gpcdma 26>, <&gpcdma 26>;
 856                         dma-names = "rx", "tx";
 857                         status = "disabled";
 858                 };
 859
 860                 /* shares pads with dpaux0 */
 861                 dp_aux_ch0_i2c: i2c@31b0000 {
 862                         compatible = "nvidia,tegra194-i2c";
 863                         reg = <0x0 0x031b0000 0x0 0x10000>;
 864                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 865                         #address-cells = <1>;
 866                         #size-cells = <0>;
 867                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 868                         clock-names = "div-clk";
 869                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 870                         reset-names = "i2c";
 871                         pinctrl-0 = <&state_dpaux0_i2c>;
 872                         pinctrl-1 = <&state_dpaux0_off>;
 873                         pinctrl-names = "default", "idle";
 874                         dmas = <&gpcdma 30>, <&gpcdma 30>;
 875                         dma-names = "rx", "tx";
 876                         status = "disabled";
 877                 };
 878
 879                 /* shares pads with dpaux2 */
 880                 dp_aux_ch2_i2c: i2c@31c0000 {
 881                         compatible = "nvidia,tegra194-i2c";
 882                         reg = <0x0 0x031c0000 0x0 0x10000>;
 883                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 884                         #address-cells = <1>;
 885                         #size-cells = <0>;
 886                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 887                         clock-names = "div-clk";
 888                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 889                         reset-names = "i2c";
 890                         pinctrl-0 = <&state_dpaux2_i2c>;
 891                         pinctrl-1 = <&state_dpaux2_off>;
 892                         pinctrl-names = "default", "idle";
 893                         dmas = <&gpcdma 27>, <&gpcdma 27>;
 894                         dma-names = "rx", "tx";
 895                         status = "disabled";
 896                 };
 897
 898                 /* shares pads with dpaux3 */
 899                 dp_aux_ch3_i2c: i2c@31e0000 {
 900                         compatible = "nvidia,tegra194-i2c";
 901                         reg = <0x0 0x031e0000 0x0 0x10000>;
 902                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 903                         #address-cells = <1>;
 904                         #size-cells = <0>;
 905                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 906                         clock-names = "div-clk";
 907                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 908                         reset-names = "i2c";
 909                         pinctrl-0 = <&state_dpaux3_i2c>;
 910                         pinctrl-1 = <&state_dpaux3_off>;
 911                         pinctrl-names = "default", "idle";
 912                         dmas = <&gpcdma 31>, <&gpcdma 31>;
 913                         dma-names = "rx", "tx";
 914                         status = "disabled";
 915                 };
 916
 917                 spi@3270000 {
 918                         compatible = "nvidia,tegra194-qspi";
 919                         reg = <0x0 0x3270000 0x0 0x1000>;
 920                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 921                         #address-cells = <1>;
 922                         #size-cells = <0>;
 923                         clocks = <&bpmp TEGRA194_CLK_QSPI0>,
 924                                  <&bpmp TEGRA194_CLK_QSPI0_PM>;
 925                         clock-names = "qspi", "qspi_out";
 926                         resets = <&bpmp TEGRA194_RESET_QSPI0>;
 927                         status = "disabled";
 928                 };
 929
 930                 pwm1: pwm@3280000 {
 931                         compatible = "nvidia,tegra194-pwm",
 932                                      "nvidia,tegra186-pwm";
 933                         reg = <0x0 0x3280000 0x0 0x10000>;
 934                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 935                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 936                         reset-names = "pwm";
 937                         status = "disabled";
 938                         #pwm-cells = <2>;
 939                 };
 940
 941                 pwm2: pwm@3290000 {
 942                         compatible = "nvidia,tegra194-pwm",
 943                                      "nvidia,tegra186-pwm";
 944                         reg = <0x0 0x3290000 0x0 0x10000>;
 945                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 946                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 947                         reset-names = "pwm";
 948                         status = "disabled";
 949                         #pwm-cells = <2>;
 950                 };
 951
 952                 pwm3: pwm@32a0000 {
 953                         compatible = "nvidia,tegra194-pwm",
 954                                      "nvidia,tegra186-pwm";
 955                         reg = <0x0 0x32a0000 0x0 0x10000>;
 956                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 957                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 958                         reset-names = "pwm";
 959                         status = "disabled";
 960                         #pwm-cells = <2>;
 961                 };
 962
 963                 pwm5: pwm@32c0000 {
 964                         compatible = "nvidia,tegra194-pwm",
 965                                      "nvidia,tegra186-pwm";
 966                         reg = <0x0 0x32c0000 0x0 0x10000>;
 967                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 968                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 969                         reset-names = "pwm";
 970                         status = "disabled";
 971                         #pwm-cells = <2>;
 972                 };
 973
 974                 pwm6: pwm@32d0000 {
 975                         compatible = "nvidia,tegra194-pwm",
 976                                      "nvidia,tegra186-pwm";
 977                         reg = <0x0 0x32d0000 0x0 0x10000>;
 978                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 979                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 980                         reset-names = "pwm";
 981                         status = "disabled";
 982                         #pwm-cells = <2>;
 983                 };
 984
 985                 pwm7: pwm@32e0000 {
 986                         compatible = "nvidia,tegra194-pwm",
 987                                      "nvidia,tegra186-pwm";
 988                         reg = <0x0 0x32e0000 0x0 0x10000>;
 989                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 990                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 991                         reset-names = "pwm";
 992                         status = "disabled";
 993                         #pwm-cells = <2>;
 994                 };
 995
 996                 pwm8: pwm@32f0000 {
 997                         compatible = "nvidia,tegra194-pwm",
 998                                      "nvidia,tegra186-pwm";
 999                         reg = <0x0 0x32f0000 0x0 0x10000>;
1000                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
1001                         resets = <&bpmp TEGRA194_RESET_PWM8>;
1002                         reset-names = "pwm";
1003                         status = "disabled";
1004                         #pwm-cells = <2>;
1005                 };
1006
1007                 spi@3300000 {
1008                         compatible = "nvidia,tegra194-qspi";
1009                         reg = <0x0 0x3300000 0x0 0x1000>;
1010                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1011                         #address-cells = <1>;
1012                         #size-cells = <0>;
1013                         clocks = <&bpmp TEGRA194_CLK_QSPI1>,
1014                                  <&bpmp TEGRA194_CLK_QSPI1_PM>;
1015                         clock-names = "qspi", "qspi_out";
1016                         resets = <&bpmp TEGRA194_RESET_QSPI1>;
1017                         status = "disabled";
1018                 };
1019
1020                 sdmmc1: mmc@3400000 {
1021                         compatible = "nvidia,tegra194-sdhci";
1022                         reg = <0x0 0x03400000 0x0 0x10000>;
1023                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1024                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026                         clock-names = "sdhci", "tmclk";
1027                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1028                                           <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1029                         assigned-clock-parents =
1030                                           <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1031                                           <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1032                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033                         reset-names = "sdhci";
1034                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
1035                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
1036                         interconnect-names = "dma-mem", "write";
1037                         iommus = <&smmu TEGRA194_SID_SDMMC1>;
1038                         pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1039                         pinctrl-0 = <&sdmmc1_3v3>;
1040                         pinctrl-1 = <&sdmmc1_1v8>;
1041                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1042                                                                         <0x07>;
1043                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1044                                                                         <0x07>;
1045                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1047                                                                         <0x07>;
1048                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050                         nvidia,default-tap = <0x9>;
1051                         nvidia,default-trim = <0x5>;
1052                         sd-uhs-sdr25;
1053                         sd-uhs-sdr50;
1054                         sd-uhs-ddr50;
1055                         sd-uhs-sdr104;
1056                         status = "disabled";
1057                 };
1058
1059                 sdmmc3: mmc@3440000 {
1060                         compatible = "nvidia,tegra194-sdhci";
1061                         reg = <0x0 0x03440000 0x0 0x10000>;
1062                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1063                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065                         clock-names = "sdhci", "tmclk";
1066                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1067                                           <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1068                         assigned-clock-parents =
1069                                           <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1070                                           <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1071                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072                         reset-names = "sdhci";
1073                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
1074                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
1075                         interconnect-names = "dma-mem", "write";
1076                         iommus = <&smmu TEGRA194_SID_SDMMC3>;
1077                         pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1078                         pinctrl-0 = <&sdmmc3_3v3>;
1079                         pinctrl-1 = <&sdmmc3_1v8>;
1080                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1084                                                                         <0x07>;
1085                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1087                                                                         <0x07>;
1088                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090                         nvidia,default-tap = <0x9>;
1091                         nvidia,default-trim = <0x5>;
1092                         sd-uhs-sdr25;
1093                         sd-uhs-sdr50;
1094                         sd-uhs-ddr50;
1095                         sd-uhs-sdr104;
1096                         status = "disabled";
1097                 };
1098
1099                 sdmmc4: mmc@3460000 {
1100                         compatible = "nvidia,tegra194-sdhci";
1101                         reg = <0x0 0x03460000 0x0 0x10000>;
1102                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1103                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105                         clock-names = "sdhci", "tmclk";
1106                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107                                           <&bpmp TEGRA194_CLK_PLLC4>;
1108                         assigned-clock-parents =
1109                                           <&bpmp TEGRA194_CLK_PLLC4>;
1110                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111                         reset-names = "sdhci";
1112                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
1113                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
1114                         interconnect-names = "dma-mem", "write";
1115                         iommus = <&smmu TEGRA194_SID_SDMMC4>;
1116                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1120                                                                         <0x0a>;
1121                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1123                                                                         <0x0a>;
1124                         nvidia,default-tap = <0x8>;
1125                         nvidia,default-trim = <0x14>;
1126                         nvidia,dqs-trim = <40>;
1127                         cap-mmc-highspeed;
1128                         mmc-ddr-1_8v;
1129                         mmc-hs200-1_8v;
1130                         mmc-hs400-1_8v;
1131                         mmc-hs400-enhanced-strobe;
1132                         supports-cqe;
1133                         status = "disabled";
1134                 };
1135
1136                 hda@3510000 {
1137                         compatible = "nvidia,tegra194-hda";
1138                         reg = <0x0 0x3510000 0x0 0x10000>;
1139                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1140                         clocks = <&bpmp TEGRA194_CLK_HDA>,
1141                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143                         clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144                         resets = <&bpmp TEGRA194_RESET_HDA>,
1145                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146                         reset-names = "hda", "hda2hdmi";
1147                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1148                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
1149                                         <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
1150                         interconnect-names = "dma-mem", "write";
1151                         iommus = <&smmu TEGRA194_SID_HDA>;
1152                         status = "disabled";
1153                 };
1154
1155                 xusb_padctl: padctl@3520000 {
1156                         compatible = "nvidia,tegra194-xusb-padctl";
1157                         reg = <0x0 0x03520000 0x0 0x1000>,
1158                               <0x0 0x03540000 0x0 0x1000>;
1159                         reg-names = "padctl", "ao";
1160                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1161
1162                         resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163                         reset-names = "padctl";
1164
1165                         status = "disabled";
1166
1167                         pads {
1168                                 usb2 {
1169                                         clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170                                         clock-names = "trk";
1171
1172                                         lanes {
1173                                                 usb2-0 {
1174                                                         nvidia,function = "xusb";
1175                                                         status = "disabled";
1176                                                         #phy-cells = <0>;
1177                                                 };
1178
1179                                                 usb2-1 {
1180                                                         nvidia,function = "xusb";
1181                                                         status = "disabled";
1182                                                         #phy-cells = <0>;
1183                                                 };
1184
1185                                                 usb2-2 {
1186                                                         nvidia,function = "xusb";
1187                                                         status = "disabled";
1188                                                         #phy-cells = <0>;
1189                                                 };
1190
1191                                                 usb2-3 {
1192                                                         nvidia,function = "xusb";
1193                                                         status = "disabled";
1194                                                         #phy-cells = <0>;
1195                                                 };
1196                                         };
1197                                 };
1198
1199                                 usb3 {
1200                                         lanes {
1201                                                 usb3-0 {
1202                                                         nvidia,function = "xusb";
1203                                                         status = "disabled";
1204                                                         #phy-cells = <0>;
1205                                                 };
1206
1207                                                 usb3-1 {
1208                                                         nvidia,function = "xusb";
1209                                                         status = "disabled";
1210                                                         #phy-cells = <0>;
1211                                                 };
1212
1213                                                 usb3-2 {
1214                                                         nvidia,function = "xusb";
1215                                                         status = "disabled";
1216                                                         #phy-cells = <0>;
1217                                                 };
1218
1219                                                 usb3-3 {
1220                                                         nvidia,function = "xusb";
1221                                                         status = "disabled";
1222                                                         #phy-cells = <0>;
1223                                                 };
1224                                         };
1225                                 };
1226                         };
1227
1228                         ports {
1229                                 usb2-0 {
1230                                         status = "disabled";
1231                                 };
1232
1233                                 usb2-1 {
1234                                         status = "disabled";
1235                                 };
1236
1237                                 usb2-2 {
1238                                         status = "disabled";
1239                                 };
1240
1241                                 usb2-3 {
1242                                         status = "disabled";
1243                                 };
1244
1245                                 usb3-0 {
1246                                         status = "disabled";
1247                                 };
1248
1249                                 usb3-1 {
1250                                         status = "disabled";
1251                                 };
1252
1253                                 usb3-2 {
1254                                         status = "disabled";
1255                                 };
1256
1257                                 usb3-3 {
1258                                         status = "disabled";
1259                                 };
1260                         };
1261                 };
1262
1263                 usb@3550000 {
1264                         compatible = "nvidia,tegra194-xudc";
1265                         reg = <0x0 0x03550000 0x0 0x8000>,
1266                               <0x0 0x03558000 0x0 0x1000>;
1267                         reg-names = "base", "fpci";
1268                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1269                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
1272                                  <&bpmp TEGRA194_CLK_XUSB_FS>;
1273                         clock-names = "dev", "ss", "ss_src", "fs_src";
1274                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>,
1275                                         <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>;
1276                         interconnect-names = "dma-mem", "write";
1277                         iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1278                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280                         power-domain-names = "dev", "ss";
1281                         nvidia,xusb-padctl = <&xusb_padctl>;
1282                         dma-coherent;
1283                         status = "disabled";
1284                 };
1285
1286                 usb@3610000 {
1287                         compatible = "nvidia,tegra194-xusb";
1288                         reg = <0x0 0x03610000 0x0 0x40000>,
1289                               <0x0 0x03600000 0x0 0x10000>;
1290                         reg-names = "hcd", "fpci";
1291
1292                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1293                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1294
1295                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296                                  <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
1299                                  <&bpmp TEGRA194_CLK_CLK_M>,
1300                                  <&bpmp TEGRA194_CLK_XUSB_FS>,
1301                                  <&bpmp TEGRA194_CLK_UTMIPLL>,
1302                                  <&bpmp TEGRA194_CLK_CLK_M>,
1303                                  <&bpmp TEGRA194_CLK_PLLE>;
1304                         clock-names = "xusb_host", "xusb_falcon_src",
1305                                       "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1306                                       "xusb_fs_src", "pll_u_480m", "clk_m",
1307                                       "pll_e";
1308                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1309                                         <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1310                         interconnect-names = "dma-mem", "write";
1311                         iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1312
1313                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315                         power-domain-names = "xusb_host", "xusb_ss";
1316
1317                         nvidia,xusb-padctl = <&xusb_padctl>;
1318                         status = "disabled";
1319                 };
1320
1321                 fuse@3820000 {
1322                         compatible = "nvidia,tegra194-efuse";
1323                         reg = <0x0 0x03820000 0x0 0x10000>;
1324                         clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325                         clock-names = "fuse";
1326                 };
1327
1328                 gic: interrupt-controller@3881000 {
1329                         compatible = "arm,gic-400";
1330                         #interrupt-cells = <3>;
1331                         interrupt-controller;
1332                         reg = <0x0 0x03881000 0x0 0x1000>,
1333                               <0x0 0x03882000 0x0 0x2000>,
1334                               <0x0 0x03884000 0x0 0x2000>,
1335                               <0x0 0x03886000 0x0 0x2000>;
1336                         interrupts = <GIC_PPI 9
1337                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1338                         interrupt-parent = <&gic>;
1339                 };
1340
1341                 cec@3960000 {
1342                         compatible = "nvidia,tegra194-cec";
1343                         reg = <0x0 0x03960000 0x0 0x10000>;
1344                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1345                         clocks = <&bpmp TEGRA194_CLK_CEC>;
1346                         clock-names = "cec";
1347                         status = "disabled";
1348                 };
1349
1350                 hte_lic: hardware-timestamp@3aa0000 {
1351                         compatible = "nvidia,tegra194-gte-lic";
1352                         reg = <0x0 0x3aa0000 0x0 0x10000>;
1353                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1354                         nvidia,int-threshold = <1>;
1355                         nvidia,slices = <11>;
1356                         #timestamp-cells = <1>;
1357                         status = "okay";
1358                 };
1359
1360                 hsp_top0: hsp@3c00000 {
1361                         compatible = "nvidia,tegra194-hsp";
1362                         reg = <0x0 0x03c00000 0x0 0xa0000>;
1363                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1364                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1365                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1366                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1367                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1368                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1369                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1370                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1371                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1372                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1373                                           "shared3", "shared4", "shared5", "shared6",
1374                                           "shared7";
1375                         #mbox-cells = <2>;
1376                 };
1377
1378                 p2u_hsio_0: phy@3e10000 {
1379                         compatible = "nvidia,tegra194-p2u";
1380                         reg = <0x0 0x03e10000 0x0 0x10000>;
1381                         reg-names = "ctl";
1382
1383                         #phy-cells = <0>;
1384                 };
1385
1386                 p2u_hsio_1: phy@3e20000 {
1387                         compatible = "nvidia,tegra194-p2u";
1388                         reg = <0x0 0x03e20000 0x0 0x10000>;
1389                         reg-names = "ctl";
1390
1391                         #phy-cells = <0>;
1392                 };
1393
1394                 p2u_hsio_2: phy@3e30000 {
1395                         compatible = "nvidia,tegra194-p2u";
1396                         reg = <0x0 0x03e30000 0x0 0x10000>;
1397                         reg-names = "ctl";
1398
1399                         #phy-cells = <0>;
1400                 };
1401
1402                 p2u_hsio_3: phy@3e40000 {
1403                         compatible = "nvidia,tegra194-p2u";
1404                         reg = <0x0 0x03e40000 0x0 0x10000>;
1405                         reg-names = "ctl";
1406
1407                         #phy-cells = <0>;
1408                 };
1409
1410                 p2u_hsio_4: phy@3e50000 {
1411                         compatible = "nvidia,tegra194-p2u";
1412                         reg = <0x0 0x03e50000 0x0 0x10000>;
1413                         reg-names = "ctl";
1414
1415                         #phy-cells = <0>;
1416                 };
1417
1418                 p2u_hsio_5: phy@3e60000 {
1419                         compatible = "nvidia,tegra194-p2u";
1420                         reg = <0x0 0x03e60000 0x0 0x10000>;
1421                         reg-names = "ctl";
1422
1423                         #phy-cells = <0>;
1424                 };
1425
1426                 p2u_hsio_6: phy@3e70000 {
1427                         compatible = "nvidia,tegra194-p2u";
1428                         reg = <0x0 0x03e70000 0x0 0x10000>;
1429                         reg-names = "ctl";
1430
1431                         #phy-cells = <0>;
1432                 };
1433
1434                 p2u_hsio_7: phy@3e80000 {
1435                         compatible = "nvidia,tegra194-p2u";
1436                         reg = <0x0 0x03e80000 0x0 0x10000>;
1437                         reg-names = "ctl";
1438
1439                         #phy-cells = <0>;
1440                 };
1441
1442                 p2u_hsio_8: phy@3e90000 {
1443                         compatible = "nvidia,tegra194-p2u";
1444                         reg = <0x0 0x03e90000 0x0 0x10000>;
1445                         reg-names = "ctl";
1446
1447                         #phy-cells = <0>;
1448                 };
1449
1450                 p2u_hsio_9: phy@3ea0000 {
1451                         compatible = "nvidia,tegra194-p2u";
1452                         reg = <0x0 0x03ea0000 0x0 0x10000>;
1453                         reg-names = "ctl";
1454
1455                         #phy-cells = <0>;
1456                 };
1457
1458                 p2u_nvhs_0: phy@3eb0000 {
1459                         compatible = "nvidia,tegra194-p2u";
1460                         reg = <0x0 0x03eb0000 0x0 0x10000>;
1461                         reg-names = "ctl";
1462
1463                         #phy-cells = <0>;
1464                 };
1465
1466                 p2u_nvhs_1: phy@3ec0000 {
1467                         compatible = "nvidia,tegra194-p2u";
1468                         reg = <0x0 0x03ec0000 0x0 0x10000>;
1469                         reg-names = "ctl";
1470
1471                         #phy-cells = <0>;
1472                 };
1473
1474                 p2u_nvhs_2: phy@3ed0000 {
1475                         compatible = "nvidia,tegra194-p2u";
1476                         reg = <0x0 0x03ed0000 0x0 0x10000>;
1477                         reg-names = "ctl";
1478
1479                         #phy-cells = <0>;
1480                 };
1481
1482                 p2u_nvhs_3: phy@3ee0000 {
1483                         compatible = "nvidia,tegra194-p2u";
1484                         reg = <0x0 0x03ee0000 0x0 0x10000>;
1485                         reg-names = "ctl";
1486
1487                         #phy-cells = <0>;
1488                 };
1489
1490                 p2u_nvhs_4: phy@3ef0000 {
1491                         compatible = "nvidia,tegra194-p2u";
1492                         reg = <0x0 0x03ef0000 0x0 0x10000>;
1493                         reg-names = "ctl";
1494
1495                         #phy-cells = <0>;
1496                 };
1497
1498                 p2u_nvhs_5: phy@3f00000 {
1499                         compatible = "nvidia,tegra194-p2u";
1500                         reg = <0x0 0x03f00000 0x0 0x10000>;
1501                         reg-names = "ctl";
1502
1503                         #phy-cells = <0>;
1504                 };
1505
1506                 p2u_nvhs_6: phy@3f10000 {
1507                         compatible = "nvidia,tegra194-p2u";
1508                         reg = <0x0 0x03f10000 0x0 0x10000>;
1509                         reg-names = "ctl";
1510
1511                         #phy-cells = <0>;
1512                 };
1513
1514                 p2u_nvhs_7: phy@3f20000 {
1515                         compatible = "nvidia,tegra194-p2u";
1516                         reg = <0x0 0x03f20000 0x0 0x10000>;
1517                         reg-names = "ctl";
1518
1519                         #phy-cells = <0>;
1520                 };
1521
1522                 p2u_hsio_10: phy@3f30000 {
1523                         compatible = "nvidia,tegra194-p2u";
1524                         reg = <0x0 0x03f30000 0x0 0x10000>;
1525                         reg-names = "ctl";
1526
1527                         #phy-cells = <0>;
1528                 };
1529
1530                 p2u_hsio_11: phy@3f40000 {
1531                         compatible = "nvidia,tegra194-p2u";
1532                         reg = <0x0 0x03f40000 0x0 0x10000>;
1533                         reg-names = "ctl";
1534
1535                         #phy-cells = <0>;
1536                 };
1537
1538                 sce-noc@b600000 {
1539                         compatible = "nvidia,tegra194-sce-noc";
1540                         reg = <0x0 0xb600000 0x0 0x1000>;
1541                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
1542                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1543                         nvidia,axi2apb = <&axi2apb>;
1544                         nvidia,apbmisc = <&apbmisc>;
1545                         status = "okay";
1546                 };
1547
1548                 rce-noc@be00000 {
1549                         compatible = "nvidia,tegra194-rce-noc";
1550                         reg = <0x0 0xbe00000 0x0 0x1000>;
1551                         interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
1552                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1553                         nvidia,axi2apb = <&axi2apb>;
1554                         nvidia,apbmisc = <&apbmisc>;
1555                         status = "okay";
1556                 };
1557
1558                 hsp_aon: hsp@c150000 {
1559                         compatible = "nvidia,tegra194-hsp";
1560                         reg = <0x0 0x0c150000 0x0 0x90000>;
1561                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1562                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1563                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1564                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1565                         /*
1566                          * Shared interrupt 0 is routed only to AON/SPE, so
1567                          * we only have 4 shared interrupts for the CCPLEX.
1568                          */
1569                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570                         #mbox-cells = <2>;
1571                 };
1572
1573                 hte_aon: hardware-timestamp@c1e0000 {
1574                         compatible = "nvidia,tegra194-gte-aon";
1575                         reg = <0x0 0xc1e0000 0x0 0x10000>;
1576                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1577                         nvidia,int-threshold = <1>;
1578                         nvidia,slices = <3>;
1579                         #timestamp-cells = <1>;
1580                         status = "okay";
1581                 };
1582
1583                 gen2_i2c: i2c@c240000 {
1584                         compatible = "nvidia,tegra194-i2c";
1585                         reg = <0x0 0x0c240000 0x0 0x10000>;
1586                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1587                         #address-cells = <1>;
1588                         #size-cells = <0>;
1589                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590                         clock-names = "div-clk";
1591                         resets = <&bpmp TEGRA194_RESET_I2C2>;
1592                         reset-names = "i2c";
1593                         dmas = <&gpcdma 22>, <&gpcdma 22>;
1594                         dma-names = "rx", "tx";
1595                         status = "disabled";
1596                 };
1597
1598                 gen8_i2c: i2c@c250000 {
1599                         compatible = "nvidia,tegra194-i2c";
1600                         reg = <0x0 0x0c250000 0x0 0x10000>;
1601                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1602                         #address-cells = <1>;
1603                         #size-cells = <0>;
1604                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605                         clock-names = "div-clk";
1606                         resets = <&bpmp TEGRA194_RESET_I2C8>;
1607                         reset-names = "i2c";
1608                         dmas = <&gpcdma 0>, <&gpcdma 0>;
1609                         dma-names = "rx", "tx";
1610                         status = "disabled";
1611                 };
1612
1613                 uartc: serial@c280000 {
1614                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1615                         reg = <0x0 0x0c280000 0x0 0x40>;
1616                         reg-shift = <2>;
1617                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1618                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619                         clock-names = "serial";
1620                         resets = <&bpmp TEGRA194_RESET_UARTC>;
1621                         reset-names = "serial";
1622                         status = "disabled";
1623                 };
1624
1625                 uartg: serial@c290000 {
1626                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1627                         reg = <0x0 0x0c290000 0x0 0x40>;
1628                         reg-shift = <2>;
1629                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1630                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631                         clock-names = "serial";
1632                         resets = <&bpmp TEGRA194_RESET_UARTG>;
1633                         reset-names = "serial";
1634                         status = "disabled";
1635                 };
1636
1637                 rtc: rtc@c2a0000 {
1638                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1639                         reg = <0x0 0x0c2a0000 0x0 0x10000>;
1640                         interrupt-parent = <&pmc>;
1641                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1642                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643                         clock-names = "rtc";
1644                         status = "disabled";
1645                 };
1646
1647                 gpio_aon: gpio@c2f0000 {
1648                         compatible = "nvidia,tegra194-gpio-aon";
1649                         reg-names = "security", "gpio";
1650                         reg = <0x0 0xc2f0000 0x0 0x1000>,
1651                               <0x0 0xc2f1000 0x0 0x1000>;
1652                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1653                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1654                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1655                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1656                         gpio-controller;
1657                         #gpio-cells = <2>;
1658                         interrupt-controller;
1659                         #interrupt-cells = <2>;
1660                         gpio-ranges = <&pinmux_aon 0 0 30>;
1661                 };
1662
1663                 pinmux_aon: pinmux@c300000 {
1664                         compatible = "nvidia,tegra194-pinmux-aon";
1665                         reg = <0x0 0xc300000 0x0 0x4000>;
1666
1667                         status = "okay";
1668                 };
1669
1670                 pwm4: pwm@c340000 {
1671                         compatible = "nvidia,tegra194-pwm",
1672                                      "nvidia,tegra186-pwm";
1673                         reg = <0x0 0xc340000 0x0 0x10000>;
1674                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
1675                         resets = <&bpmp TEGRA194_RESET_PWM4>;
1676                         reset-names = "pwm";
1677                         status = "disabled";
1678                         #pwm-cells = <2>;
1679                 };
1680
1681                 pmc: pmc@c360000 {
1682                         compatible = "nvidia,tegra194-pmc";
1683                         reg = <0x0 0x0c360000 0x0 0x10000>,
1684                               <0x0 0x0c370000 0x0 0x10000>,
1685                               <0x0 0x0c380000 0x0 0x10000>,
1686                               <0x0 0x0c390000 0x0 0x10000>,
1687                               <0x0 0x0c3a0000 0x0 0x10000>;
1688                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689
1690                         #interrupt-cells = <2>;
1691                         interrupt-controller;
1692
1693                         sdmmc1_1v8: sdmmc1-1v8 {
1694                                 pins = "sdmmc1-hv";
1695                                 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1696                         };
1697
1698                         sdmmc1_3v3: sdmmc1-3v3 {
1699                                 pins = "sdmmc1-hv";
1700                                 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1701                         };
1702
1703                         sdmmc3_1v8: sdmmc3-1v8 {
1704                                 pins = "sdmmc3-hv";
1705                                 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1706                         };
1707
1708                         sdmmc3_3v3: sdmmc3-3v3 {
1709                                 pins = "sdmmc3-hv";
1710                                 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1711                         };
1712                 };
1713
1714                 aon-noc@c600000 {
1715                         compatible = "nvidia,tegra194-aon-noc";
1716                         reg = <0x0 0xc600000 0x0 0x1000>;
1717                         interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1718                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1719                         nvidia,apbmisc = <&apbmisc>;
1720                         status = "okay";
1721                 };
1722
1723                 bpmp-noc@d600000 {
1724                         compatible = "nvidia,tegra194-bpmp-noc";
1725                         reg = <0x0 0xd600000 0x0 0x1000>;
1726                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
1727                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1728                         nvidia,axi2apb = <&axi2apb>;
1729                         nvidia,apbmisc = <&apbmisc>;
1730                         status = "okay";
1731                 };
1732
1733                 iommu@10000000 {
1734                         compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1735                         reg = <0x0 0x10000000 0x0 0x800000>;
1736                         interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1738                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1740                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1741                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1742                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1743                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1744                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1745                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1746                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1747                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1748                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1749                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1750                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1751                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1752                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1753                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1754                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1755                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1756                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1757                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1758                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1759                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1760                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1761                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1762                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1763                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1764                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1765                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1766                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1767                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1768                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1769                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1770                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1771                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1772                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1773                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1774                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1775                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1776                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1777                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1778                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1779                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1780                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1781                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1782                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1783                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1784                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1785                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1786                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1787                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1788                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1789                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1790                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1791                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1792                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1793                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1794                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1795                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1796                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1797                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1798                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1799                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1800                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1801                         stream-match-mask = <0x7f80>;
1802                         #global-interrupts = <1>;
1803                         #iommu-cells = <1>;
1804
1805                         nvidia,memory-controller = <&mc>;
1806                         status = "disabled";
1807                 };
1808
1809                 smmu: iommu@12000000 {
1810                         compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1811                         reg = <0x0 0x12000000 0x0 0x800000>,
1812                               <0x0 0x11000000 0x0 0x800000>;
1813                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1814                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1815                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1816                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1817                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1818                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1819                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1820                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1821                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1822                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1823                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1824                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1826                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1827                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1828                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1829                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1830                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1831                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1832                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1833                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1834                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1835                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1836                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1837                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1838                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1840                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1841                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1842                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1843                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1844                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1845                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1846                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1847                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1848                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1849                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1850                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1851                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1852                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1853                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1854                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1855                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1856                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1857                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1858                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1859                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1860                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1861                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1862                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1863                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1864                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1865                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1867                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1868                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1869                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1870                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1871                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1872                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1873                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1874                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1875                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1876                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1877                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1878                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1879                         stream-match-mask = <0x7f80>;
1880                         #global-interrupts = <2>;
1881                         #iommu-cells = <1>;
1882
1883                         nvidia,memory-controller = <&mc>;
1884                         status = "okay";
1885                 };
1886
1887                 host1x@13e00000 {
1888                         compatible = "nvidia,tegra194-host1x";
1889                         reg = <0x0 0x13e00000 0x0 0x10000>,
1890                               <0x0 0x13e10000 0x0 0x10000>;
1891                         reg-names = "hypervisor", "vm";
1892                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1893                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1894                         interrupt-names = "syncpt", "host1x";
1895                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896                         clock-names = "host1x";
1897                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898                         reset-names = "host1x";
1899
1900                         #address-cells = <2>;
1901                         #size-cells = <2>;
1902                         ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>;
1903
1904                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1905                         interconnect-names = "dma-mem";
1906                         iommus = <&smmu TEGRA194_SID_HOST1X>;
1907                         dma-coherent;
1908
1909                         /* Context isolation domains */
1910                         iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1911                                     <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,
1912                                     <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,
1913                                     <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,
1914                                     <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,
1915                                     <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,
1916                                     <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,
1917                                     <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
1918
1919                         nvdec@15140000 {
1920                                 compatible = "nvidia,tegra194-nvdec";
1921                                 reg = <0x0 0x15140000 0x0 0x00040000>;
1922                                 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1923                                 clock-names = "nvdec";
1924                                 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1925                                 reset-names = "nvdec";
1926
1927                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1928                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
1929                                                 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
1930                                                 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
1931                                 interconnect-names = "dma-mem", "read-1", "write";
1932                                 iommus = <&smmu TEGRA194_SID_NVDEC1>;
1933                                 dma-coherent;
1934
1935                                 nvidia,host1x-class = <0xf5>;
1936                         };
1937
1938                         display-hub@15200000 {
1939                                 compatible = "nvidia,tegra194-display";
1940                                 reg = <0x0 0x15200000 0x0 0x00040000>;
1941                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1949                                               "wgrp3", "wgrp4", "wgrp5";
1950                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952                                 clock-names = "disp", "hub";
1953                                 status = "disabled";
1954
1955                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1956
1957                                 #address-cells = <2>;
1958                                 #size-cells = <2>;
1959                                 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>;
1960
1961                                 display@15200000 {
1962                                         compatible = "nvidia,tegra194-dc";
1963                                         reg = <0x0 0x15200000 0x0 0x10000>;
1964                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1965                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966                                         clock-names = "dc";
1967                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968                                         reset-names = "dc";
1969
1970                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1971                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1972                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1973                                         interconnect-names = "dma-mem", "read-1";
1974
1975                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1976                                         nvidia,head = <0>;
1977                                 };
1978
1979                                 display@15210000 {
1980                                         compatible = "nvidia,tegra194-dc";
1981                                         reg = <0x0 0x15210000 0x0 0x10000>;
1982                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1983                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984                                         clock-names = "dc";
1985                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986                                         reset-names = "dc";
1987
1988                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1989                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1990                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1991                                         interconnect-names = "dma-mem", "read-1";
1992
1993                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1994                                         nvidia,head = <1>;
1995                                 };
1996
1997                                 display@15220000 {
1998                                         compatible = "nvidia,tegra194-dc";
1999                                         reg = <0x0 0x15220000 0x0 0x10000>;
2000                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2001                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002                                         clock-names = "dc";
2003                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004                                         reset-names = "dc";
2005
2006                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2007                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2008                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2009                                         interconnect-names = "dma-mem", "read-1";
2010
2011                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2012                                         nvidia,head = <2>;
2013                                 };
2014
2015                                 display@15230000 {
2016                                         compatible = "nvidia,tegra194-dc";
2017                                         reg = <0x0 0x15230000 0x0 0x10000>;
2018                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
2019                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020                                         clock-names = "dc";
2021                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022                                         reset-names = "dc";
2023
2024                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2025                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
2026                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
2027                                         interconnect-names = "dma-mem", "read-1";
2028
2029                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
2030                                         nvidia,head = <3>;
2031                                 };
2032                         };
2033
2034                         vic@15340000 {
2035                                 compatible = "nvidia,tegra194-vic";
2036                                 reg = <0x0 0x15340000 0x0 0x00040000>;
2037                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2038                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039                                 clock-names = "vic";
2040                                 resets = <&bpmp TEGRA194_RESET_VIC>;
2041                                 reset-names = "vic";
2042
2043                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2044                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
2045                                                 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
2046                                 interconnect-names = "dma-mem", "write";
2047                                 iommus = <&smmu TEGRA194_SID_VIC>;
2048                                 dma-coherent;
2049                         };
2050
2051                         nvjpg@15380000 {
2052                                 compatible = "nvidia,tegra194-nvjpg";
2053                                 reg = <0x0 0x15380000 0x0 0x40000>;
2054                                 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2055                                 clock-names = "nvjpg";
2056                                 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2057                                 reset-names = "nvjpg";
2058
2059                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2060                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
2061                                                 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
2062                                 interconnect-names = "dma-mem", "write";
2063                                 iommus = <&smmu TEGRA194_SID_NVJPG>;
2064                                 dma-coherent;
2065                         };
2066
2067                         nvdec@15480000 {
2068                                 compatible = "nvidia,tegra194-nvdec";
2069                                 reg = <0x0 0x15480000 0x0 0x00040000>;
2070                                 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2071                                 clock-names = "nvdec";
2072                                 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2073                                 reset-names = "nvdec";
2074
2075                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2076                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
2077                                                 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
2078                                                 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
2079                                 interconnect-names = "dma-mem", "read-1", "write";
2080                                 iommus = <&smmu TEGRA194_SID_NVDEC>;
2081                                 dma-coherent;
2082
2083                                 nvidia,host1x-class = <0xf0>;
2084                         };
2085
2086                         nvenc@154c0000 {
2087                                 compatible = "nvidia,tegra194-nvenc";
2088                                 reg = <0x0 0x154c0000 0x0 0x40000>;
2089                                 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2090                                 clock-names = "nvenc";
2091                                 resets = <&bpmp TEGRA194_RESET_NVENC>;
2092                                 reset-names = "nvenc";
2093
2094                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2095                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
2096                                                 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
2097                                                 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
2098                                 interconnect-names = "dma-mem", "read-1", "write";
2099                                 iommus = <&smmu TEGRA194_SID_NVENC>;
2100                                 dma-coherent;
2101
2102                                 nvidia,host1x-class = <0x21>;
2103                         };
2104
2105                         dpaux0: dpaux@155c0000 {
2106                                 compatible = "nvidia,tegra194-dpaux";
2107                                 reg = <0x0 0x155c0000 0x0 0x10000>;
2108                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
2109                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110                                          <&bpmp TEGRA194_CLK_PLLDP>;
2111                                 clock-names = "dpaux", "parent";
2112                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113                                 reset-names = "dpaux";
2114                                 status = "disabled";
2115
2116                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2117
2118                                 state_dpaux0_aux: pinmux-aux {
2119                                         groups = "dpaux-io";
2120                                         function = "aux";
2121                                 };
2122
2123                                 state_dpaux0_i2c: pinmux-i2c {
2124                                         groups = "dpaux-io";
2125                                         function = "i2c";
2126                                 };
2127
2128                                 state_dpaux0_off: pinmux-off {
2129                                         groups = "dpaux-io";
2130                                         function = "off";
2131                                 };
2132
2133                                 i2c-bus {
2134                                         #address-cells = <1>;
2135                                         #size-cells = <0>;
2136                                 };
2137                         };
2138
2139                         dpaux1: dpaux@155d0000 {
2140                                 compatible = "nvidia,tegra194-dpaux";
2141                                 reg = <0x0 0x155d0000 0x0 0x10000>;
2142                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2143                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144                                          <&bpmp TEGRA194_CLK_PLLDP>;
2145                                 clock-names = "dpaux", "parent";
2146                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147                                 reset-names = "dpaux";
2148                                 status = "disabled";
2149
2150                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2151
2152                                 state_dpaux1_aux: pinmux-aux {
2153                                         groups = "dpaux-io";
2154                                         function = "aux";
2155                                 };
2156
2157                                 state_dpaux1_i2c: pinmux-i2c {
2158                                         groups = "dpaux-io";
2159                                         function = "i2c";
2160                                 };
2161
2162                                 state_dpaux1_off: pinmux-off {
2163                                         groups = "dpaux-io";
2164                                         function = "off";
2165                                 };
2166
2167                                 i2c-bus {
2168                                         #address-cells = <1>;
2169                                         #size-cells = <0>;
2170                                 };
2171                         };
2172
2173                         dpaux2: dpaux@155e0000 {
2174                                 compatible = "nvidia,tegra194-dpaux";
2175                                 reg = <0x0 0x155e0000 0x0 0x10000>;
2176                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
2177                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178                                          <&bpmp TEGRA194_CLK_PLLDP>;
2179                                 clock-names = "dpaux", "parent";
2180                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181                                 reset-names = "dpaux";
2182                                 status = "disabled";
2183
2184                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2185
2186                                 state_dpaux2_aux: pinmux-aux {
2187                                         groups = "dpaux-io";
2188                                         function = "aux";
2189                                 };
2190
2191                                 state_dpaux2_i2c: pinmux-i2c {
2192                                         groups = "dpaux-io";
2193                                         function = "i2c";
2194                                 };
2195
2196                                 state_dpaux2_off: pinmux-off {
2197                                         groups = "dpaux-io";
2198                                         function = "off";
2199                                 };
2200
2201                                 i2c-bus {
2202                                         #address-cells = <1>;
2203                                         #size-cells = <0>;
2204                                 };
2205                         };
2206
2207                         dpaux3: dpaux@155f0000 {
2208                                 compatible = "nvidia,tegra194-dpaux";
2209                                 reg = <0x0 0x155f0000 0x0 0x10000>;
2210                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
2211                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212                                          <&bpmp TEGRA194_CLK_PLLDP>;
2213                                 clock-names = "dpaux", "parent";
2214                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215                                 reset-names = "dpaux";
2216                                 status = "disabled";
2217
2218                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2219
2220                                 state_dpaux3_aux: pinmux-aux {
2221                                         groups = "dpaux-io";
2222                                         function = "aux";
2223                                 };
2224
2225                                 state_dpaux3_i2c: pinmux-i2c {
2226                                         groups = "dpaux-io";
2227                                         function = "i2c";
2228                                 };
2229
2230                                 state_dpaux3_off: pinmux-off {
2231                                         groups = "dpaux-io";
2232                                         function = "off";
2233                                 };
2234
2235                                 i2c-bus {
2236                                         #address-cells = <1>;
2237                                         #size-cells = <0>;
2238                                 };
2239                         };
2240
2241                         nvenc@15a80000 {
2242                                 compatible = "nvidia,tegra194-nvenc";
2243                                 reg = <0x0 0x15a80000 0x0 0x00040000>;
2244                                 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2245                                 clock-names = "nvenc";
2246                                 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2247                                 reset-names = "nvenc";
2248
2249                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2250                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
2251                                                 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
2252                                                 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
2253                                 interconnect-names = "dma-mem", "read-1", "write";
2254                                 iommus = <&smmu TEGRA194_SID_NVENC1>;
2255                                 dma-coherent;
2256
2257                                 nvidia,host1x-class = <0x22>;
2258                         };
2259
2260                         sor0: sor@15b00000 {
2261                                 compatible = "nvidia,tegra194-sor";
2262                                 reg = <0x0 0x15b00000 0x0 0x40000>;
2263                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
2264                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266                                          <&bpmp TEGRA194_CLK_PLLD>,
2267                                          <&bpmp TEGRA194_CLK_PLLDP>,
2268                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270                                 clock-names = "sor", "out", "parent", "dp", "safe",
2271                                               "pad";
2272                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273                                 reset-names = "sor";
2274                                 pinctrl-0 = <&state_dpaux0_aux>;
2275                                 pinctrl-1 = <&state_dpaux0_i2c>;
2276                                 pinctrl-2 = <&state_dpaux0_off>;
2277                                 pinctrl-names = "aux", "i2c", "off";
2278                                 status = "disabled";
2279
2280                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2281                                 nvidia,interface = <0>;
2282                         };
2283
2284                         sor1: sor@15b40000 {
2285                                 compatible = "nvidia,tegra194-sor";
2286                                 reg = <0x0 0x15b40000 0x0 0x40000>;
2287                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2288                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290                                          <&bpmp TEGRA194_CLK_PLLD2>,
2291                                          <&bpmp TEGRA194_CLK_PLLDP>,
2292                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294                                 clock-names = "sor", "out", "parent", "dp", "safe",
2295                                               "pad";
2296                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297                                 reset-names = "sor";
2298                                 pinctrl-0 = <&state_dpaux1_aux>;
2299                                 pinctrl-1 = <&state_dpaux1_i2c>;
2300                                 pinctrl-2 = <&state_dpaux1_off>;
2301                                 pinctrl-names = "aux", "i2c", "off";
2302                                 status = "disabled";
2303
2304                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2305                                 nvidia,interface = <1>;
2306                         };
2307
2308                         sor2: sor@15b80000 {
2309                                 compatible = "nvidia,tegra194-sor";
2310                                 reg = <0x0 0x15b80000 0x0 0x40000>;
2311                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2312                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314                                          <&bpmp TEGRA194_CLK_PLLD3>,
2315                                          <&bpmp TEGRA194_CLK_PLLDP>,
2316                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318                                 clock-names = "sor", "out", "parent", "dp", "safe",
2319                                               "pad";
2320                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321                                 reset-names = "sor";
2322                                 pinctrl-0 = <&state_dpaux2_aux>;
2323                                 pinctrl-1 = <&state_dpaux2_i2c>;
2324                                 pinctrl-2 = <&state_dpaux2_off>;
2325                                 pinctrl-names = "aux", "i2c", "off";
2326                                 status = "disabled";
2327
2328                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2329                                 nvidia,interface = <2>;
2330                         };
2331
2332                         sor3: sor@15bc0000 {
2333                                 compatible = "nvidia,tegra194-sor";
2334                                 reg = <0x0 0x15bc0000 0x0 0x40000>;
2335                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
2336                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338                                          <&bpmp TEGRA194_CLK_PLLD4>,
2339                                          <&bpmp TEGRA194_CLK_PLLDP>,
2340                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342                                 clock-names = "sor", "out", "parent", "dp", "safe",
2343                                               "pad";
2344                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345                                 reset-names = "sor";
2346                                 pinctrl-0 = <&state_dpaux3_aux>;
2347                                 pinctrl-1 = <&state_dpaux3_i2c>;
2348                                 pinctrl-2 = <&state_dpaux3_off>;
2349                                 pinctrl-names = "aux", "i2c", "off";
2350                                 status = "disabled";
2351
2352                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2353                                 nvidia,interface = <3>;
2354                         };
2355                 };
2356
2357                 pcie@14100000 {
2358                         compatible = "nvidia,tegra194-pcie";
2359                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2360                         reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
2361                               <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2362                               <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2363                               <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2364                         reg-names = "appl", "config", "atu_dma", "dbi";
2365
2366                         status = "disabled";
2367
2368                         #address-cells = <3>;
2369                         #size-cells = <2>;
2370                         device_type = "pci";
2371                         num-lanes = <1>;
2372                         linux,pci-domain = <1>;
2373
2374                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2375                         clock-names = "core";
2376
2377                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2378                                  <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2379                         reset-names = "apb", "core";
2380
2381                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2382                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2383                         interrupt-names = "intr", "msi";
2384
2385                         #interrupt-cells = <1>;
2386                         interrupt-map-mask = <0 0 0 0>;
2387                         interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2388
2389                         nvidia,bpmp = <&bpmp 1>;
2390
2391                         nvidia,aspm-cmrt-us = <60>;
2392                         nvidia,aspm-pwr-on-t-us = <20>;
2393                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2394
2395                         bus-range = <0x0 0xff>;
2396
2397                         ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2398                                  <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2399                                  <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2400
2401                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
2402                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
2403                         interconnect-names = "dma-mem", "write";
2404                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2405                         iommu-map-mask = <0x0>;
2406                         dma-coherent;
2407                 };
2408
2409                 pcie@14120000 {
2410                         compatible = "nvidia,tegra194-pcie";
2411                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2412                         reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
2413                               <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2414                               <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2415                               <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2416                         reg-names = "appl", "config", "atu_dma", "dbi";
2417
2418                         status = "disabled";
2419
2420                         #address-cells = <3>;
2421                         #size-cells = <2>;
2422                         device_type = "pci";
2423                         num-lanes = <1>;
2424                         linux,pci-domain = <2>;
2425
2426                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2427                         clock-names = "core";
2428
2429                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2430                                  <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2431                         reset-names = "apb", "core";
2432
2433                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2434                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2435                         interrupt-names = "intr", "msi";
2436
2437                         #interrupt-cells = <1>;
2438                         interrupt-map-mask = <0 0 0 0>;
2439                         interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2440
2441                         nvidia,bpmp = <&bpmp 2>;
2442
2443                         nvidia,aspm-cmrt-us = <60>;
2444                         nvidia,aspm-pwr-on-t-us = <20>;
2445                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2446
2447                         bus-range = <0x0 0xff>;
2448
2449                         ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2450                                  <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
2451                                  <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2452
2453                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
2454                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
2455                         interconnect-names = "dma-mem", "write";
2456                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2457                         iommu-map-mask = <0x0>;
2458                         dma-coherent;
2459                 };
2460
2461                 pcie@14140000 {
2462                         compatible = "nvidia,tegra194-pcie";
2463                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2464                         reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
2465                               <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2466                               <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2467                               <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2468                         reg-names = "appl", "config", "atu_dma", "dbi";
2469
2470                         status = "disabled";
2471
2472                         #address-cells = <3>;
2473                         #size-cells = <2>;
2474                         device_type = "pci";
2475                         num-lanes = <1>;
2476                         linux,pci-domain = <3>;
2477
2478                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2479                         clock-names = "core";
2480
2481                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2482                                  <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2483                         reset-names = "apb", "core";
2484
2485                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2486                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2487                         interrupt-names = "intr", "msi";
2488
2489                         #interrupt-cells = <1>;
2490                         interrupt-map-mask = <0 0 0 0>;
2491                         interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2492
2493                         nvidia,bpmp = <&bpmp 3>;
2494
2495                         nvidia,aspm-cmrt-us = <60>;
2496                         nvidia,aspm-pwr-on-t-us = <20>;
2497                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2498
2499                         bus-range = <0x0 0xff>;
2500
2501                         ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
2502                                  <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
2503                                  <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2504
2505                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
2506                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
2507                         interconnect-names = "dma-mem", "write";
2508                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2509                         iommu-map-mask = <0x0>;
2510                         dma-coherent;
2511                 };
2512
2513                 pcie@14160000 {
2514                         compatible = "nvidia,tegra194-pcie";
2515                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2516                         reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2517                               <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2518                               <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2519                               <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2520                         reg-names = "appl", "config", "atu_dma", "dbi";
2521
2522                         status = "disabled";
2523
2524                         #address-cells = <3>;
2525                         #size-cells = <2>;
2526                         device_type = "pci";
2527                         num-lanes = <4>;
2528                         linux,pci-domain = <4>;
2529
2530                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2531                         clock-names = "core";
2532
2533                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2534                                  <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2535                         reset-names = "apb", "core";
2536
2537                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2538                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2539                         interrupt-names = "intr", "msi";
2540
2541                         #interrupt-cells = <1>;
2542                         interrupt-map-mask = <0 0 0 0>;
2543                         interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2544
2545                         nvidia,bpmp = <&bpmp 4>;
2546
2547                         nvidia,aspm-cmrt-us = <60>;
2548                         nvidia,aspm-pwr-on-t-us = <20>;
2549                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2550
2551                         bus-range = <0x0 0xff>;
2552
2553                         ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2554                                  <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2555                                  <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2556
2557                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2558                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2559                         interconnect-names = "dma-mem", "write";
2560                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2561                         iommu-map-mask = <0x0>;
2562                         dma-coherent;
2563                 };
2564
2565                 pcie-ep@14160000 {
2566                         compatible = "nvidia,tegra194-pcie-ep";
2567                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2568                         reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
2569                               <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2570                               <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2571                               <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2572                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2573
2574                         status = "disabled";
2575
2576                         num-lanes = <4>;
2577                         num-ib-windows = <2>;
2578                         num-ob-windows = <8>;
2579
2580                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2581                         clock-names = "core";
2582
2583                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2584                                  <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2585                         reset-names = "apb", "core";
2586
2587                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2588                         interrupt-names = "intr";
2589
2590                         nvidia,bpmp = <&bpmp 4>;
2591
2592                         nvidia,aspm-cmrt-us = <60>;
2593                         nvidia,aspm-pwr-on-t-us = <20>;
2594                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2595
2596                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
2597                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
2598                         interconnect-names = "dma-mem", "write";
2599                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2600                         iommu-map-mask = <0x0>;
2601                         dma-coherent;
2602                 };
2603
2604                 pcie@14180000 {
2605                         compatible = "nvidia,tegra194-pcie";
2606                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2607                         reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2608                               <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2609                               <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2610                               <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2611                         reg-names = "appl", "config", "atu_dma", "dbi";
2612
2613                         status = "disabled";
2614
2615                         #address-cells = <3>;
2616                         #size-cells = <2>;
2617                         device_type = "pci";
2618                         num-lanes = <8>;
2619                         linux,pci-domain = <0>;
2620
2621                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2622                         clock-names = "core";
2623
2624                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2625                                  <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2626                         reset-names = "apb", "core";
2627
2628                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2629                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2630                         interrupt-names = "intr", "msi";
2631
2632                         #interrupt-cells = <1>;
2633                         interrupt-map-mask = <0 0 0 0>;
2634                         interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2635
2636                         nvidia,bpmp = <&bpmp 0>;
2637
2638                         nvidia,aspm-cmrt-us = <60>;
2639                         nvidia,aspm-pwr-on-t-us = <20>;
2640                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2641
2642                         bus-range = <0x0 0xff>;
2643
2644                         ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2645                                  <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2646                                  <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2647
2648                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2649                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2650                         interconnect-names = "dma-mem", "write";
2651                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2652                         iommu-map-mask = <0x0>;
2653                         dma-coherent;
2654                 };
2655
2656                 pcie-ep@14180000 {
2657                         compatible = "nvidia,tegra194-pcie-ep";
2658                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2659                         reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
2660                               <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2661                               <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2662                               <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2663                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2664
2665                         status = "disabled";
2666
2667                         num-lanes = <8>;
2668                         num-ib-windows = <2>;
2669                         num-ob-windows = <8>;
2670
2671                         clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2672                         clock-names = "core";
2673
2674                         resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2675                                  <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2676                         reset-names = "apb", "core";
2677
2678                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2679                         interrupt-names = "intr";
2680
2681                         nvidia,bpmp = <&bpmp 0>;
2682
2683                         nvidia,aspm-cmrt-us = <60>;
2684                         nvidia,aspm-pwr-on-t-us = <20>;
2685                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2686
2687                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
2688                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
2689                         interconnect-names = "dma-mem", "write";
2690                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2691                         iommu-map-mask = <0x0>;
2692                         dma-coherent;
2693                 };
2694
2695                 pcie@141a0000 {
2696                         compatible = "nvidia,tegra194-pcie";
2697                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2698                         reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2699                               <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2700                               <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2701                               <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
2702                         reg-names = "appl", "config", "atu_dma", "dbi";
2703
2704                         status = "disabled";
2705
2706                         #address-cells = <3>;
2707                         #size-cells = <2>;
2708                         device_type = "pci";
2709                         num-lanes = <8>;
2710                         linux,pci-domain = <5>;
2711
2712                         pinctrl-names = "default";
2713                         pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>;
2714
2715                         clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2716                         clock-names = "core";
2717
2718                         resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2719                                  <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2720                         reset-names = "apb", "core";
2721
2722                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2723                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2724                         interrupt-names = "intr", "msi";
2725
2726                         nvidia,bpmp = <&bpmp 5>;
2727
2728                         #interrupt-cells = <1>;
2729                         interrupt-map-mask = <0 0 0 0>;
2730                         interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2731
2732                         nvidia,aspm-cmrt-us = <60>;
2733                         nvidia,aspm-pwr-on-t-us = <20>;
2734                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2735
2736                         bus-range = <0x0 0xff>;
2737
2738                         ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
2739                                  <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
2740                                  <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
2741
2742                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2743                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2744                         interconnect-names = "dma-mem", "write";
2745                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2746                         iommu-map-mask = <0x0>;
2747                         dma-coherent;
2748                 };
2749
2750                 pcie-ep@141a0000 {
2751                         compatible = "nvidia,tegra194-pcie-ep";
2752                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2753                         reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
2754                               <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
2755                               <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
2756                               <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
2757                         reg-names = "appl", "atu_dma", "dbi", "addr_space";
2758
2759                         status = "disabled";
2760
2761                         num-lanes = <8>;
2762                         num-ib-windows = <2>;
2763                         num-ob-windows = <8>;
2764
2765                         pinctrl-names = "default";
2766                         pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>;
2767
2768                         clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2769                         clock-names = "core";
2770
2771                         resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2772                                  <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2773                         reset-names = "apb", "core";
2774
2775                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
2776                         interrupt-names = "intr";
2777
2778                         nvidia,bpmp = <&bpmp 5>;
2779
2780                         nvidia,aspm-cmrt-us = <60>;
2781                         nvidia,aspm-pwr-on-t-us = <20>;
2782                         nvidia,aspm-l0s-entrance-latency-us = <3>;
2783
2784                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
2785                                         <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
2786                         interconnect-names = "dma-mem", "write";
2787                         iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2788                         iommu-map-mask = <0x0>;
2789                         dma-coherent;
2790                 };
2791
2792                 gpu@17000000 {
2793                         compatible = "nvidia,gv11b";
2794                         reg = <0x0 0x17000000 0x0 0x1000000>,
2795                               <0x0 0x18000000 0x0 0x1000000>;
2796                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2797                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2798                         interrupt-names = "stall", "nonstall";
2799                         clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2800                                  <&bpmp TEGRA194_CLK_GPU_PWR>,
2801                                  <&bpmp TEGRA194_CLK_FUSE>;
2802                         clock-names = "gpu", "pwr", "fuse";
2803                         resets = <&bpmp TEGRA194_RESET_GPU>;
2804                         reset-names = "gpu";
2805                         dma-coherent;
2806
2807                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2808                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
2809                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
2810                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
2811                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
2812                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
2813                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
2814                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
2815                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
2816                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
2817                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
2818                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
2819                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
2820                         interconnect-names = "dma-mem", "read-0-hp", "write-0",
2821                                              "read-1", "read-1-hp", "write-1",
2822                                              "read-2", "read-2-hp", "write-2",
2823                                              "read-3", "read-3-hp", "write-3";
2824                 };
2825         };
2826
2827         sram@40000000 {
2828                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2829                 reg = <0x0 0x40000000 0x0 0x50000>;
2830
2831                 #address-cells = <1>;
2832                 #size-cells = <1>;
2833                 ranges = <0x0 0x0 0x40000000 0x50000>;
2834
2835                 no-memory-wc;
2836
2837                 cpu_bpmp_tx: sram@4e000 {
2838                         reg = <0x4e000 0x1000>;
2839                         label = "cpu-bpmp-tx";
2840                         pool;
2841                 };
2842
2843                 cpu_bpmp_rx: sram@4f000 {
2844                         reg = <0x4f000 0x1000>;
2845                         label = "cpu-bpmp-rx";
2846                         pool;
2847                 };
2848         };
2849
2850         bpmp: bpmp {
2851                 compatible = "nvidia,tegra186-bpmp";
2852                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2853                                     TEGRA_HSP_DB_MASTER_BPMP>;
2854                 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
2855                 #clock-cells = <1>;
2856                 #reset-cells = <1>;
2857                 #power-domain-cells = <1>;
2858                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
2859                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
2860                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
2861                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
2862                 interconnect-names = "read", "write", "dma-mem", "dma-write";
2863                 iommus = <&smmu TEGRA194_SID_BPMP>;
2864
2865                 bpmp_i2c: i2c {
2866                         compatible = "nvidia,tegra186-bpmp-i2c";
2867                         nvidia,bpmp-bus-id = <5>;
2868                         #address-cells = <1>;
2869                         #size-cells = <0>;
2870                 };
2871
2872                 bpmp_thermal: thermal {
2873                         compatible = "nvidia,tegra186-bpmp-thermal";
2874                         #thermal-sensor-cells = <1>;
2875                 };
2876         };
2877
2878         cpus {
2879                 compatible = "nvidia,tegra194-ccplex";
2880                 nvidia,bpmp = <&bpmp>;
2881                 #address-cells = <1>;
2882                 #size-cells = <0>;
2883
2884                 cpu0_0: cpu@0 {
2885                         compatible = "nvidia,tegra194-carmel";
2886                         device_type = "cpu";
2887                         reg = <0x000>;
2888                         enable-method = "psci";
2889                         i-cache-size = <131072>;
2890                         i-cache-line-size = <64>;
2891                         i-cache-sets = <512>;
2892                         d-cache-size = <65536>;
2893                         d-cache-line-size = <64>;
2894                         d-cache-sets = <256>;
2895                         next-level-cache = <&l2c_0>;
2896                 };
2897
2898                 cpu0_1: cpu@1 {
2899                         compatible = "nvidia,tegra194-carmel";
2900                         device_type = "cpu";
2901                         reg = <0x001>;
2902                         enable-method = "psci";
2903                         i-cache-size = <131072>;
2904                         i-cache-line-size = <64>;
2905                         i-cache-sets = <512>;
2906                         d-cache-size = <65536>;
2907                         d-cache-line-size = <64>;
2908                         d-cache-sets = <256>;
2909                         next-level-cache = <&l2c_0>;
2910                 };
2911
2912                 cpu1_0: cpu@100 {
2913                         compatible = "nvidia,tegra194-carmel";
2914                         device_type = "cpu";
2915                         reg = <0x100>;
2916                         enable-method = "psci";
2917                         i-cache-size = <131072>;
2918                         i-cache-line-size = <64>;
2919                         i-cache-sets = <512>;
2920                         d-cache-size = <65536>;
2921                         d-cache-line-size = <64>;
2922                         d-cache-sets = <256>;
2923                         next-level-cache = <&l2c_1>;
2924                 };
2925
2926                 cpu1_1: cpu@101 {
2927                         compatible = "nvidia,tegra194-carmel";
2928                         device_type = "cpu";
2929                         reg = <0x101>;
2930                         enable-method = "psci";
2931                         i-cache-size = <131072>;
2932                         i-cache-line-size = <64>;
2933                         i-cache-sets = <512>;
2934                         d-cache-size = <65536>;
2935                         d-cache-line-size = <64>;
2936                         d-cache-sets = <256>;
2937                         next-level-cache = <&l2c_1>;
2938                 };
2939
2940                 cpu2_0: cpu@200 {
2941                         compatible = "nvidia,tegra194-carmel";
2942                         device_type = "cpu";
2943                         reg = <0x200>;
2944                         enable-method = "psci";
2945                         i-cache-size = <131072>;
2946                         i-cache-line-size = <64>;
2947                         i-cache-sets = <512>;
2948                         d-cache-size = <65536>;
2949                         d-cache-line-size = <64>;
2950                         d-cache-sets = <256>;
2951                         next-level-cache = <&l2c_2>;
2952                 };
2953
2954                 cpu2_1: cpu@201 {
2955                         compatible = "nvidia,tegra194-carmel";
2956                         device_type = "cpu";
2957                         reg = <0x201>;
2958                         enable-method = "psci";
2959                         i-cache-size = <131072>;
2960                         i-cache-line-size = <64>;
2961                         i-cache-sets = <512>;
2962                         d-cache-size = <65536>;
2963                         d-cache-line-size = <64>;
2964                         d-cache-sets = <256>;
2965                         next-level-cache = <&l2c_2>;
2966                 };
2967
2968                 cpu3_0: cpu@300 {
2969                         compatible = "nvidia,tegra194-carmel";
2970                         device_type = "cpu";
2971                         reg = <0x300>;
2972                         enable-method = "psci";
2973                         i-cache-size = <131072>;
2974                         i-cache-line-size = <64>;
2975                         i-cache-sets = <512>;
2976                         d-cache-size = <65536>;
2977                         d-cache-line-size = <64>;
2978                         d-cache-sets = <256>;
2979                         next-level-cache = <&l2c_3>;
2980                 };
2981
2982                 cpu3_1: cpu@301 {
2983                         compatible = "nvidia,tegra194-carmel";
2984                         device_type = "cpu";
2985                         reg = <0x301>;
2986                         enable-method = "psci";
2987                         i-cache-size = <131072>;
2988                         i-cache-line-size = <64>;
2989                         i-cache-sets = <512>;
2990                         d-cache-size = <65536>;
2991                         d-cache-line-size = <64>;
2992                         d-cache-sets = <256>;
2993                         next-level-cache = <&l2c_3>;
2994                 };
2995
2996                 cpu-map {
2997                         cluster0 {
2998                                 core0 {
2999                                         cpu = <&cpu0_0>;
3000                                 };
3001
3002                                 core1 {
3003                                         cpu = <&cpu0_1>;
3004                                 };
3005                         };
3006
3007                         cluster1 {
3008                                 core0 {
3009                                         cpu = <&cpu1_0>;
3010                                 };
3011
3012                                 core1 {
3013                                         cpu = <&cpu1_1>;
3014                                 };
3015                         };
3016
3017                         cluster2 {
3018                                 core0 {
3019                                         cpu = <&cpu2_0>;
3020                                 };
3021
3022                                 core1 {
3023                                         cpu = <&cpu2_1>;
3024                                 };
3025                         };
3026
3027                         cluster3 {
3028                                 core0 {
3029                                         cpu = <&cpu3_0>;
3030                                 };
3031
3032                                 core1 {
3033                                         cpu = <&cpu3_1>;
3034                                 };
3035                         };
3036                 };
3037
3038                 l2c_0: l2-cache0 {
3039                         compatible = "cache";
3040                         cache-unified;
3041                         cache-size = <2097152>;
3042                         cache-line-size = <64>;
3043                         cache-sets = <2048>;
3044                         cache-level = <2>;
3045                         next-level-cache = <&l3c>;
3046                 };
3047
3048                 l2c_1: l2-cache1 {
3049                         compatible = "cache";
3050                         cache-unified;
3051                         cache-size = <2097152>;
3052                         cache-line-size = <64>;
3053                         cache-sets = <2048>;
3054                         cache-level = <2>;
3055                         next-level-cache = <&l3c>;
3056                 };
3057
3058                 l2c_2: l2-cache2 {
3059                         compatible = "cache";
3060                         cache-unified;
3061                         cache-size = <2097152>;
3062                         cache-line-size = <64>;
3063                         cache-sets = <2048>;
3064                         cache-level = <2>;
3065                         next-level-cache = <&l3c>;
3066                 };
3067
3068                 l2c_3: l2-cache3 {
3069                         compatible = "cache";
3070                         cache-unified;
3071                         cache-size = <2097152>;
3072                         cache-line-size = <64>;
3073                         cache-sets = <2048>;
3074                         cache-level = <2>;
3075                         next-level-cache = <&l3c>;
3076                 };
3077
3078                 l3c: l3-cache {
3079                         compatible = "cache";
3080                         cache-unified;
3081                         cache-size = <4194304>;
3082                         cache-line-size = <64>;
3083                         cache-level = <3>;
3084                         cache-sets = <4096>;
3085                 };
3086         };
3087
3088         pmu {
3089                 compatible = "nvidia,carmel-pmu";
3090                 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
3091                              <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
3092                              <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
3093                              <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
3094                              <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
3095                              <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
3096                              <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
3097                              <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
3098                 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3099                                       &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
3100         };
3101
3102         psci {
3103                 compatible = "arm,psci-1.0";
3104                 status = "okay";
3105                 method = "smc";
3106         };
3107
3108         tcu: serial {
3109                 compatible = "nvidia,tegra194-tcu";
3110                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3111                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3112                 mbox-names = "rx", "tx";
3113         };
3114
3115         sound {
3116                 status = "disabled";
3117
3118                 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119                          <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3120                 clock-names = "pll_a", "plla_out0";
3121                 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122                                   <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123                                   <&bpmp TEGRA194_CLK_AUD_MCLK>;
3124                 assigned-clock-parents = <0>,
3125                                          <&bpmp TEGRA194_CLK_PLLA>,
3126                                          <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3127                 /*
3128                  * PLLA supports dynamic ramp. Below initial rate is chosen
3129                  * for this to work and oscillate between base rates required
3130                  * for 8x and 11.025x sample rate streams.
3131                  */
3132                 assigned-clock-rates = <258000000>;
3133         };
3134
3135         thermal-zones {
3136                 cpu-thermal {
3137                         thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3138                         status = "disabled";
3139                 };
3140
3141                 gpu-thermal {
3142                         thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3143                         status = "disabled";
3144                 };
3145
3146                 aux-thermal {
3147                         thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3148                         status = "disabled";
3149                 };
3150
3151                 pllx-thermal {
3152                         thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3153                         status = "disabled";
3154                 };
3155
3156                 ao-thermal {
3157                         thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3158                         status = "disabled";
3159                 };
3160
3161                 tj-thermal {
3162                         thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3163                         status = "disabled";
3164                 };
3165         };
3166
3167         timer {
3168                 compatible = "arm,armv8-timer";
3169                 interrupts = <GIC_PPI 13
3170                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3171                              <GIC_PPI 14
3172                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3173                              <GIC_PPI 11
3174                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3175                              <GIC_PPI 10
3176                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3177                 interrupt-parent = <&gic>;
3178                 always-on;
3179         };
3180 };