1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65 interconnect-names = "dma-mem", "write";
66 iommus = <&smmu TEGRA186_SID_EQOS>;
69 snps,write-requests = <1>;
70 snps,read-requests = <3>;
71 snps,burst-map = <0x7>;
76 gpcdma: dma-controller@2600000 {
77 compatible = "nvidia,tegra186-gpcdma";
78 reg = <0x0 0x2600000 0x0 0x210000>;
79 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
80 reset-names = "gpcdma";
81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
116 dma-channel-mask = <0xfffffffe>;
121 compatible = "nvidia,tegra186-aconnect",
122 "nvidia,tegra210-aconnect";
123 clocks = <&bpmp TEGRA186_CLK_APE>,
124 <&bpmp TEGRA186_CLK_APB2APE>;
125 clock-names = "ape", "apb2ape";
126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
127 #address-cells = <1>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
132 tegra_ahub: ahub@2900800 {
133 compatible = "nvidia,tegra186-ahub";
134 reg = <0x02900800 0x800>;
135 clocks = <&bpmp TEGRA186_CLK_AHUB>;
136 clock-names = "ahub";
137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
139 assigned-clock-rates = <81600000>;
140 #address-cells = <1>;
142 ranges = <0x02900800 0x02900800 0x11800>;
145 tegra_i2s1: i2s@2901000 {
146 compatible = "nvidia,tegra186-i2s",
147 "nvidia,tegra210-i2s";
148 reg = <0x2901000 0x100>;
149 clocks = <&bpmp TEGRA186_CLK_I2S1>,
150 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
151 clock-names = "i2s", "sync_input";
152 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
154 assigned-clock-rates = <1536000>;
155 sound-name-prefix = "I2S1";
159 tegra_i2s2: i2s@2901100 {
160 compatible = "nvidia,tegra186-i2s",
161 "nvidia,tegra210-i2s";
162 reg = <0x2901100 0x100>;
163 clocks = <&bpmp TEGRA186_CLK_I2S2>,
164 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
165 clock-names = "i2s", "sync_input";
166 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
168 assigned-clock-rates = <1536000>;
169 sound-name-prefix = "I2S2";
173 tegra_i2s3: i2s@2901200 {
174 compatible = "nvidia,tegra186-i2s",
175 "nvidia,tegra210-i2s";
176 reg = <0x2901200 0x100>;
177 clocks = <&bpmp TEGRA186_CLK_I2S3>,
178 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
179 clock-names = "i2s", "sync_input";
180 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
182 assigned-clock-rates = <1536000>;
183 sound-name-prefix = "I2S3";
187 tegra_i2s4: i2s@2901300 {
188 compatible = "nvidia,tegra186-i2s",
189 "nvidia,tegra210-i2s";
190 reg = <0x2901300 0x100>;
191 clocks = <&bpmp TEGRA186_CLK_I2S4>,
192 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
193 clock-names = "i2s", "sync_input";
194 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
196 assigned-clock-rates = <1536000>;
197 sound-name-prefix = "I2S4";
201 tegra_i2s5: i2s@2901400 {
202 compatible = "nvidia,tegra186-i2s",
203 "nvidia,tegra210-i2s";
204 reg = <0x2901400 0x100>;
205 clocks = <&bpmp TEGRA186_CLK_I2S5>,
206 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
207 clock-names = "i2s", "sync_input";
208 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
210 assigned-clock-rates = <1536000>;
211 sound-name-prefix = "I2S5";
215 tegra_i2s6: i2s@2901500 {
216 compatible = "nvidia,tegra186-i2s",
217 "nvidia,tegra210-i2s";
218 reg = <0x2901500 0x100>;
219 clocks = <&bpmp TEGRA186_CLK_I2S6>,
220 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
221 clock-names = "i2s", "sync_input";
222 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
224 assigned-clock-rates = <1536000>;
225 sound-name-prefix = "I2S6";
229 tegra_sfc1: sfc@2902000 {
230 compatible = "nvidia,tegra186-sfc",
231 "nvidia,tegra210-sfc";
232 reg = <0x2902000 0x200>;
233 sound-name-prefix = "SFC1";
237 tegra_sfc2: sfc@2902200 {
238 compatible = "nvidia,tegra186-sfc",
239 "nvidia,tegra210-sfc";
240 reg = <0x2902200 0x200>;
241 sound-name-prefix = "SFC2";
245 tegra_sfc3: sfc@2902400 {
246 compatible = "nvidia,tegra186-sfc",
247 "nvidia,tegra210-sfc";
248 reg = <0x2902400 0x200>;
249 sound-name-prefix = "SFC3";
253 tegra_sfc4: sfc@2902600 {
254 compatible = "nvidia,tegra186-sfc",
255 "nvidia,tegra210-sfc";
256 reg = <0x2902600 0x200>;
257 sound-name-prefix = "SFC4";
261 tegra_amx1: amx@2903000 {
262 compatible = "nvidia,tegra186-amx",
263 "nvidia,tegra210-amx";
264 reg = <0x2903000 0x100>;
265 sound-name-prefix = "AMX1";
269 tegra_amx2: amx@2903100 {
270 compatible = "nvidia,tegra186-amx",
271 "nvidia,tegra210-amx";
272 reg = <0x2903100 0x100>;
273 sound-name-prefix = "AMX2";
277 tegra_amx3: amx@2903200 {
278 compatible = "nvidia,tegra186-amx",
279 "nvidia,tegra210-amx";
280 reg = <0x2903200 0x100>;
281 sound-name-prefix = "AMX3";
285 tegra_amx4: amx@2903300 {
286 compatible = "nvidia,tegra186-amx",
287 "nvidia,tegra210-amx";
288 reg = <0x2903300 0x100>;
289 sound-name-prefix = "AMX4";
293 tegra_adx1: adx@2903800 {
294 compatible = "nvidia,tegra186-adx",
295 "nvidia,tegra210-adx";
296 reg = <0x2903800 0x100>;
297 sound-name-prefix = "ADX1";
301 tegra_adx2: adx@2903900 {
302 compatible = "nvidia,tegra186-adx",
303 "nvidia,tegra210-adx";
304 reg = <0x2903900 0x100>;
305 sound-name-prefix = "ADX2";
309 tegra_adx3: adx@2903a00 {
310 compatible = "nvidia,tegra186-adx",
311 "nvidia,tegra210-adx";
312 reg = <0x2903a00 0x100>;
313 sound-name-prefix = "ADX3";
317 tegra_adx4: adx@2903b00 {
318 compatible = "nvidia,tegra186-adx",
319 "nvidia,tegra210-adx";
320 reg = <0x2903b00 0x100>;
321 sound-name-prefix = "ADX4";
325 tegra_dmic1: dmic@2904000 {
326 compatible = "nvidia,tegra210-dmic";
327 reg = <0x2904000 0x100>;
328 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
329 clock-names = "dmic";
330 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
332 assigned-clock-rates = <3072000>;
333 sound-name-prefix = "DMIC1";
337 tegra_dmic2: dmic@2904100 {
338 compatible = "nvidia,tegra210-dmic";
339 reg = <0x2904100 0x100>;
340 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
341 clock-names = "dmic";
342 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
344 assigned-clock-rates = <3072000>;
345 sound-name-prefix = "DMIC2";
349 tegra_dmic3: dmic@2904200 {
350 compatible = "nvidia,tegra210-dmic";
351 reg = <0x2904200 0x100>;
352 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
353 clock-names = "dmic";
354 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
356 assigned-clock-rates = <3072000>;
357 sound-name-prefix = "DMIC3";
361 tegra_dmic4: dmic@2904300 {
362 compatible = "nvidia,tegra210-dmic";
363 reg = <0x2904300 0x100>;
364 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
365 clock-names = "dmic";
366 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
368 assigned-clock-rates = <3072000>;
369 sound-name-prefix = "DMIC4";
373 tegra_dspk1: dspk@2905000 {
374 compatible = "nvidia,tegra186-dspk";
375 reg = <0x2905000 0x100>;
376 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
377 clock-names = "dspk";
378 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
380 assigned-clock-rates = <12288000>;
381 sound-name-prefix = "DSPK1";
385 tegra_dspk2: dspk@2905100 {
386 compatible = "nvidia,tegra186-dspk";
387 reg = <0x2905100 0x100>;
388 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
389 clock-names = "dspk";
390 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
392 assigned-clock-rates = <12288000>;
393 sound-name-prefix = "DSPK2";
397 tegra_ope1: processing-engine@2908000 {
398 compatible = "nvidia,tegra186-ope",
399 "nvidia,tegra210-ope";
400 reg = <0x2908000 0x100>;
401 #address-cells = <1>;
404 sound-name-prefix = "OPE1";
408 compatible = "nvidia,tegra186-peq",
409 "nvidia,tegra210-peq";
410 reg = <0x2908100 0x100>;
413 dynamic-range-compressor@2908200 {
414 compatible = "nvidia,tegra186-mbdrc",
415 "nvidia,tegra210-mbdrc";
416 reg = <0x2908200 0x200>;
420 tegra_mvc1: mvc@290a000 {
421 compatible = "nvidia,tegra186-mvc",
422 "nvidia,tegra210-mvc";
423 reg = <0x290a000 0x200>;
424 sound-name-prefix = "MVC1";
428 tegra_mvc2: mvc@290a200 {
429 compatible = "nvidia,tegra186-mvc",
430 "nvidia,tegra210-mvc";
431 reg = <0x290a200 0x200>;
432 sound-name-prefix = "MVC2";
436 tegra_amixer: amixer@290bb00 {
437 compatible = "nvidia,tegra186-amixer",
438 "nvidia,tegra210-amixer";
439 reg = <0x290bb00 0x800>;
440 sound-name-prefix = "MIXER1";
444 tegra_admaif: admaif@290f000 {
445 compatible = "nvidia,tegra186-admaif";
446 reg = <0x0290f000 0x1000>;
447 dmas = <&adma 1>, <&adma 1>,
448 <&adma 2>, <&adma 2>,
449 <&adma 3>, <&adma 3>,
450 <&adma 4>, <&adma 4>,
451 <&adma 5>, <&adma 5>,
452 <&adma 6>, <&adma 6>,
453 <&adma 7>, <&adma 7>,
454 <&adma 8>, <&adma 8>,
455 <&adma 9>, <&adma 9>,
456 <&adma 10>, <&adma 10>,
457 <&adma 11>, <&adma 11>,
458 <&adma 12>, <&adma 12>,
459 <&adma 13>, <&adma 13>,
460 <&adma 14>, <&adma 14>,
461 <&adma 15>, <&adma 15>,
462 <&adma 16>, <&adma 16>,
463 <&adma 17>, <&adma 17>,
464 <&adma 18>, <&adma 18>,
465 <&adma 19>, <&adma 19>,
466 <&adma 20>, <&adma 20>;
467 dma-names = "rx1", "tx1",
490 tegra_asrc: asrc@2910000 {
491 compatible = "nvidia,tegra186-asrc";
492 reg = <0x2910000 0x2000>;
493 sound-name-prefix = "ASRC1";
498 adma: dma-controller@2930000 {
499 compatible = "nvidia,tegra186-adma";
500 reg = <0x02930000 0x20000>;
501 interrupt-parent = <&agic>;
502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&bpmp TEGRA186_CLK_AHUB>;
536 clock-names = "d_audio";
540 agic: interrupt-controller@2a40000 {
541 compatible = "nvidia,tegra186-agic",
542 "nvidia,tegra210-agic";
543 #interrupt-cells = <3>;
544 interrupt-controller;
545 reg = <0x02a41000 0x1000>,
547 interrupts = <GIC_SPI 145
548 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
549 clocks = <&bpmp TEGRA186_CLK_APE>;
555 mc: memory-controller@2c00000 {
556 compatible = "nvidia,tegra186-mc";
557 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
558 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
559 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
560 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
561 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
562 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
563 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
564 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
567 #interconnect-cells = <1>;
568 #address-cells = <2>;
571 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
574 * Memory clients have access to all 40 bits that the memory
575 * controller can address.
577 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
579 emc: external-memory-controller@2c60000 {
580 compatible = "nvidia,tegra186-emc";
581 reg = <0x0 0x02c60000 0x0 0x50000>;
582 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&bpmp TEGRA186_CLK_EMC>;
586 #interconnect-cells = <0>;
588 nvidia,bpmp = <&bpmp>;
593 compatible = "nvidia,tegra186-timer";
594 reg = <0x0 0x03010000 0x0 0x000e0000>;
595 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
608 uarta: serial@3100000 {
609 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
610 reg = <0x0 0x03100000 0x0 0x40>;
612 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&bpmp TEGRA186_CLK_UARTA>;
614 resets = <&bpmp TEGRA186_RESET_UARTA>;
618 uartb: serial@3110000 {
619 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
620 reg = <0x0 0x03110000 0x0 0x40>;
622 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&bpmp TEGRA186_CLK_UARTB>;
624 clock-names = "serial";
625 resets = <&bpmp TEGRA186_RESET_UARTB>;
626 reset-names = "serial";
630 uartd: serial@3130000 {
631 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
632 reg = <0x0 0x03130000 0x0 0x40>;
634 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&bpmp TEGRA186_CLK_UARTD>;
636 clock-names = "serial";
637 resets = <&bpmp TEGRA186_RESET_UARTD>;
638 reset-names = "serial";
642 uarte: serial@3140000 {
643 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
644 reg = <0x0 0x03140000 0x0 0x40>;
646 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&bpmp TEGRA186_CLK_UARTE>;
648 clock-names = "serial";
649 resets = <&bpmp TEGRA186_RESET_UARTE>;
650 reset-names = "serial";
654 uartf: serial@3150000 {
655 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
656 reg = <0x0 0x03150000 0x0 0x40>;
658 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&bpmp TEGRA186_CLK_UARTF>;
660 clock-names = "serial";
661 resets = <&bpmp TEGRA186_RESET_UARTF>;
662 reset-names = "serial";
666 gen1_i2c: i2c@3160000 {
667 compatible = "nvidia,tegra186-i2c";
668 reg = <0x0 0x03160000 0x0 0x10000>;
669 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
670 #address-cells = <1>;
672 clocks = <&bpmp TEGRA186_CLK_I2C1>;
673 clock-names = "div-clk";
674 resets = <&bpmp TEGRA186_RESET_I2C1>;
676 dmas = <&gpcdma 21>, <&gpcdma 21>;
677 dma-names = "rx", "tx";
681 cam_i2c: i2c@3180000 {
682 compatible = "nvidia,tegra186-i2c";
683 reg = <0x0 0x03180000 0x0 0x10000>;
684 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
687 clocks = <&bpmp TEGRA186_CLK_I2C3>;
688 clock-names = "div-clk";
689 resets = <&bpmp TEGRA186_RESET_I2C3>;
691 dmas = <&gpcdma 23>, <&gpcdma 23>;
692 dma-names = "rx", "tx";
696 /* shares pads with dpaux1 */
697 dp_aux_ch1_i2c: i2c@3190000 {
698 compatible = "nvidia,tegra186-i2c";
699 reg = <0x0 0x03190000 0x0 0x10000>;
700 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
701 #address-cells = <1>;
703 clocks = <&bpmp TEGRA186_CLK_I2C4>;
704 clock-names = "div-clk";
705 resets = <&bpmp TEGRA186_RESET_I2C4>;
707 pinctrl-names = "default", "idle";
708 pinctrl-0 = <&state_dpaux1_i2c>;
709 pinctrl-1 = <&state_dpaux1_off>;
710 dmas = <&gpcdma 26>, <&gpcdma 26>;
711 dma-names = "rx", "tx";
715 /* controlled by BPMP, should not be enabled */
716 pwr_i2c: i2c@31a0000 {
717 compatible = "nvidia,tegra186-i2c";
718 reg = <0x0 0x031a0000 0x0 0x10000>;
719 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
720 #address-cells = <1>;
722 clocks = <&bpmp TEGRA186_CLK_I2C5>;
723 clock-names = "div-clk";
724 resets = <&bpmp TEGRA186_RESET_I2C5>;
729 /* shares pads with dpaux0 */
730 dp_aux_ch0_i2c: i2c@31b0000 {
731 compatible = "nvidia,tegra186-i2c";
732 reg = <0x0 0x031b0000 0x0 0x10000>;
733 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
734 #address-cells = <1>;
736 clocks = <&bpmp TEGRA186_CLK_I2C6>;
737 clock-names = "div-clk";
738 resets = <&bpmp TEGRA186_RESET_I2C6>;
740 pinctrl-names = "default", "idle";
741 pinctrl-0 = <&state_dpaux_i2c>;
742 pinctrl-1 = <&state_dpaux_off>;
743 dmas = <&gpcdma 30>, <&gpcdma 30>;
744 dma-names = "rx", "tx";
748 gen7_i2c: i2c@31c0000 {
749 compatible = "nvidia,tegra186-i2c";
750 reg = <0x0 0x031c0000 0x0 0x10000>;
751 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
752 #address-cells = <1>;
754 clocks = <&bpmp TEGRA186_CLK_I2C7>;
755 clock-names = "div-clk";
756 resets = <&bpmp TEGRA186_RESET_I2C7>;
758 dmas = <&gpcdma 27>, <&gpcdma 27>;
759 dma-names = "rx", "tx";
763 gen9_i2c: i2c@31e0000 {
764 compatible = "nvidia,tegra186-i2c";
765 reg = <0x0 0x031e0000 0x0 0x10000>;
766 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
769 clocks = <&bpmp TEGRA186_CLK_I2C9>;
770 clock-names = "div-clk";
771 resets = <&bpmp TEGRA186_RESET_I2C9>;
773 dmas = <&gpcdma 31>, <&gpcdma 31>;
774 dma-names = "rx", "tx";
779 compatible = "nvidia,tegra186-pwm";
780 reg = <0x0 0x3280000 0x0 0x10000>;
781 clocks = <&bpmp TEGRA186_CLK_PWM1>;
782 resets = <&bpmp TEGRA186_RESET_PWM1>;
789 compatible = "nvidia,tegra186-pwm";
790 reg = <0x0 0x3290000 0x0 0x10000>;
791 clocks = <&bpmp TEGRA186_CLK_PWM2>;
792 resets = <&bpmp TEGRA186_RESET_PWM2>;
799 compatible = "nvidia,tegra186-pwm";
800 reg = <0x0 0x32a0000 0x0 0x10000>;
801 clocks = <&bpmp TEGRA186_CLK_PWM3>;
802 resets = <&bpmp TEGRA186_RESET_PWM3>;
809 compatible = "nvidia,tegra186-pwm";
810 reg = <0x0 0x32c0000 0x0 0x10000>;
811 clocks = <&bpmp TEGRA186_CLK_PWM5>;
812 resets = <&bpmp TEGRA186_RESET_PWM5>;
819 compatible = "nvidia,tegra186-pwm";
820 reg = <0x0 0x32d0000 0x0 0x10000>;
821 clocks = <&bpmp TEGRA186_CLK_PWM6>;
822 resets = <&bpmp TEGRA186_RESET_PWM6>;
829 compatible = "nvidia,tegra186-pwm";
830 reg = <0x0 0x32e0000 0x0 0x10000>;
831 clocks = <&bpmp TEGRA186_CLK_PWM7>;
832 resets = <&bpmp TEGRA186_RESET_PWM7>;
839 compatible = "nvidia,tegra186-pwm";
840 reg = <0x0 0x32f0000 0x0 0x10000>;
841 clocks = <&bpmp TEGRA186_CLK_PWM8>;
842 resets = <&bpmp TEGRA186_RESET_PWM8>;
848 sdmmc1: mmc@3400000 {
849 compatible = "nvidia,tegra186-sdhci";
850 reg = <0x0 0x03400000 0x0 0x10000>;
851 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
853 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
854 clock-names = "sdhci", "tmclk";
855 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
856 reset-names = "sdhci";
857 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
858 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
859 interconnect-names = "dma-mem", "write";
860 iommus = <&smmu TEGRA186_SID_SDMMC1>;
861 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
862 pinctrl-0 = <&sdmmc1_3v3>;
863 pinctrl-1 = <&sdmmc1_1v8>;
864 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
865 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
866 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
867 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
868 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
869 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
870 nvidia,default-tap = <0x5>;
871 nvidia,default-trim = <0xb>;
872 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
873 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
874 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
878 sdmmc2: mmc@3420000 {
879 compatible = "nvidia,tegra186-sdhci";
880 reg = <0x0 0x03420000 0x0 0x10000>;
881 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
883 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
884 clock-names = "sdhci", "tmclk";
885 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
886 reset-names = "sdhci";
887 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
888 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
889 interconnect-names = "dma-mem", "write";
890 iommus = <&smmu TEGRA186_SID_SDMMC2>;
891 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
892 pinctrl-0 = <&sdmmc2_3v3>;
893 pinctrl-1 = <&sdmmc2_1v8>;
894 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
895 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
896 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
897 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
898 nvidia,default-tap = <0x5>;
899 nvidia,default-trim = <0xb>;
903 sdmmc3: mmc@3440000 {
904 compatible = "nvidia,tegra186-sdhci";
905 reg = <0x0 0x03440000 0x0 0x10000>;
906 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
908 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
909 clock-names = "sdhci", "tmclk";
910 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
911 reset-names = "sdhci";
912 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
913 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
914 interconnect-names = "dma-mem", "write";
915 iommus = <&smmu TEGRA186_SID_SDMMC3>;
916 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
917 pinctrl-0 = <&sdmmc3_3v3>;
918 pinctrl-1 = <&sdmmc3_1v8>;
919 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
920 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
921 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
922 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
923 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
924 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
925 nvidia,default-tap = <0x5>;
926 nvidia,default-trim = <0xb>;
930 sdmmc4: mmc@3460000 {
931 compatible = "nvidia,tegra186-sdhci";
932 reg = <0x0 0x03460000 0x0 0x10000>;
933 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
935 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
936 clock-names = "sdhci", "tmclk";
937 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
938 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
939 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
940 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
941 reset-names = "sdhci";
942 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
943 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
944 interconnect-names = "dma-mem", "write";
945 iommus = <&smmu TEGRA186_SID_SDMMC4>;
946 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
947 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
948 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
949 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
950 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
951 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
952 nvidia,default-tap = <0x9>;
953 nvidia,default-trim = <0x5>;
954 nvidia,dqs-trim = <63>;
961 compatible = "nvidia,tegra186-ahci";
962 reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */
963 <0x0 0x03500000 0x0 0x00007000>, /* SATA */
964 <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */
965 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
967 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
968 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>,
969 <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>;
970 interconnect-names = "dma-mem", "write";
971 iommus = <&smmu TEGRA186_SID_SATA>;
973 clocks = <&bpmp TEGRA186_CLK_SATA>,
974 <&bpmp TEGRA186_CLK_SATA_OOB>;
975 clock-names = "sata", "sata-oob";
976 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
977 <&bpmp TEGRA186_CLK_SATA_OOB>;
978 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
979 <&bpmp TEGRA186_CLK_PLLP>;
980 assigned-clock-rates = <102000000>,
982 resets = <&bpmp TEGRA186_RESET_SATA>,
983 <&bpmp TEGRA186_RESET_SATACOLD>;
984 reset-names = "sata", "sata-cold";
989 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
990 reg = <0x0 0x03510000 0x0 0x10000>;
991 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
992 clocks = <&bpmp TEGRA186_CLK_HDA>,
993 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
994 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
995 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
996 resets = <&bpmp TEGRA186_RESET_HDA>,
997 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
998 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
999 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1001 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
1002 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
1003 interconnect-names = "dma-mem", "write";
1004 iommus = <&smmu TEGRA186_SID_HDA>;
1005 status = "disabled";
1008 padctl: padctl@3520000 {
1009 compatible = "nvidia,tegra186-xusb-padctl";
1010 reg = <0x0 0x03520000 0x0 0x1000>,
1011 <0x0 0x03540000 0x0 0x1000>;
1012 reg-names = "padctl", "ao";
1013 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1015 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1016 reset-names = "padctl";
1018 status = "disabled";
1022 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1023 clock-names = "trk";
1024 status = "disabled";
1028 status = "disabled";
1033 status = "disabled";
1038 status = "disabled";
1045 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1046 clock-names = "trk";
1047 status = "disabled";
1051 status = "disabled";
1058 status = "disabled";
1062 status = "disabled";
1067 status = "disabled";
1072 status = "disabled";
1081 status = "disabled";
1085 status = "disabled";
1089 status = "disabled";
1093 status = "disabled";
1097 status = "disabled";
1101 status = "disabled";
1105 status = "disabled";
1111 compatible = "nvidia,tegra186-xusb";
1112 reg = <0x0 0x03530000 0x0 0x8000>,
1113 <0x0 0x03538000 0x0 0x1000>;
1114 reg-names = "hcd", "fpci";
1115 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1118 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1119 <&bpmp TEGRA186_CLK_XUSB_SS>,
1120 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1121 <&bpmp TEGRA186_CLK_CLK_M>,
1122 <&bpmp TEGRA186_CLK_XUSB_FS>,
1123 <&bpmp TEGRA186_CLK_PLLU>,
1124 <&bpmp TEGRA186_CLK_CLK_M>,
1125 <&bpmp TEGRA186_CLK_PLLE>;
1126 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
1127 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
1128 "pll_u_480m", "clk_m", "pll_e";
1129 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1130 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1131 power-domain-names = "xusb_host", "xusb_ss";
1132 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1133 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1134 interconnect-names = "dma-mem", "write";
1135 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1136 #address-cells = <1>;
1138 status = "disabled";
1140 nvidia,xusb-padctl = <&padctl>;
1144 compatible = "nvidia,tegra186-xudc";
1145 reg = <0x0 0x03550000 0x0 0x8000>,
1146 <0x0 0x03558000 0x0 0x1000>;
1147 reg-names = "base", "fpci";
1148 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1150 <&bpmp TEGRA186_CLK_XUSB_SS>,
1151 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1152 <&bpmp TEGRA186_CLK_XUSB_FS>;
1153 clock-names = "dev", "ss", "ss_src", "fs_src";
1154 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVR &emc>,
1155 <&mc TEGRA186_MEMORY_CLIENT_XUSB_DEVW &emc>;
1156 interconnect-names = "dma-mem", "write";
1157 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
1158 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1159 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1160 power-domain-names = "dev", "ss";
1161 nvidia,xusb-padctl = <&padctl>;
1162 status = "disabled";
1166 compatible = "nvidia,tegra186-efuse";
1167 reg = <0x0 0x03820000 0x0 0x10000>;
1168 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1169 clock-names = "fuse";
1172 gic: interrupt-controller@3881000 {
1173 compatible = "arm,gic-400";
1174 #interrupt-cells = <3>;
1175 interrupt-controller;
1176 reg = <0x0 0x03881000 0x0 0x1000>,
1177 <0x0 0x03882000 0x0 0x2000>,
1178 <0x0 0x03884000 0x0 0x2000>,
1179 <0x0 0x03886000 0x0 0x2000>;
1180 interrupts = <GIC_PPI 9
1181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1182 interrupt-parent = <&gic>;
1186 compatible = "nvidia,tegra186-cec";
1187 reg = <0x0 0x03960000 0x0 0x10000>;
1188 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1189 clocks = <&bpmp TEGRA186_CLK_CEC>;
1190 clock-names = "cec";
1191 status = "disabled";
1194 hsp_top0: hsp@3c00000 {
1195 compatible = "nvidia,tegra186-hsp";
1196 reg = <0x0 0x03c00000 0x0 0xa0000>;
1197 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
1198 interrupt-names = "doorbell";
1200 status = "disabled";
1203 gen2_i2c: i2c@c240000 {
1204 compatible = "nvidia,tegra186-i2c";
1205 reg = <0x0 0x0c240000 0x0 0x10000>;
1206 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1207 #address-cells = <1>;
1209 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1210 clock-names = "div-clk";
1211 resets = <&bpmp TEGRA186_RESET_I2C2>;
1212 reset-names = "i2c";
1213 dmas = <&gpcdma 22>, <&gpcdma 22>;
1214 dma-names = "rx", "tx";
1215 status = "disabled";
1218 gen8_i2c: i2c@c250000 {
1219 compatible = "nvidia,tegra186-i2c";
1220 reg = <0x0 0x0c250000 0x0 0x10000>;
1221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1222 #address-cells = <1>;
1224 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1225 clock-names = "div-clk";
1226 resets = <&bpmp TEGRA186_RESET_I2C8>;
1227 reset-names = "i2c";
1228 dmas = <&gpcdma 0>, <&gpcdma 0>;
1229 dma-names = "rx", "tx";
1230 status = "disabled";
1233 uartc: serial@c280000 {
1234 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1235 reg = <0x0 0x0c280000 0x0 0x40>;
1237 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1239 clock-names = "serial";
1240 resets = <&bpmp TEGRA186_RESET_UARTC>;
1241 reset-names = "serial";
1242 status = "disabled";
1245 uartg: serial@c290000 {
1246 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
1247 reg = <0x0 0x0c290000 0x0 0x40>;
1249 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1251 clock-names = "serial";
1252 resets = <&bpmp TEGRA186_RESET_UARTG>;
1253 reset-names = "serial";
1254 status = "disabled";
1258 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
1259 reg = <0 0x0c2a0000 0 0x10000>;
1260 interrupt-parent = <&pmc>;
1261 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1263 clock-names = "rtc";
1264 status = "disabled";
1267 gpio_aon: gpio@c2f0000 {
1268 compatible = "nvidia,tegra186-gpio-aon";
1269 reg-names = "security", "gpio";
1270 reg = <0x0 0xc2f0000 0x0 0x1000>,
1271 <0x0 0xc2f1000 0x0 0x1000>;
1272 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1275 interrupt-controller;
1276 #interrupt-cells = <2>;
1280 compatible = "nvidia,tegra186-pwm";
1281 reg = <0x0 0xc340000 0x0 0x10000>;
1282 clocks = <&bpmp TEGRA186_CLK_PWM4>;
1283 resets = <&bpmp TEGRA186_RESET_PWM4>;
1284 reset-names = "pwm";
1285 status = "disabled";
1290 compatible = "nvidia,tegra186-pmc";
1291 reg = <0 0x0c360000 0 0x10000>,
1292 <0 0x0c370000 0 0x10000>,
1293 <0 0x0c380000 0 0x10000>,
1294 <0 0x0c390000 0 0x10000>;
1295 reg-names = "pmc", "wake", "aotag", "scratch";
1297 #interrupt-cells = <2>;
1298 interrupt-controller;
1300 sdmmc1_1v8: sdmmc1-1v8 {
1302 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1305 sdmmc1_3v3: sdmmc1-3v3 {
1307 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1310 sdmmc2_1v8: sdmmc2-1v8 {
1312 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1315 sdmmc2_3v3: sdmmc2-3v3 {
1317 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1320 sdmmc3_1v8: sdmmc3-1v8 {
1322 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1325 sdmmc3_3v3: sdmmc3-3v3 {
1327 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1332 compatible = "nvidia,tegra186-ccplex-cluster";
1333 reg = <0x0 0x0e000000 0x0 0x400000>;
1335 nvidia,bpmp = <&bpmp>;
1339 compatible = "nvidia,tegra186-pcie";
1340 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1341 device_type = "pci";
1342 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
1343 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
1344 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
1345 reg-names = "pads", "afi", "cs";
1347 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1348 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1349 interrupt-names = "intr", "msi";
1351 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0>;
1353 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1355 bus-range = <0x00 0xff>;
1356 #address-cells = <3>;
1359 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1360 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1361 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1362 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1363 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1364 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1366 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1367 <&bpmp TEGRA186_CLK_AFI>,
1368 <&bpmp TEGRA186_CLK_PLLE>;
1369 clock-names = "pex", "afi", "pll_e";
1371 resets = <&bpmp TEGRA186_RESET_PCIE>,
1372 <&bpmp TEGRA186_RESET_AFI>,
1373 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1374 reset-names = "pex", "afi", "pcie_x";
1376 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1377 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1378 interconnect-names = "dma-mem", "write";
1380 iommus = <&smmu TEGRA186_SID_AFI>;
1381 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1382 iommu-map-mask = <0x0>;
1384 status = "disabled";
1387 device_type = "pci";
1388 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
1389 reg = <0x000800 0 0 0 0>;
1390 status = "disabled";
1392 #address-cells = <3>;
1396 nvidia,num-lanes = <2>;
1400 device_type = "pci";
1401 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
1402 reg = <0x001000 0 0 0 0>;
1403 status = "disabled";
1405 #address-cells = <3>;
1409 nvidia,num-lanes = <1>;
1413 device_type = "pci";
1414 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
1415 reg = <0x001800 0 0 0 0>;
1416 status = "disabled";
1418 #address-cells = <3>;
1422 nvidia,num-lanes = <1>;
1426 smmu: iommu@12000000 {
1427 compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
1428 reg = <0 0x12000000 0 0x800000>;
1429 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1494 stream-match-mask = <0x7f80>;
1495 #global-interrupts = <1>;
1498 nvidia,memory-controller = <&mc>;
1502 compatible = "nvidia,tegra186-host1x";
1503 reg = <0x0 0x13e00000 0x0 0x10000>,
1504 <0x0 0x13e10000 0x0 0x10000>;
1505 reg-names = "hypervisor", "vm";
1506 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-names = "syncpt", "host1x";
1509 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1510 clock-names = "host1x";
1511 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1512 reset-names = "host1x";
1514 #address-cells = <1>;
1517 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1519 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1520 interconnect-names = "dma-mem";
1522 iommus = <&smmu TEGRA186_SID_HOST1X>;
1524 /* Context isolation domains */
1525 iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
1526 <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
1527 <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
1528 <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
1529 <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
1530 <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
1531 <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
1532 <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
1534 dpaux1: dpaux@15040000 {
1535 compatible = "nvidia,tegra186-dpaux";
1536 reg = <0x15040000 0x10000>;
1537 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1538 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1539 <&bpmp TEGRA186_CLK_PLLDP>;
1540 clock-names = "dpaux", "parent";
1541 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1542 reset-names = "dpaux";
1543 status = "disabled";
1545 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1547 state_dpaux1_aux: pinmux-aux {
1548 groups = "dpaux-io";
1552 state_dpaux1_i2c: pinmux-i2c {
1553 groups = "dpaux-io";
1557 state_dpaux1_off: pinmux-off {
1558 groups = "dpaux-io";
1563 #address-cells = <1>;
1568 display-hub@15200000 {
1569 compatible = "nvidia,tegra186-display";
1570 reg = <0x15200000 0x00040000>;
1571 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1572 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1573 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1574 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1575 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1576 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1577 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1578 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1579 "wgrp3", "wgrp4", "wgrp5";
1580 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1581 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1582 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1583 clock-names = "disp", "dsc", "hub";
1584 status = "disabled";
1586 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1588 #address-cells = <1>;
1591 ranges = <0x15200000 0x15200000 0x40000>;
1594 compatible = "nvidia,tegra186-dc";
1595 reg = <0x15200000 0x10000>;
1596 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1597 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1599 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1602 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1603 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1604 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1605 interconnect-names = "dma-mem", "read-1";
1606 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1608 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1613 compatible = "nvidia,tegra186-dc";
1614 reg = <0x15210000 0x10000>;
1615 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1616 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1618 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1621 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1622 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1623 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1624 interconnect-names = "dma-mem", "read-1";
1625 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1627 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
1632 compatible = "nvidia,tegra186-dc";
1633 reg = <0x15220000 0x10000>;
1634 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1635 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1637 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1640 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1641 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1642 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1643 interconnect-names = "dma-mem", "read-1";
1644 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1646 nvidia,outputs = <&sor0 &sor1>;
1651 dsia: dsi@15300000 {
1652 compatible = "nvidia,tegra186-dsi";
1653 reg = <0x15300000 0x10000>;
1654 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1655 clocks = <&bpmp TEGRA186_CLK_DSI>,
1656 <&bpmp TEGRA186_CLK_DSIA_LP>,
1657 <&bpmp TEGRA186_CLK_PLLD>;
1658 clock-names = "dsi", "lp", "parent";
1659 resets = <&bpmp TEGRA186_RESET_DSI>;
1660 reset-names = "dsi";
1661 status = "disabled";
1663 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1667 compatible = "nvidia,tegra186-vic";
1668 reg = <0x15340000 0x40000>;
1669 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1670 clocks = <&bpmp TEGRA186_CLK_VIC>;
1671 clock-names = "vic";
1672 resets = <&bpmp TEGRA186_RESET_VIC>;
1673 reset-names = "vic";
1675 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1676 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1677 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1678 interconnect-names = "dma-mem", "write";
1679 iommus = <&smmu TEGRA186_SID_VIC>;
1683 compatible = "nvidia,tegra186-nvjpg";
1684 reg = <0x15380000 0x40000>;
1685 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1686 clock-names = "nvjpg";
1687 resets = <&bpmp TEGRA186_RESET_NVJPG>;
1688 reset-names = "nvjpg";
1690 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1691 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
1692 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
1693 interconnect-names = "dma-mem", "write";
1694 iommus = <&smmu TEGRA186_SID_NVJPG>;
1697 dsib: dsi@15400000 {
1698 compatible = "nvidia,tegra186-dsi";
1699 reg = <0x15400000 0x10000>;
1700 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1701 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1702 <&bpmp TEGRA186_CLK_DSIB_LP>,
1703 <&bpmp TEGRA186_CLK_PLLD>;
1704 clock-names = "dsi", "lp", "parent";
1705 resets = <&bpmp TEGRA186_RESET_DSIB>;
1706 reset-names = "dsi";
1707 status = "disabled";
1709 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1713 compatible = "nvidia,tegra186-nvdec";
1714 reg = <0x15480000 0x40000>;
1715 clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1716 clock-names = "nvdec";
1717 resets = <&bpmp TEGRA186_RESET_NVDEC>;
1718 reset-names = "nvdec";
1720 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1721 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
1722 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
1723 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
1724 interconnect-names = "dma-mem", "read-1", "write";
1725 iommus = <&smmu TEGRA186_SID_NVDEC>;
1729 compatible = "nvidia,tegra186-nvenc";
1730 reg = <0x154c0000 0x40000>;
1731 clocks = <&bpmp TEGRA186_CLK_NVENC>;
1732 clock-names = "nvenc";
1733 resets = <&bpmp TEGRA186_RESET_NVENC>;
1734 reset-names = "nvenc";
1736 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1737 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
1738 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
1739 interconnect-names = "dma-mem", "write";
1740 iommus = <&smmu TEGRA186_SID_NVENC>;
1743 sor0: sor@15540000 {
1744 compatible = "nvidia,tegra186-sor";
1745 reg = <0x15540000 0x10000>;
1746 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1747 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1748 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1749 <&bpmp TEGRA186_CLK_PLLD2>,
1750 <&bpmp TEGRA186_CLK_PLLDP>,
1751 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1752 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1753 clock-names = "sor", "out", "parent", "dp", "safe",
1755 resets = <&bpmp TEGRA186_RESET_SOR0>;
1756 reset-names = "sor";
1757 pinctrl-0 = <&state_dpaux_aux>;
1758 pinctrl-1 = <&state_dpaux_i2c>;
1759 pinctrl-2 = <&state_dpaux_off>;
1760 pinctrl-names = "aux", "i2c", "off";
1761 status = "disabled";
1763 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1764 nvidia,interface = <0>;
1767 sor1: sor@15580000 {
1768 compatible = "nvidia,tegra186-sor";
1769 reg = <0x15580000 0x10000>;
1770 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1771 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1772 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1773 <&bpmp TEGRA186_CLK_PLLD3>,
1774 <&bpmp TEGRA186_CLK_PLLDP>,
1775 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1776 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1777 clock-names = "sor", "out", "parent", "dp", "safe",
1779 resets = <&bpmp TEGRA186_RESET_SOR1>;
1780 reset-names = "sor";
1781 pinctrl-0 = <&state_dpaux1_aux>;
1782 pinctrl-1 = <&state_dpaux1_i2c>;
1783 pinctrl-2 = <&state_dpaux1_off>;
1784 pinctrl-names = "aux", "i2c", "off";
1785 status = "disabled";
1787 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1788 nvidia,interface = <1>;
1791 dpaux: dpaux@155c0000 {
1792 compatible = "nvidia,tegra186-dpaux";
1793 reg = <0x155c0000 0x10000>;
1794 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1795 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1796 <&bpmp TEGRA186_CLK_PLLDP>;
1797 clock-names = "dpaux", "parent";
1798 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1799 reset-names = "dpaux";
1800 status = "disabled";
1802 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1804 state_dpaux_aux: pinmux-aux {
1805 groups = "dpaux-io";
1809 state_dpaux_i2c: pinmux-i2c {
1810 groups = "dpaux-io";
1814 state_dpaux_off: pinmux-off {
1815 groups = "dpaux-io";
1820 #address-cells = <1>;
1826 compatible = "nvidia,tegra186-dsi-padctl";
1827 reg = <0x15880000 0x10000>;
1828 resets = <&bpmp TEGRA186_RESET_DSI>;
1829 reset-names = "dsi";
1830 status = "disabled";
1833 dsic: dsi@15900000 {
1834 compatible = "nvidia,tegra186-dsi";
1835 reg = <0x15900000 0x10000>;
1836 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1837 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1838 <&bpmp TEGRA186_CLK_DSIC_LP>,
1839 <&bpmp TEGRA186_CLK_PLLD>;
1840 clock-names = "dsi", "lp", "parent";
1841 resets = <&bpmp TEGRA186_RESET_DSIC>;
1842 reset-names = "dsi";
1843 status = "disabled";
1845 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1848 dsid: dsi@15940000 {
1849 compatible = "nvidia,tegra186-dsi";
1850 reg = <0x15940000 0x10000>;
1851 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&bpmp TEGRA186_CLK_DSID>,
1853 <&bpmp TEGRA186_CLK_DSID_LP>,
1854 <&bpmp TEGRA186_CLK_PLLD>;
1855 clock-names = "dsi", "lp", "parent";
1856 resets = <&bpmp TEGRA186_RESET_DSID>;
1857 reset-names = "dsi";
1858 status = "disabled";
1860 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1865 compatible = "nvidia,gp10b";
1866 reg = <0x0 0x17000000 0x0 0x1000000>,
1867 <0x0 0x18000000 0x0 0x1000000>;
1868 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1870 interrupt-names = "stall", "nonstall";
1872 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1873 <&bpmp TEGRA186_CLK_GPU>;
1874 clock-names = "gpu", "pwr";
1875 resets = <&bpmp TEGRA186_RESET_GPU>;
1876 reset-names = "gpu";
1877 status = "disabled";
1879 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1880 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1881 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1882 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1883 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1884 interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
1888 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1889 reg = <0x0 0x30000000 0x0 0x50000>;
1890 #address-cells = <1>;
1892 ranges = <0x0 0x0 0x30000000 0x50000>;
1895 cpu_bpmp_tx: sram@4e000 {
1896 reg = <0x4e000 0x1000>;
1897 label = "cpu-bpmp-tx";
1901 cpu_bpmp_rx: sram@4f000 {
1902 reg = <0x4f000 0x1000>;
1903 label = "cpu-bpmp-rx";
1909 compatible = "nvidia,tegra186-bpmp";
1910 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1911 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1912 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1913 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1914 interconnect-names = "read", "write", "dma-mem", "dma-write";
1915 iommus = <&smmu TEGRA186_SID_BPMP>;
1916 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1917 TEGRA_HSP_DB_MASTER_BPMP>;
1918 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
1921 #power-domain-cells = <1>;
1924 compatible = "nvidia,tegra186-bpmp-i2c";
1925 nvidia,bpmp-bus-id = <5>;
1926 #address-cells = <1>;
1928 status = "disabled";
1931 bpmp_thermal: thermal {
1932 compatible = "nvidia,tegra186-bpmp-thermal";
1933 #thermal-sensor-cells = <1>;
1938 #address-cells = <1>;
1942 compatible = "nvidia,tegra186-denver";
1943 device_type = "cpu";
1944 i-cache-size = <0x20000>;
1945 i-cache-line-size = <64>;
1946 i-cache-sets = <512>;
1947 d-cache-size = <0x10000>;
1948 d-cache-line-size = <64>;
1949 d-cache-sets = <256>;
1950 next-level-cache = <&L2_DENVER>;
1955 compatible = "nvidia,tegra186-denver";
1956 device_type = "cpu";
1957 i-cache-size = <0x20000>;
1958 i-cache-line-size = <64>;
1959 i-cache-sets = <512>;
1960 d-cache-size = <0x10000>;
1961 d-cache-line-size = <64>;
1962 d-cache-sets = <256>;
1963 next-level-cache = <&L2_DENVER>;
1968 compatible = "arm,cortex-a57";
1969 device_type = "cpu";
1970 i-cache-size = <0xC000>;
1971 i-cache-line-size = <64>;
1972 i-cache-sets = <256>;
1973 d-cache-size = <0x8000>;
1974 d-cache-line-size = <64>;
1975 d-cache-sets = <256>;
1976 next-level-cache = <&L2_A57>;
1981 compatible = "arm,cortex-a57";
1982 device_type = "cpu";
1983 i-cache-size = <0xC000>;
1984 i-cache-line-size = <64>;
1985 i-cache-sets = <256>;
1986 d-cache-size = <0x8000>;
1987 d-cache-line-size = <64>;
1988 d-cache-sets = <256>;
1989 next-level-cache = <&L2_A57>;
1994 compatible = "arm,cortex-a57";
1995 device_type = "cpu";
1996 i-cache-size = <0xC000>;
1997 i-cache-line-size = <64>;
1998 i-cache-sets = <256>;
1999 d-cache-size = <0x8000>;
2000 d-cache-line-size = <64>;
2001 d-cache-sets = <256>;
2002 next-level-cache = <&L2_A57>;
2007 compatible = "arm,cortex-a57";
2008 device_type = "cpu";
2009 i-cache-size = <0xC000>;
2010 i-cache-line-size = <64>;
2011 i-cache-sets = <256>;
2012 d-cache-size = <0x8000>;
2013 d-cache-line-size = <64>;
2014 d-cache-sets = <256>;
2015 next-level-cache = <&L2_A57>;
2019 L2_DENVER: l2-cache0 {
2020 compatible = "cache";
2023 cache-size = <0x200000>;
2024 cache-line-size = <64>;
2025 cache-sets = <2048>;
2029 compatible = "cache";
2032 cache-size = <0x200000>;
2033 cache-line-size = <64>;
2034 cache-sets = <2048>;
2039 compatible = "arm,cortex-a57-pmu";
2040 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
2044 interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>;
2048 compatible = "nvidia,denver-pmu";
2049 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2051 interrupt-affinity = <&denver_0 &denver_1>;
2055 status = "disabled";
2057 clocks = <&bpmp TEGRA186_CLK_PLLA>,
2058 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2059 clock-names = "pll_a", "plla_out0";
2060 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2061 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2062 <&bpmp TEGRA186_CLK_AUD_MCLK>;
2063 assigned-clock-parents = <0>,
2064 <&bpmp TEGRA186_CLK_PLLA>,
2065 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2067 * PLLA supports dynamic ramp. Below initial rate is chosen
2068 * for this to work and oscillate between base rates required
2069 * for 8x and 11.025x sample rate streams.
2071 assigned-clock-rates = <258000000>;
2073 iommus = <&smmu TEGRA186_SID_APE>;
2077 /* Cortex-A57 cluster */
2079 polling-delay = <0>;
2080 polling-delay-passive = <1000>;
2082 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
2086 temperature = <101000>;
2096 /* Denver cluster */
2098 polling-delay = <0>;
2099 polling-delay-passive = <1000>;
2101 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
2105 temperature = <101000>;
2116 polling-delay = <0>;
2117 polling-delay-passive = <1000>;
2119 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
2123 temperature = <101000>;
2134 polling-delay = <0>;
2135 polling-delay-passive = <1000>;
2137 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
2141 temperature = <101000>;
2152 polling-delay = <0>;
2153 polling-delay-passive = <1000>;
2155 thermal-sensors = <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
2159 temperature = <101000>;
2171 compatible = "arm,armv8-timer";
2172 interrupts = <GIC_PPI 13
2173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2180 interrupt-parent = <&gic>;