1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
7 #include "sparx5_pcb_common.dtsi"
11 compatible = "gpio-restart";
12 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
17 compatible = "gpio-leds";
19 label = "eth60:yellow";
20 gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>;
21 default-state = "off";
24 label = "eth60:green";
25 gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>;
26 default-state = "off";
29 label = "eth61:yellow";
30 gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>;
31 default-state = "off";
34 label = "eth61:green";
35 gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>;
36 default-state = "off";
39 label = "eth62:yellow";
40 gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>;
41 default-state = "off";
44 label = "eth62:green";
45 gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>;
46 default-state = "off";
49 label = "eth63:yellow";
50 gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>;
51 default-state = "off";
54 label = "eth63:green";
55 gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>;
56 default-state = "off";
62 i2cmux_pins_i: i2cmux-pins {
63 pins = "GPIO_35", "GPIO_36",
65 function = "twi_scl_m";
68 i2cmux_s29: i2cmux-0-pins {
70 function = "twi_scl_m";
73 i2cmux_s30: i2cmux-1-pins {
75 function = "twi_scl_m";
78 i2cmux_s31: i2cmux-2-pins {
80 function = "twi_scl_m";
83 i2cmux_s32: i2cmux-3-pins {
85 function = "twi_scl_m";
93 compatible = "jedec,spi-nor";
94 spi-max-frequency = <8000000>;
102 compatible = "spi-mux";
103 mux-controls = <&mux>;
104 #address-cells = <1>;
108 compatible = "jedec,spi-nor";
109 spi-max-frequency = <8000000>;
110 reg = <0x9>; /* SPI */
117 microchip,sgpio-port-ranges = <24 31>;
128 microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
132 i2c0_imux: i2c0-imux@0 {
133 compatible = "i2c-mux-pinctrl";
134 #address-cells = <1>;
136 i2c-parent = <&i2c0>;
142 "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
144 pinctrl-0 = <&i2cmux_s29>;
145 pinctrl-1 = <&i2cmux_s30>;
146 pinctrl-2 = <&i2cmux_s31>;
147 pinctrl-3 = <&i2cmux_s32>;
148 pinctrl-4 = <&i2cmux_pins_i>;
151 #address-cells = <1>;
156 #address-cells = <1>;
161 #address-cells = <1>;
166 #address-cells = <1>;
172 sfp_eth60: sfp-eth60 {
173 compatible = "sff,sfp";
174 i2c-bus = <&i2c_sfp1>;
175 tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
176 rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
177 los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
178 mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
179 tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
181 sfp_eth61: sfp-eth61 {
182 compatible = "sff,sfp";
183 i2c-bus = <&i2c_sfp2>;
184 tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
185 rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
186 los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
187 mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
188 tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
190 sfp_eth62: sfp-eth62 {
191 compatible = "sff,sfp";
192 i2c-bus = <&i2c_sfp3>;
193 tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
194 rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
195 los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
196 mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
197 tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
199 sfp_eth63: sfp-eth63 {
200 compatible = "sff,sfp";
201 i2c-bus = <&i2c_sfp4>;
202 tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
203 rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
204 los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
205 mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
206 tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
212 phy0: ethernet-phy@0 {
215 phy1: ethernet-phy@1 {
218 phy2: ethernet-phy@2 {
221 phy3: ethernet-phy@3 {
224 phy4: ethernet-phy@4 {
227 phy5: ethernet-phy@5 {
230 phy6: ethernet-phy@6 {
233 phy7: ethernet-phy@7 {
236 phy8: ethernet-phy@8 {
239 phy9: ethernet-phy@9 {
242 phy10: ethernet-phy@10 {
245 phy11: ethernet-phy@11 {
248 phy12: ethernet-phy@12 {
251 phy13: ethernet-phy@13 {
254 phy14: ethernet-phy@14 {
257 phy15: ethernet-phy@15 {
260 phy16: ethernet-phy@16 {
263 phy17: ethernet-phy@17 {
266 phy18: ethernet-phy@18 {
269 phy19: ethernet-phy@19 {
272 phy20: ethernet-phy@20 {
275 phy21: ethernet-phy@21 {
278 phy22: ethernet-phy@22 {
281 phy23: ethernet-phy@23 {
288 phy24: ethernet-phy@24 {
291 phy25: ethernet-phy@25 {
294 phy26: ethernet-phy@26 {
297 phy27: ethernet-phy@27 {
300 phy28: ethernet-phy@28 {
303 phy29: ethernet-phy@29 {
306 phy30: ethernet-phy@30 {
309 phy31: ethernet-phy@31 {
312 phy32: ethernet-phy@32 {
315 phy33: ethernet-phy@33 {
318 phy34: ethernet-phy@34 {
321 phy35: ethernet-phy@35 {
324 phy36: ethernet-phy@36 {
327 phy37: ethernet-phy@37 {
330 phy38: ethernet-phy@38 {
333 phy39: ethernet-phy@39 {
336 phy40: ethernet-phy@40 {
339 phy41: ethernet-phy@41 {
342 phy42: ethernet-phy@42 {
345 phy43: ethernet-phy@43 {
348 phy44: ethernet-phy@44 {
351 phy45: ethernet-phy@45 {
354 phy46: ethernet-phy@46 {
357 phy47: ethernet-phy@47 {
364 phy64: ethernet-phy@64 {
371 #address-cells = <1>;
376 microchip,bandwidth = <1000>;
378 phy-handle = <&phy0>;
383 microchip,bandwidth = <1000>;
385 phy-handle = <&phy1>;
390 microchip,bandwidth = <1000>;
392 phy-handle = <&phy2>;
397 microchip,bandwidth = <1000>;
399 phy-handle = <&phy3>;
404 microchip,bandwidth = <1000>;
406 phy-handle = <&phy4>;
411 microchip,bandwidth = <1000>;
413 phy-handle = <&phy5>;
418 microchip,bandwidth = <1000>;
420 phy-handle = <&phy6>;
425 microchip,bandwidth = <1000>;
427 phy-handle = <&phy7>;
432 microchip,bandwidth = <1000>;
434 phy-handle = <&phy8>;
439 microchip,bandwidth = <1000>;
441 phy-handle = <&phy9>;
446 microchip,bandwidth = <1000>;
448 phy-handle = <&phy10>;
453 microchip,bandwidth = <1000>;
455 phy-handle = <&phy11>;
460 microchip,bandwidth = <1000>;
462 phy-handle = <&phy12>;
467 microchip,bandwidth = <1000>;
469 phy-handle = <&phy13>;
474 microchip,bandwidth = <1000>;
476 phy-handle = <&phy14>;
481 microchip,bandwidth = <1000>;
483 phy-handle = <&phy15>;
488 microchip,bandwidth = <1000>;
490 phy-handle = <&phy16>;
495 microchip,bandwidth = <1000>;
497 phy-handle = <&phy17>;
502 microchip,bandwidth = <1000>;
504 phy-handle = <&phy18>;
509 microchip,bandwidth = <1000>;
511 phy-handle = <&phy19>;
516 microchip,bandwidth = <1000>;
518 phy-handle = <&phy20>;
523 microchip,bandwidth = <1000>;
525 phy-handle = <&phy21>;
530 microchip,bandwidth = <1000>;
532 phy-handle = <&phy22>;
537 microchip,bandwidth = <1000>;
539 phy-handle = <&phy23>;
544 microchip,bandwidth = <1000>;
546 phy-handle = <&phy24>;
551 microchip,bandwidth = <1000>;
553 phy-handle = <&phy25>;
558 microchip,bandwidth = <1000>;
560 phy-handle = <&phy26>;
565 microchip,bandwidth = <1000>;
567 phy-handle = <&phy27>;
572 microchip,bandwidth = <1000>;
574 phy-handle = <&phy28>;
579 microchip,bandwidth = <1000>;
581 phy-handle = <&phy29>;
586 microchip,bandwidth = <1000>;
588 phy-handle = <&phy30>;
593 microchip,bandwidth = <1000>;
595 phy-handle = <&phy31>;
600 microchip,bandwidth = <1000>;
602 phy-handle = <&phy32>;
607 microchip,bandwidth = <1000>;
609 phy-handle = <&phy33>;
614 microchip,bandwidth = <1000>;
616 phy-handle = <&phy34>;
621 microchip,bandwidth = <1000>;
623 phy-handle = <&phy35>;
628 microchip,bandwidth = <1000>;
630 phy-handle = <&phy36>;
635 microchip,bandwidth = <1000>;
637 phy-handle = <&phy37>;
642 microchip,bandwidth = <1000>;
644 phy-handle = <&phy38>;
649 microchip,bandwidth = <1000>;
651 phy-handle = <&phy39>;
656 microchip,bandwidth = <1000>;
658 phy-handle = <&phy40>;
663 microchip,bandwidth = <1000>;
665 phy-handle = <&phy41>;
670 microchip,bandwidth = <1000>;
672 phy-handle = <&phy42>;
677 microchip,bandwidth = <1000>;
679 phy-handle = <&phy43>;
684 microchip,bandwidth = <1000>;
686 phy-handle = <&phy44>;
691 microchip,bandwidth = <1000>;
693 phy-handle = <&phy45>;
698 microchip,bandwidth = <1000>;
700 phy-handle = <&phy46>;
705 microchip,bandwidth = <1000>;
707 phy-handle = <&phy47>;
710 /* Then the 25G interfaces */
713 microchip,bandwidth = <25000>;
715 phy-mode = "10gbase-r";
717 managed = "in-band-status";
721 microchip,bandwidth = <25000>;
723 phy-mode = "10gbase-r";
725 managed = "in-band-status";
729 microchip,bandwidth = <25000>;
731 phy-mode = "10gbase-r";
733 managed = "in-band-status";
737 microchip,bandwidth = <25000>;
739 phy-mode = "10gbase-r";
741 managed = "in-band-status";
743 /* Finally the Management interface */
746 microchip,bandwidth = <1000>;
748 phy-handle = <&phy64>;