1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
23 stdout-path = "serial0:115200n8";
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 next-level-cache = <&L2_0>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53-pmu";
62 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-affinity = <&cpu0>, <&cpu1>;
67 compatible = "arm,psci-0.2";
72 compatible = "arm,armv8-timer";
73 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
74 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
75 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
76 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
79 lcpll_clk: lcpll-clk {
80 compatible = "fixed-clock";
82 clock-frequency = <2500000000>;
85 clks: clock-controller@61110000c {
86 compatible = "microchip,sparx5-dpll";
88 clocks = <&lcpll_clk>;
89 reg = <0x6 0x1110000c 0x24>;
93 compatible = "fixed-clock";
95 clock-frequency = <250000000>;
99 compatible = "fixed-clock";
101 clock-frequency = <625000000>;
105 compatible = "simple-bus";
106 #address-cells = <2>;
110 gic: interrupt-controller@600300000 {
111 compatible = "arm,gic-v3";
112 #interrupt-cells = <3>;
113 #address-cells = <2>;
115 interrupt-controller;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
118 <0x6 0x00200000 0x2000>, /* GICC */
119 <0x6 0x00210000 0x2000>, /* GICV */
120 <0x6 0x00220000 0x2000>; /* GICH */
121 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
124 cpu_ctrl: syscon@600000000 {
125 compatible = "microchip,sparx5-cpu-syscon", "syscon",
127 reg = <0x6 0x00000000 0xd0>;
128 mux: mux-controller {
129 compatible = "mmio-mux";
130 #mux-control-cells = <0>;
132 * SI_OWNER and SI2_OWNER in GENERAL_CTRL
133 * SPI: value 9 - (SIMC,SIBM) = 0b1001
134 * SPI2: value 6 - (SIBM,SIMC) = 0b0110
136 mux-reg-masks = <0x88 0xf0>;
140 reset: reset-controller@611010008 {
141 compatible = "microchip,sparx5-switch-reset";
142 reg = <0x6 0x11010008 0x4>;
145 cpu-syscon = <&cpu_ctrl>;
148 uart0: serial@600100000 {
149 pinctrl-0 = <&uart_pins>;
150 pinctrl-names = "default";
151 compatible = "ns16550a";
152 reg = <0x6 0x00100000 0x20>;
156 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
161 uart1: serial@600102000 {
162 pinctrl-0 = <&uart2_pins>;
163 pinctrl-names = "default";
164 compatible = "ns16550a";
165 reg = <0x6 0x00102000 0x20>;
169 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
174 spi0: spi@600104000 {
175 #address-cells = <1>;
177 compatible = "microchip,sparx5-spi";
178 reg = <0x6 0x00104000 0x40>;
183 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
187 timer1: timer@600105000 {
188 compatible = "snps,dw-apb-timer";
189 reg = <0x6 0x00105000 0x1000>;
191 clock-names = "timer";
192 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
195 sdhci0: mmc@600800000 {
196 compatible = "microchip,dw-sparx5-sdhci";
198 reg = <0x6 0x00800000 0x1000>;
199 pinctrl-0 = <&emmc_pins>;
200 pinctrl-names = "default";
201 clocks = <&clks CLK_ID_AUX1>;
202 clock-names = "core";
203 assigned-clocks = <&clks CLK_ID_AUX1>;
204 assigned-clock-rates = <800000000>;
205 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
209 gpio: pinctrl@6110101e0 {
210 compatible = "microchip,sparx5-pinctrl";
211 reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
214 gpio-ranges = <&gpio 0 0 64>;
215 interrupt-controller;
216 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
217 #interrupt-cells = <2>;
235 pins = "GPIO_39", "GPIO_40", "GPIO_41";
239 sgpio0_pins: sgpio-pins {
240 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
244 sgpio1_pins: sgpio1-pins {
245 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
249 sgpio2_pins: sgpio2-pins {
250 pins = "GPIO_30", "GPIO_31", "GPIO_32",
255 uart_pins: uart-pins {
256 pins = "GPIO_10", "GPIO_11";
260 uart2_pins: uart2-pins {
261 pins = "GPIO_26", "GPIO_27";
266 pins = "GPIO_14", "GPIO_15";
270 i2c2_pins: i2c2-pins {
271 pins = "GPIO_28", "GPIO_29";
275 emmc_pins: emmc-pins {
276 pins = "GPIO_34", "GPIO_35", "GPIO_36",
277 "GPIO_37", "GPIO_38", "GPIO_39",
278 "GPIO_40", "GPIO_41", "GPIO_42",
279 "GPIO_43", "GPIO_44", "GPIO_45",
280 "GPIO_46", "GPIO_47";
284 miim1_pins: miim1-pins {
285 pins = "GPIO_56", "GPIO_57";
289 miim2_pins: miim2-pins {
290 pins = "GPIO_58", "GPIO_59";
294 miim3_pins: miim3-pins {
295 pins = "GPIO_52", "GPIO_53";
300 sgpio0: gpio@61101036c {
301 #address-cells = <1>;
303 compatible = "microchip,sparx5-sgpio";
306 pinctrl-0 = <&sgpio0_pins>;
307 pinctrl-names = "default";
309 reset-names = "switch";
310 reg = <0x6 0x1101036c 0x100>;
312 compatible = "microchip,sparx5-sgpio-bank";
317 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-controller;
319 #interrupt-cells = <3>;
322 compatible = "microchip,sparx5-sgpio-bank";
330 sgpio1: gpio@611010484 {
331 #address-cells = <1>;
333 compatible = "microchip,sparx5-sgpio";
336 pinctrl-0 = <&sgpio1_pins>;
337 pinctrl-names = "default";
339 reset-names = "switch";
340 reg = <0x6 0x11010484 0x100>;
342 compatible = "microchip,sparx5-sgpio-bank";
347 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-controller;
349 #interrupt-cells = <3>;
352 compatible = "microchip,sparx5-sgpio-bank";
360 sgpio2: gpio@61101059c {
361 #address-cells = <1>;
363 compatible = "microchip,sparx5-sgpio";
366 pinctrl-0 = <&sgpio2_pins>;
367 pinctrl-names = "default";
369 reset-names = "switch";
370 reg = <0x6 0x1101059c 0x100>;
373 compatible = "microchip,sparx5-sgpio-bank";
377 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
378 interrupt-controller;
379 #interrupt-cells = <3>;
382 compatible = "microchip,sparx5-sgpio-bank";
390 i2c0: i2c@600101000 {
391 compatible = "snps,designware-i2c";
393 pinctrl-0 = <&i2c_pins>;
394 pinctrl-names = "default";
395 reg = <0x6 0x00101000 0x100>;
396 #address-cells = <1>;
398 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
399 i2c-sda-hold-time-ns = <300>;
400 clock-frequency = <100000>;
404 i2c1: i2c@600103000 {
405 compatible = "snps,designware-i2c";
407 pinctrl-0 = <&i2c2_pins>;
408 pinctrl-names = "default";
409 reg = <0x6 0x00103000 0x100>;
410 #address-cells = <1>;
412 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
413 i2c-sda-hold-time-ns = <300>;
414 clock-frequency = <100000>;
418 tmon0: tmon@610508110 {
419 compatible = "microchip,sparx5-temp";
420 reg = <0x6 0x10508110 0xc>;
421 #thermal-sensor-cells = <0>;
425 mdio0: mdio@6110102b0 {
426 compatible = "mscc,ocelot-miim";
428 #address-cells = <1>;
430 reg = <0x6 0x110102b0 0x24>;
433 mdio1: mdio@6110102d4 {
434 compatible = "mscc,ocelot-miim";
436 pinctrl-0 = <&miim1_pins>;
437 pinctrl-names = "default";
438 #address-cells = <1>;
440 reg = <0x6 0x110102d4 0x24>;
443 mdio2: mdio@6110102f8 {
444 compatible = "mscc,ocelot-miim";
446 pinctrl-0 = <&miim2_pins>;
447 pinctrl-names = "default";
448 #address-cells = <1>;
450 reg = <0x6 0x110102d4 0x24>;
453 mdio3: mdio@61101031c {
454 compatible = "mscc,ocelot-miim";
456 pinctrl-0 = <&miim3_pins>;
457 pinctrl-names = "default";
458 #address-cells = <1>;
460 reg = <0x6 0x1101031c 0x24>;
463 serdes: serdes@10808000 {
464 compatible = "microchip,sparx5-serdes";
467 reg = <0x6 0x10808000 0x5d0000>;
470 switch: switch@600000000 {
471 compatible = "microchip,sparx5-switch";
472 reg = <0x6 0 0x401000>,
473 <0x6 0x10004000 0x7fc000>,
474 <0x6 0x11010000 0xaf0000>;
475 reg-names = "cpu", "dev", "gcb";
476 interrupt-names = "xtr", "fdma", "ptp";
477 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
481 reset-names = "switch";