arch/arm64/boot/dts/microchip/sparx5.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/microchip,sparx5.h>
   9
  10 / {
  11         compatible = "microchip,sparx5";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <1>;
  15
  16         aliases {
  17                 spi0 = &spi0;
  18                 serial0 = &uart0;
  19                 serial1 = &uart1;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                         };
  38                 };
  39                 cpu0: cpu@0 {
  40                         compatible = "arm,cortex-a53";
  41                         device_type = "cpu";
  42                         reg = <0x0>;
  43                         enable-method = "psci";
  44                         next-level-cache = <&L2_0>;
  45                 };
  46                 cpu1: cpu@1 {
  47                         compatible = "arm,cortex-a53";
  48                         device_type = "cpu";
  49                         reg = <0x1>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&L2_0>;
  52                 };
  53                 L2_0: l2-cache0 {
  54                         compatible = "cache";
  55                         cache-level = <2>;
  56                         cache-unified;
  57                 };
  58         };
  59
  60         arm-pmu {
  61                 compatible = "arm,cortex-a53-pmu";
  62                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  63                 interrupt-affinity = <&cpu0>, <&cpu1>;
  64         };
  65
  66         psci: psci {
  67                 compatible = "arm,psci-0.2";
  68                 method = "smc";
  69         };
  70
  71         timer {
  72                 compatible = "arm,armv8-timer";
  73                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  74                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  75                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  76                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  77         };
  78
  79         lcpll_clk: lcpll-clk {
  80                 compatible = "fixed-clock";
  81                 #clock-cells = <0>;
  82                 clock-frequency = <2500000000>;
  83         };
  84
  85         clks: clock-controller@61110000c {
  86                 compatible = "microchip,sparx5-dpll";
  87                 #clock-cells = <1>;
  88                 clocks = <&lcpll_clk>;
  89                 reg = <0x6 0x1110000c 0x24>;
  90         };
  91
  92         ahb_clk: ahb-clk {
  93                 compatible = "fixed-clock";
  94                 #clock-cells = <0>;
  95                 clock-frequency = <250000000>;
  96         };
  97
  98         sys_clk: sys-clk {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <625000000>;
 102         };
 103
 104         axi: axi@600000000 {
 105                 compatible = "simple-bus";
 106                 #address-cells = <2>;
 107                 #size-cells = <1>;
 108                 ranges;
 109
 110                 gic: interrupt-controller@600300000 {
 111                         compatible = "arm,gic-v3";
 112                         #interrupt-cells = <3>;
 113                         #address-cells = <2>;
 114                         #size-cells = <2>;
 115                         interrupt-controller;
 116                         reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
 117                               <0x6 0x00340000 0xc0000>, /* GICR */
 118                               <0x6 0x00200000 0x2000>,  /* GICC */
 119                               <0x6 0x00210000 0x2000>,  /* GICV */
 120                               <0x6 0x00220000 0x2000>;  /* GICH */
 121                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 122                 };
 123
 124                 cpu_ctrl: syscon@600000000 {
 125                         compatible = "microchip,sparx5-cpu-syscon", "syscon",
 126                                      "simple-mfd";
 127                         reg = <0x6 0x00000000 0xd0>;
 128                         mux: mux-controller {
 129                                 compatible = "mmio-mux";
 130                                 #mux-control-cells = <0>;
 131                                 /*
 132                                  * SI_OWNER and SI2_OWNER in GENERAL_CTRL
 133                                  * SPI:  value 9 - (SIMC,SIBM) = 0b1001
 134                                  * SPI2: value 6 - (SIBM,SIMC) = 0b0110
 135                                  */
 136                                 mux-reg-masks = <0x88 0xf0>;
 137                         };
 138                 };
 139
 140                 reset: reset-controller@611010008 {
 141                         compatible = "microchip,sparx5-switch-reset";
 142                         reg = <0x6 0x11010008 0x4>;
 143                         reg-names = "gcb";
 144                         #reset-cells = <1>;
 145                         cpu-syscon = <&cpu_ctrl>;
 146                 };
 147
 148                 uart0: serial@600100000 {
 149                         pinctrl-0 = <&uart_pins>;
 150                         pinctrl-names = "default";
 151                         compatible = "ns16550a";
 152                         reg = <0x6 0x00100000 0x20>;
 153                         clocks = <&ahb_clk>;
 154                         reg-io-width = <4>;
 155                         reg-shift = <2>;
 156                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 157
 158                         status = "disabled";
 159                 };
 160
 161                 uart1: serial@600102000 {
 162                         pinctrl-0 = <&uart2_pins>;
 163                         pinctrl-names = "default";
 164                         compatible = "ns16550a";
 165                         reg = <0x6 0x00102000 0x20>;
 166                         clocks = <&ahb_clk>;
 167                         reg-io-width = <4>;
 168                         reg-shift = <2>;
 169                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 170
 171                         status = "disabled";
 172                 };
 173
 174                 spi0: spi@600104000 {
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         compatible = "microchip,sparx5-spi";
 178                         reg = <0x6 0x00104000 0x40>;
 179                         num-cs = <16>;
 180                         reg-io-width = <4>;
 181                         reg-shift = <2>;
 182                         clocks = <&ahb_clk>;
 183                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 184                         status = "disabled";
 185                 };
 186
 187                 timer1: timer@600105000 {
 188                         compatible = "snps,dw-apb-timer";
 189                         reg = <0x6 0x00105000 0x1000>;
 190                         clocks = <&ahb_clk>;
 191                         clock-names = "timer";
 192                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 193                 };
 194
 195                 sdhci0: mmc@600800000 {
 196                         compatible = "microchip,dw-sparx5-sdhci";
 197                         status = "disabled";
 198                         reg = <0x6 0x00800000 0x1000>;
 199                         pinctrl-0 = <&emmc_pins>;
 200                         pinctrl-names = "default";
 201                         clocks = <&clks CLK_ID_AUX1>;
 202                         clock-names = "core";
 203                         assigned-clocks = <&clks CLK_ID_AUX1>;
 204                         assigned-clock-rates = <800000000>;
 205                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 206                         bus-width = <8>;
 207                 };
 208
 209                 gpio: pinctrl@6110101e0 {
 210                         compatible = "microchip,sparx5-pinctrl";
 211                         reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
 212                         gpio-controller;
 213                         #gpio-cells = <2>;
 214                         gpio-ranges = <&gpio 0 0 64>;
 215                         interrupt-controller;
 216                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 217                         #interrupt-cells = <2>;
 218
 219                         cs1_pins: cs1-pins {
 220                                 pins = "GPIO_16";
 221                                 function = "si";
 222                         };
 223
 224                         cs2_pins: cs2-pins {
 225                                 pins = "GPIO_17";
 226                                 function = "si";
 227                         };
 228
 229                         cs3_pins: cs3-pins {
 230                                 pins = "GPIO_18";
 231                                 function = "si";
 232                         };
 233
 234                         si2_pins: si2-pins {
 235                                 pins = "GPIO_39", "GPIO_40", "GPIO_41";
 236                                 function = "si2";
 237                         };
 238
 239                         sgpio0_pins: sgpio-pins {
 240                                 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
 241                                 function = "sg0";
 242                         };
 243
 244                         sgpio1_pins: sgpio1-pins {
 245                                 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
 246                                 function = "sg1";
 247                         };
 248
 249                         sgpio2_pins: sgpio2-pins {
 250                                 pins = "GPIO_30", "GPIO_31", "GPIO_32",
 251                                        "GPIO_33";
 252                                 function = "sg2";
 253                         };
 254
 255                         uart_pins: uart-pins {
 256                                 pins = "GPIO_10", "GPIO_11";
 257                                 function = "uart";
 258                         };
 259
 260                         uart2_pins: uart2-pins {
 261                                 pins = "GPIO_26", "GPIO_27";
 262                                 function = "uart2";
 263                         };
 264
 265                         i2c_pins: i2c-pins {
 266                                 pins = "GPIO_14", "GPIO_15";
 267                                 function = "twi";
 268                         };
 269
 270                         i2c2_pins: i2c2-pins {
 271                                 pins = "GPIO_28", "GPIO_29";
 272                                 function = "twi2";
 273                         };
 274
 275                         emmc_pins: emmc-pins {
 276                                 pins = "GPIO_34", "GPIO_35", "GPIO_36",
 277                                         "GPIO_37", "GPIO_38", "GPIO_39",
 278                                         "GPIO_40", "GPIO_41", "GPIO_42",
 279                                         "GPIO_43", "GPIO_44", "GPIO_45",
 280                                         "GPIO_46", "GPIO_47";
 281                                 function = "emmc";
 282                         };
 283
 284                         miim1_pins: miim1-pins {
 285                                 pins = "GPIO_56", "GPIO_57";
 286                                 function = "miim";
 287                         };
 288
 289                         miim2_pins: miim2-pins {
 290                                 pins = "GPIO_58", "GPIO_59";
 291                                 function = "miim";
 292                         };
 293
 294                         miim3_pins: miim3-pins {
 295                                 pins = "GPIO_52", "GPIO_53";
 296                                 function = "miim";
 297                         };
 298                 };
 299
 300                 sgpio0: gpio@61101036c {
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         compatible = "microchip,sparx5-sgpio";
 304                         status = "disabled";
 305                         clocks = <&sys_clk>;
 306                         pinctrl-0 = <&sgpio0_pins>;
 307                         pinctrl-names = "default";
 308                         resets = <&reset 0>;
 309                         reset-names = "switch";
 310                         reg = <0x6 0x1101036c 0x100>;
 311                         sgpio_in0: gpio@0 {
 312                                 compatible = "microchip,sparx5-sgpio-bank";
 313                                 reg = <0>;
 314                                 gpio-controller;
 315                                 #gpio-cells = <3>;
 316                                 ngpios = <96>;
 317                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 318                                 interrupt-controller;
 319                                 #interrupt-cells = <3>;
 320                         };
 321                         sgpio_out0: gpio@1 {
 322                                 compatible = "microchip,sparx5-sgpio-bank";
 323                                 reg = <1>;
 324                                 gpio-controller;
 325                                 #gpio-cells = <3>;
 326                                 ngpios = <96>;
 327                         };
 328                 };
 329
 330                 sgpio1: gpio@611010484 {
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         compatible = "microchip,sparx5-sgpio";
 334                         status = "disabled";
 335                         clocks = <&sys_clk>;
 336                         pinctrl-0 = <&sgpio1_pins>;
 337                         pinctrl-names = "default";
 338                         resets = <&reset 0>;
 339                         reset-names = "switch";
 340                         reg = <0x6 0x11010484 0x100>;
 341                         sgpio_in1: gpio@0 {
 342                                 compatible = "microchip,sparx5-sgpio-bank";
 343                                 reg = <0>;
 344                                 gpio-controller;
 345                                 #gpio-cells = <3>;
 346                                 ngpios = <96>;
 347                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 348                                 interrupt-controller;
 349                                 #interrupt-cells = <3>;
 350                         };
 351                         sgpio_out1: gpio@1 {
 352                                 compatible = "microchip,sparx5-sgpio-bank";
 353                                 reg = <1>;
 354                                 gpio-controller;
 355                                 #gpio-cells = <3>;
 356                                 ngpios = <96>;
 357                         };
 358                 };
 359
 360                 sgpio2: gpio@61101059c {
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         compatible = "microchip,sparx5-sgpio";
 364                         status = "disabled";
 365                         clocks = <&sys_clk>;
 366                         pinctrl-0 = <&sgpio2_pins>;
 367                         pinctrl-names = "default";
 368                         resets = <&reset 0>;
 369                         reset-names = "switch";
 370                         reg = <0x6 0x1101059c 0x100>;
 371                         sgpio_in2: gpio@0 {
 372                                 reg = <0>;
 373                                 compatible = "microchip,sparx5-sgpio-bank";
 374                                 gpio-controller;
 375                                 #gpio-cells = <3>;
 376                                 ngpios = <96>;
 377                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 378                                 interrupt-controller;
 379                                 #interrupt-cells = <3>;
 380                         };
 381                         sgpio_out2: gpio@1 {
 382                                 compatible = "microchip,sparx5-sgpio-bank";
 383                                 reg = <1>;
 384                                 gpio-controller;
 385                                 #gpio-cells = <3>;
 386                                 ngpios = <96>;
 387                         };
 388                 };
 389
 390                 i2c0: i2c@600101000 {
 391                         compatible = "snps,designware-i2c";
 392                         status = "disabled";
 393                         pinctrl-0 = <&i2c_pins>;
 394                         pinctrl-names = "default";
 395                         reg = <0x6 0x00101000 0x100>;
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 399                         i2c-sda-hold-time-ns = <300>;
 400                         clock-frequency = <100000>;
 401                         clocks = <&ahb_clk>;
 402                 };
 403
 404                 i2c1: i2c@600103000 {
 405                         compatible = "snps,designware-i2c";
 406                         status = "disabled";
 407                         pinctrl-0 = <&i2c2_pins>;
 408                         pinctrl-names = "default";
 409                         reg = <0x6 0x00103000 0x100>;
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 413                         i2c-sda-hold-time-ns = <300>;
 414                         clock-frequency = <100000>;
 415                         clocks = <&ahb_clk>;
 416                 };
 417
 418                 tmon0: tmon@610508110 {
 419                         compatible = "microchip,sparx5-temp";
 420                         reg = <0x6 0x10508110 0xc>;
 421                         #thermal-sensor-cells = <0>;
 422                         clocks = <&ahb_clk>;
 423                 };
 424
 425                 mdio0: mdio@6110102b0 {
 426                         compatible = "mscc,ocelot-miim";
 427                         status = "disabled";
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         reg = <0x6 0x110102b0 0x24>;
 431                 };
 432
 433                 mdio1: mdio@6110102d4 {
 434                         compatible = "mscc,ocelot-miim";
 435                         status = "disabled";
 436                         pinctrl-0 = <&miim1_pins>;
 437                         pinctrl-names = "default";
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         reg = <0x6 0x110102d4 0x24>;
 441                 };
 442
 443                 mdio2: mdio@6110102f8 {
 444                         compatible = "mscc,ocelot-miim";
 445                         status = "disabled";
 446                         pinctrl-0 = <&miim2_pins>;
 447                         pinctrl-names = "default";
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         reg = <0x6 0x110102d4 0x24>;
 451                 };
 452
 453                 mdio3: mdio@61101031c {
 454                         compatible = "mscc,ocelot-miim";
 455                         status = "disabled";
 456                         pinctrl-0 = <&miim3_pins>;
 457                         pinctrl-names = "default";
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         reg = <0x6 0x1101031c 0x24>;
 461                 };
 462
 463                 serdes: serdes@10808000 {
 464                         compatible = "microchip,sparx5-serdes";
 465                         #phy-cells = <1>;
 466                         clocks = <&sys_clk>;
 467                         reg = <0x6 0x10808000 0x5d0000>;
 468                 };
 469
 470                 switch: switch@600000000 {
 471                         compatible = "microchip,sparx5-switch";
 472                         reg = <0x6 0 0x401000>,
 473                               <0x6 0x10004000 0x7fc000>,
 474                               <0x6 0x11010000 0xaf0000>;
 475                         reg-names = "cpu", "dev", "gcb";
 476                         interrupt-names = "xtr", "fdma", "ptp";
 477                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 478                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 479                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 480                         resets = <&reset 0>;
 481                         reset-names = "switch";
 482                 };
 483         };
 484 };