1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
23 stdout-path = "serial0:115200n8";
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 next-level-cache = <&L2_0>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
59 compatible = "arm,cortex-a53-pmu";
60 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
61 interrupt-affinity = <&cpu0>, <&cpu1>;
65 compatible = "arm,psci-0.2";
70 compatible = "arm,armv8-timer";
71 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
72 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
73 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
74 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
77 lcpll_clk: lcpll-clk {
78 compatible = "fixed-clock";
80 clock-frequency = <2500000000>;
83 clks: clock-controller@61110000c {
84 compatible = "microchip,sparx5-dpll";
86 clocks = <&lcpll_clk>;
87 reg = <0x6 0x1110000c 0x24>;
91 compatible = "fixed-clock";
93 clock-frequency = <250000000>;
97 compatible = "fixed-clock";
99 clock-frequency = <625000000>;
103 compatible = "simple-bus";
104 #address-cells = <2>;
108 gic: interrupt-controller@600300000 {
109 compatible = "arm,gic-v3";
110 #interrupt-cells = <3>;
111 #address-cells = <2>;
113 interrupt-controller;
114 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
115 <0x6 0x00340000 0xc0000>, /* GICR */
116 <0x6 0x00200000 0x2000>, /* GICC */
117 <0x6 0x00210000 0x2000>, /* GICV */
118 <0x6 0x00220000 0x2000>; /* GICH */
119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
122 cpu_ctrl: syscon@600000000 {
123 compatible = "microchip,sparx5-cpu-syscon", "syscon",
125 reg = <0x6 0x00000000 0xd0>;
126 mux: mux-controller {
127 compatible = "mmio-mux";
128 #mux-control-cells = <0>;
130 * SI_OWNER and SI2_OWNER in GENERAL_CTRL
131 * SPI: value 9 - (SIMC,SIBM) = 0b1001
132 * SPI2: value 6 - (SIBM,SIMC) = 0b0110
134 mux-reg-masks = <0x88 0xf0>;
138 reset: reset-controller@611010008 {
139 compatible = "microchip,sparx5-switch-reset";
140 reg = <0x6 0x11010008 0x4>;
143 cpu-syscon = <&cpu_ctrl>;
146 uart0: serial@600100000 {
147 pinctrl-0 = <&uart_pins>;
148 pinctrl-names = "default";
149 compatible = "ns16550a";
150 reg = <0x6 0x00100000 0x20>;
154 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
159 uart1: serial@600102000 {
160 pinctrl-0 = <&uart2_pins>;
161 pinctrl-names = "default";
162 compatible = "ns16550a";
163 reg = <0x6 0x00102000 0x20>;
167 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
172 spi0: spi@600104000 {
173 #address-cells = <1>;
175 compatible = "microchip,sparx5-spi";
176 reg = <0x6 0x00104000 0x40>;
181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
185 timer1: timer@600105000 {
186 compatible = "snps,dw-apb-timer";
187 reg = <0x6 0x00105000 0x1000>;
189 clock-names = "timer";
190 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
193 sdhci0: mmc@600800000 {
194 compatible = "microchip,dw-sparx5-sdhci";
196 reg = <0x6 0x00800000 0x1000>;
197 pinctrl-0 = <&emmc_pins>;
198 pinctrl-names = "default";
199 clocks = <&clks CLK_ID_AUX1>;
200 clock-names = "core";
201 assigned-clocks = <&clks CLK_ID_AUX1>;
202 assigned-clock-rates = <800000000>;
203 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
207 gpio: pinctrl@6110101e0 {
208 compatible = "microchip,sparx5-pinctrl";
209 reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
212 gpio-ranges = <&gpio 0 0 64>;
213 interrupt-controller;
214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
215 #interrupt-cells = <2>;
233 pins = "GPIO_39", "GPIO_40", "GPIO_41";
237 sgpio0_pins: sgpio-pins {
238 pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
242 sgpio1_pins: sgpio1-pins {
243 pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
247 sgpio2_pins: sgpio2-pins {
248 pins = "GPIO_30", "GPIO_31", "GPIO_32",
253 uart_pins: uart-pins {
254 pins = "GPIO_10", "GPIO_11";
258 uart2_pins: uart2-pins {
259 pins = "GPIO_26", "GPIO_27";
264 pins = "GPIO_14", "GPIO_15";
268 i2c2_pins: i2c2-pins {
269 pins = "GPIO_28", "GPIO_29";
273 emmc_pins: emmc-pins {
274 pins = "GPIO_34", "GPIO_35", "GPIO_36",
275 "GPIO_37", "GPIO_38", "GPIO_39",
276 "GPIO_40", "GPIO_41", "GPIO_42",
277 "GPIO_43", "GPIO_44", "GPIO_45",
278 "GPIO_46", "GPIO_47";
282 miim1_pins: miim1-pins {
283 pins = "GPIO_56", "GPIO_57";
287 miim2_pins: miim2-pins {
288 pins = "GPIO_58", "GPIO_59";
292 miim3_pins: miim3-pins {
293 pins = "GPIO_52", "GPIO_53";
298 sgpio0: gpio@61101036c {
299 #address-cells = <1>;
301 compatible = "microchip,sparx5-sgpio";
304 pinctrl-0 = <&sgpio0_pins>;
305 pinctrl-names = "default";
307 reset-names = "switch";
308 reg = <0x6 0x1101036c 0x100>;
310 compatible = "microchip,sparx5-sgpio-bank";
315 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
316 interrupt-controller;
317 #interrupt-cells = <3>;
320 compatible = "microchip,sparx5-sgpio-bank";
328 sgpio1: gpio@611010484 {
329 #address-cells = <1>;
331 compatible = "microchip,sparx5-sgpio";
334 pinctrl-0 = <&sgpio1_pins>;
335 pinctrl-names = "default";
337 reset-names = "switch";
338 reg = <0x6 0x11010484 0x100>;
340 compatible = "microchip,sparx5-sgpio-bank";
345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-controller;
347 #interrupt-cells = <3>;
350 compatible = "microchip,sparx5-sgpio-bank";
358 sgpio2: gpio@61101059c {
359 #address-cells = <1>;
361 compatible = "microchip,sparx5-sgpio";
364 pinctrl-0 = <&sgpio2_pins>;
365 pinctrl-names = "default";
367 reset-names = "switch";
368 reg = <0x6 0x1101059c 0x100>;
371 compatible = "microchip,sparx5-sgpio-bank";
375 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
376 interrupt-controller;
377 #interrupt-cells = <3>;
380 compatible = "microchip,sparx5-sgpio-bank";
388 i2c0: i2c@600101000 {
389 compatible = "snps,designware-i2c";
391 pinctrl-0 = <&i2c_pins>;
392 pinctrl-names = "default";
393 reg = <0x6 0x00101000 0x100>;
394 #address-cells = <1>;
396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
397 i2c-sda-hold-time-ns = <300>;
398 clock-frequency = <100000>;
402 i2c1: i2c@600103000 {
403 compatible = "snps,designware-i2c";
405 pinctrl-0 = <&i2c2_pins>;
406 pinctrl-names = "default";
407 reg = <0x6 0x00103000 0x100>;
408 #address-cells = <1>;
410 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
411 i2c-sda-hold-time-ns = <300>;
412 clock-frequency = <100000>;
416 tmon0: tmon@610508110 {
417 compatible = "microchip,sparx5-temp";
418 reg = <0x6 0x10508110 0xc>;
419 #thermal-sensor-cells = <0>;
423 mdio0: mdio@6110102b0 {
424 compatible = "mscc,ocelot-miim";
426 #address-cells = <1>;
428 reg = <0x6 0x110102b0 0x24>;
431 mdio1: mdio@6110102d4 {
432 compatible = "mscc,ocelot-miim";
434 pinctrl-0 = <&miim1_pins>;
435 pinctrl-names = "default";
436 #address-cells = <1>;
438 reg = <0x6 0x110102d4 0x24>;
441 mdio2: mdio@6110102f8 {
442 compatible = "mscc,ocelot-miim";
444 pinctrl-0 = <&miim2_pins>;
445 pinctrl-names = "default";
446 #address-cells = <1>;
448 reg = <0x6 0x110102d4 0x24>;
451 mdio3: mdio@61101031c {
452 compatible = "mscc,ocelot-miim";
454 pinctrl-0 = <&miim3_pins>;
455 pinctrl-names = "default";
456 #address-cells = <1>;
458 reg = <0x6 0x1101031c 0x24>;
461 serdes: serdes@10808000 {
462 compatible = "microchip,sparx5-serdes";
465 reg = <0x6 0x10808000 0x5d0000>;
468 switch: switch@0x600000000 {
469 compatible = "microchip,sparx5-switch";
470 reg = <0x6 0 0x401000>,
471 <0x6 0x10004000 0x7fc000>,
472 <0x6 0x11010000 0xaf0000>;
473 reg-names = "cpu", "dev", "gcb";
474 interrupt-names = "xtr", "fdma", "ptp";
475 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
479 reset-names = "switch";