1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Ben Lok <ben.lok@mediatek.com>
5 * Macpaul Lin <macpaul.lin@mediatek.com>
10 #include "mt6359.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
16 #include <dt-bindings/spmi/spmi.h>
17 #include <dt-bindings/usb/pd.h>
20 model = "MediaTek Genio 1200 EVK-P1V2-EMMC";
21 compatible = "mediatek,mt8395-evk", "mediatek,mt8395",
30 stdout-path = "serial0:921600n8";
35 compatible = "linaro,optee-tz";
41 device_type = "memory";
42 reg = <0 0x40000000 0x2 0x00000000>;
51 * 12 MiB reserved for OP-TEE (BL32)
52 * +-----------------------+ 0x43e0_0000
54 * +-----------------------+ 0x43c0_0000
56 * + TZDRAM +--------------+ 0x4340_0000
58 * +-----------------------+ 0x4320_0000
60 optee_reserved: optee@43200000 {
62 reg = <0 0x43200000 0 0x00c00000>;
65 scp_mem: memory@50000000 {
66 compatible = "shared-dma-pool";
67 reg = <0 0x50000000 0 0x2900000>;
71 vpu_mem: memory@53000000 {
72 compatible = "shared-dma-pool";
73 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
76 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
77 bl31_secmon_mem: memory@54600000 {
79 reg = <0 0x54600000 0x0 0x200000>;
82 snd_dma_mem: memory@60000000 {
83 compatible = "shared-dma-pool";
84 reg = <0 0x60000000 0 0x1100000>;
88 apu_mem: memory@62000000 {
89 compatible = "shared-dma-pool";
90 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
94 backlight_lcd0: backlight-lcd0 {
95 compatible = "pwm-backlight";
96 pwms = <&disp_pwm0 0 500000>;
97 enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>;
98 brightness-levels = <0 1023>;
99 num-interpolated-steps = <1023>;
100 default-brightness-level = <576>;
103 backlight_lcd1: backlight-lcd1 {
104 compatible = "pwm-backlight";
105 pwms = <&disp_pwm1 0 500000>;
106 enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
107 brightness-levels = <0 1023>;
108 num-interpolated-steps = <1023>;
109 default-brightness-level = <576>;
113 compatible = "fixed-clock";
115 clock-frequency = <20000000>;
116 clock-output-names = "can-clk";
119 edp_panel_fixed_3v3: regulator-0 {
120 compatible = "regulator-fixed";
121 regulator-name = "edp_panel_3v3";
122 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <3300000>;
125 gpio = <&pio 6 GPIO_ACTIVE_HIGH>;
126 pinctrl-names = "default";
127 pinctrl-0 = <&edp_panel_3v3_en_pins>;
130 edp_panel_fixed_12v: regulator-1 {
131 compatible = "regulator-fixed";
132 regulator-name = "edp_backlight_12v";
133 regulator-min-microvolt = <12000000>;
134 regulator-max-microvolt = <12000000>;
136 gpio = <&pio 96 GPIO_ACTIVE_HIGH>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&edp_panel_12v_en_pins>;
142 compatible = "gpio-keys";
146 debounce-interval = <100>;
147 gpios = <&pio 106 GPIO_ACTIVE_LOW>;
149 linux,code = <KEY_VOLUMEUP>;
153 wifi_fixed_3v3: regulator-2 {
154 compatible = "regulator-fixed";
155 regulator-name = "wifi_3v3";
156 regulator-min-microvolt = <3300000>;
157 regulator-max-microvolt = <3300000>;
158 gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pwm0_default_pins>;
171 wakeup-delay-ms = <200>;
175 phy-mode ="rgmii-rxid";
176 phy-handle = <ð_phy0>;
177 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
178 snps,reset-delays-us = <0 10000 10000>;
179 mediatek,tx-delay-ps = <2030>;
181 pinctrl-names = "default", "sleep";
182 pinctrl-0 = <ð_default_pins>;
183 pinctrl-1 = <ð_sleep_pins>;
187 compatible = "snps,dwmac-mdio";
188 #address-cells = <1>;
190 eth_phy0: eth-phy0@1 {
191 compatible = "ethernet-phy-id001c.c916";
198 clock-frequency = <400000>;
199 pinctrl-0 = <&i2c0_pins>;
200 pinctrl-names = "default";
205 clock-frequency = <400000>;
206 pinctrl-0 = <&i2c1_pins>;
207 pinctrl-names = "default";
211 compatible = "goodix,gt9271";
213 interrupt-parent = <&pio>;
214 interrupts = <132 IRQ_TYPE_EDGE_RISING>;
215 irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>;
216 reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>;
217 AVDD28-supply = <&mt6360_ldo1>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&touch_pins>;
224 clock-frequency = <400000>;
225 pinctrl-0 = <&i2c2_pins>;
226 pinctrl-names = "default";
231 clock-frequency = <400000>;
232 pinctrl-0 = <&i2c6_pins>;
233 pinctrl-names = "default";
234 #address-cells = <1>;
239 compatible = "mediatek,mt6360";
241 interrupt-parent = <&pio>;
242 interrupts = <128 IRQ_TYPE_EDGE_FALLING>;
243 interrupt-names = "IRQB";
244 interrupt-controller;
245 #interrupt-cells = <1>;
246 pinctrl-0 = <&mt6360_pins>;
249 compatible = "mediatek,mt6360-chg";
250 richtek,vinovp-microvolt = <14500000>;
252 otg_vbus_regulator: usb-otg-vbus-regulator {
253 regulator-name = "usb-otg-vbus";
254 regulator-min-microvolt = <4425000>;
255 regulator-max-microvolt = <5825000>;
260 compatible = "mediatek,mt6360-regulator";
261 LDO_VIN3-supply = <&mt6360_buck2>;
263 mt6360_buck1: buck1 {
264 regulator-name = "emi_vdd2";
265 regulator-min-microvolt = <300000>;
266 regulator-max-microvolt = <1300000>;
267 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
273 mt6360_buck2: buck2 {
274 regulator-name = "emi_vddq";
275 regulator-min-microvolt = <300000>;
276 regulator-max-microvolt = <1300000>;
277 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
284 regulator-name = "tp1_p3v0";
285 regulator-min-microvolt = <3300000>;
286 regulator-max-microvolt = <3300000>;
287 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
293 regulator-name = "panel1_p1v8";
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <1800000>;
296 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
301 regulator-name = "vmc_pmu";
302 regulator-min-microvolt = <1200000>;
303 regulator-max-microvolt = <3600000>;
304 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
309 regulator-name = "vmch_pmu";
310 regulator-min-microvolt = <2700000>;
311 regulator-max-microvolt = <3600000>;
312 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
316 /* This is a measure point, which name is mt6360_ldo1 on schematic */
318 regulator-name = "mt6360_ldo1";
319 regulator-min-microvolt = <500000>;
320 regulator-max-microvolt = <2100000>;
321 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
326 regulator-name = "emi_vmddr_en";
327 regulator-min-microvolt = <500000>;
328 regulator-max-microvolt = <2100000>;
329 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
338 domain-supply = <&mt6315_7_vbuck1>;
343 pinctrl-names = "default", "state_uhs";
344 pinctrl-0 = <&mmc0_default_pins>;
345 pinctrl-1 = <&mmc0_uhs_pins>;
347 max-frequency = <200000000>;
354 hs400-ds-delay = <0x14c11>;
355 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
356 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
361 pinctrl-names = "default", "state_uhs";
362 pinctrl-0 = <&mmc1_default_pins>;
363 pinctrl-1 = <&mmc1_uhs_pins>;
365 max-frequency = <200000000>;
371 vmmc-supply = <&mt6360_ldo5>;
372 vqmmc-supply = <&mt6360_ldo3>;
377 &mt6359_vaud18_ldo_reg {
381 &mt6359_vbbck_ldo_reg {
386 &mt6359_vcamio_ldo_reg {
390 &mt6359_vcn33_2_bt_ldo_reg {
391 regulator-min-microvolt = <3300000>;
392 regulator-max-microvolt = <3300000>;
395 &mt6359_vcore_buck_reg {
399 &mt6359_vgpu11_buck_reg {
403 &mt6359_vpu_buck_reg {
407 &mt6359_vrf12_ldo_reg {
412 mediatek,mic-type-0 = <1>; /* ACC */
413 mediatek,mic-type-1 = <3>; /* DCC */
414 mediatek,mic-type-2 = <1>; /* ACC */
418 pinctrl-names = "default", "idle";
419 pinctrl-0 = <&pcie0_default_pins>;
420 pinctrl-1 = <&pcie0_idle_pins>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&pcie1_default_pins>;
435 audio_default_pins: audio-default-pins {
437 pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>,
438 <PINMUX_GPIO62__FUNC_DMIC1_DAT>,
439 <PINMUX_GPIO65__FUNC_PCM_DO>,
440 <PINMUX_GPIO66__FUNC_PCM_CLK>,
441 <PINMUX_GPIO67__FUNC_PCM_DI>,
442 <PINMUX_GPIO68__FUNC_PCM_SYNC>,
443 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
444 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
445 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
446 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
447 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
448 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
449 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>;
453 disp_pwm1_default_pins: disp-pwm1-default-pins {
455 pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>;
459 edp_panel_12v_en_pins: edp-panel-12v-en-pins {
461 pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
466 edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {
468 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
473 eth_default_pins: eth-default-pins {
475 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
476 <PINMUX_GPIO86__FUNC_GBE_RXC>,
477 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
478 <PINMUX_GPIO88__FUNC_GBE_TXEN>;
479 drive-strength = <MTK_DRIVE_8mA>;
483 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
484 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
489 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
490 <PINMUX_GPIO92__FUNC_GPIO92>;
495 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
496 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
497 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
498 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
502 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
503 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
504 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
505 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
506 drive-strength = <MTK_DRIVE_8mA>;
510 eth_sleep_pins: eth-sleep-pins {
512 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
513 <PINMUX_GPIO86__FUNC_GPIO86>,
514 <PINMUX_GPIO87__FUNC_GPIO87>,
515 <PINMUX_GPIO88__FUNC_GPIO88>;
519 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
520 <PINMUX_GPIO90__FUNC_GPIO90>;
526 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
527 <PINMUX_GPIO82__FUNC_GPIO82>,
528 <PINMUX_GPIO83__FUNC_GPIO83>,
529 <PINMUX_GPIO84__FUNC_GPIO84>;
533 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
534 <PINMUX_GPIO78__FUNC_GPIO78>,
535 <PINMUX_GPIO79__FUNC_GPIO79>,
536 <PINMUX_GPIO80__FUNC_GPIO80>;
540 gpio_key_pins: gpio-keys-pins {
542 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
548 i2c0_pins: i2c0-pins {
550 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
551 <PINMUX_GPIO9__FUNC_SCL0>;
552 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
553 drive-strength-microamp = <1000>;
557 i2c1_pins: i2c1-pins {
559 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
560 <PINMUX_GPIO11__FUNC_SCL1>;
561 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
562 drive-strength-microamp = <1000>;
566 i2c2_pins: i2c2-pins {
568 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
569 <PINMUX_GPIO13__FUNC_SCL2>;
570 bias-pull-up = <MTK_PULL_SET_RSEL_111>;
571 drive-strength = <MTK_DRIVE_6mA>;
575 i2c6_pins: i2c6-pins {
577 pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
578 <PINMUX_GPIO26__FUNC_SCL6>;
583 mmc0_default_pins: mmc0-default-pins {
585 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
586 drive-strength = <MTK_DRIVE_6mA>;
587 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
591 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
592 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
593 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
594 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
595 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
596 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
597 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
598 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
599 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
601 drive-strength = <MTK_DRIVE_6mA>;
602 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
606 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
607 drive-strength = <MTK_DRIVE_6mA>;
608 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
612 mmc0_uhs_pins: mmc0-uhs-pins {
614 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
615 drive-strength = <MTK_DRIVE_8mA>;
616 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
620 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
621 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
622 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
623 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
624 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
625 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
626 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
627 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
628 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
630 drive-strength = <MTK_DRIVE_8mA>;
631 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
635 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
636 drive-strength = <MTK_DRIVE_8mA>;
637 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
641 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
642 drive-strength = <MTK_DRIVE_8mA>;
643 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
647 mmc1_default_pins: mmc1-default-pins {
649 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
650 drive-strength = <MTK_DRIVE_8mA>;
651 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
655 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
656 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
657 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
658 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
659 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
661 drive-strength = <MTK_DRIVE_8mA>;
662 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
666 mmc1_uhs_pins: mmc1-uhs-pins {
668 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
669 drive-strength = <MTK_DRIVE_8mA>;
670 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
674 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
675 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
676 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
677 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
678 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
680 drive-strength = <MTK_DRIVE_8mA>;
681 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
685 mt6360_pins: mt6360-pins {
687 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>,
688 <PINMUX_GPIO128__FUNC_GPIO128>;
694 pcie0_default_pins: pcie0-default-pins {
696 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
697 <PINMUX_GPIO20__FUNC_PERSTN>,
698 <PINMUX_GPIO21__FUNC_CLKREQN>;
703 pcie0_idle_pins: pcie0-idle-pins {
705 pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
711 pcie1_default_pins: pcie1-default-pins {
713 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
714 <PINMUX_GPIO23__FUNC_CLKREQN_1>,
715 <PINMUX_GPIO24__FUNC_WAKEN_1>;
720 pwm0_default_pins: pwm0-default-pins {
722 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>;
726 spi1_pins: spi1-pins {
728 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
729 <PINMUX_GPIO137__FUNC_SPIM1_CLK>,
730 <PINMUX_GPIO138__FUNC_SPIM1_MO>,
731 <PINMUX_GPIO139__FUNC_SPIM1_MI>;
736 spi2_pins: spi-pins {
738 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
739 <PINMUX_GPIO141__FUNC_SPIM2_CLK>,
740 <PINMUX_GPIO142__FUNC_SPIM2_MO>,
741 <PINMUX_GPIO143__FUNC_SPIM2_MI>;
746 touch_pins: touch-pins {
748 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>;
754 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>;
759 uart0_pins: uart0-pins {
761 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
762 <PINMUX_GPIO99__FUNC_URXD0>;
766 uart1_pins: uart1-pins {
768 pinmux = <PINMUX_GPIO100__FUNC_URTS1>,
769 <PINMUX_GPIO101__FUNC_UCTS1>,
770 <PINMUX_GPIO102__FUNC_UTXD1>,
771 <PINMUX_GPIO103__FUNC_URXD1>;
777 interrupt-parent = <&pio>;
778 interrupts = <222 IRQ_TYPE_LEVEL_HIGH>;
782 memory-region = <&scp_mem>;
787 pinctrl-0 = <&spi1_pins>;
788 pinctrl-names = "default";
789 mediatek,pad-select = <0>;
790 #address-cells = <1>;
793 cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>;
796 compatible = "microchip,mcp2518fd";
799 spi-max-frequency = <20000000>;
800 interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>;
801 vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
802 xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
807 pinctrl-0 = <&spi2_pins>;
808 pinctrl-names = "default";
809 mediatek,pad-select = <0>;
810 #address-cells = <1>;
816 #address-cells = <2>;
820 compatible = "mediatek,mt6315-regulator";
821 reg = <0x6 SPMI_USID>;
824 mt6315_6_vbuck1: vbuck1 {
825 regulator-compatible = "vbuck1";
826 regulator-name = "Vbcpu";
827 regulator-min-microvolt = <300000>;
828 regulator-max-microvolt = <1193750>;
829 regulator-enable-ramp-delay = <256>;
830 regulator-allowed-modes = <0 1 2>;
837 compatible = "mediatek,mt6315-regulator";
838 reg = <0x7 SPMI_USID>;
841 mt6315_7_vbuck1: vbuck1 {
842 regulator-compatible = "vbuck1";
843 regulator-name = "Vgpu";
844 regulator-min-microvolt = <300000>;
845 regulator-max-microvolt = <1193750>;
846 regulator-enable-ramp-delay = <256>;
847 regulator-allowed-modes = <0 1 2>;
870 pinctrl-0 = <&uart0_pins>;
871 pinctrl-names = "default";
876 pinctrl-0 = <&uart1_pins>;
877 pinctrl-names = "default";
890 vusb33-supply = <&mt6359_vusb_ldo_reg>;
895 vusb33-supply = <&mt6359_vusb_ldo_reg>;
900 vusb33-supply = <&mt6359_vusb_ldo_reg>;