arch/arm64/boot/dts/mediatek/mt8365.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * (C) 2018 MediaTek Inc.
   4  * Copyright (C) 2022 BayLibre SAS
   5  * Fabien Parent <fparent@baylibre.com>
   6  * Bernhard Rosenkränzer <bero@baylibre.com>
   7  */
   8 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/phy/phy.h>
  12 #include <dt-bindings/power/mediatek,mt8365-power.h>
  13
  14 / {
  15         compatible = "mediatek,mt8365";
  16         interrupt-parent = <&sysirq>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24         cluster0_opp: opp-table-0 {
  25                 compatible = "operating-points-v2";
  26                 opp-shared;
  27
  28                 opp-850000000 {
  29                         opp-hz = /bits/ 64 <850000000>;
  30                         opp-microvolt = <650000>;
  31                 };
  32
  33                 opp-918000000 {
  34                         opp-hz = /bits/ 64 <918000000>;
  35                         opp-microvolt = <668750>;
  36                 };
  37
  38                 opp-987000000 {
  39                         opp-hz = /bits/ 64 <987000000>;
  40                         opp-microvolt = <687500>;
  41                 };
  42
  43                 opp-1056000000 {
  44                         opp-hz = /bits/ 64 <1056000000>;
  45                         opp-microvolt = <706250>;
  46                 };
  47
  48                 opp-1125000000 {
  49                         opp-hz = /bits/ 64 <1125000000>;
  50                         opp-microvolt = <725000>;
  51                 };
  52
  53                 opp-1216000000 {
  54                         opp-hz = /bits/ 64 <1216000000>;
  55                         opp-microvolt = <750000>;
  56                 };
  57
  58                 opp-1308000000 {
  59                         opp-hz = /bits/ 64 <1308000000>;
  60                         opp-microvolt = <775000>;
  61                 };
  62
  63                 opp-1400000000 {
  64                         opp-hz = /bits/ 64 <1400000000>;
  65                         opp-microvolt = <800000>;
  66                 };
  67
  68                 opp-1466000000 {
  69                         opp-hz = /bits/ 64 <1466000000>;
  70                         opp-microvolt = <825000>;
  71                 };
  72
  73                 opp-1533000000 {
  74                         opp-hz = /bits/ 64 <1533000000>;
  75                         opp-microvolt = <850000>;
  76                 };
  77
  78                 opp-1633000000 {
  79                         opp-hz = /bits/ 64 <1633000000>;
  80                         opp-microvolt = <887500>;
  81                 };
  82
  83                 opp-1700000000 {
  84                         opp-hz = /bits/ 64 <1700000000>;
  85                         opp-microvolt = <912500>;
  86                 };
  87
  88                 opp-1767000000 {
  89                         opp-hz = /bits/ 64 <1767000000>;
  90                         opp-microvolt = <937500>;
  91                 };
  92
  93                 opp-1834000000 {
  94                         opp-hz = /bits/ 64 <1834000000>;
  95                         opp-microvolt = <962500>;
  96                 };
  97
  98                 opp-1917000000 {
  99                         opp-hz = /bits/ 64 <1917000000>;
 100                         opp-microvolt = <993750>;
 101                 };
 102
 103                 opp-2001000000 {
 104                         opp-hz = /bits/ 64 <2001000000>;
 105                         opp-microvolt = <1025000>;
 106                 };
 107         };
 108
 109                 cpu-map {
 110                         cluster0 {
 111                                 core0 {
 112                                         cpu = <&cpu0>;
 113                                 };
 114                                 core1 {
 115                                         cpu = <&cpu1>;
 116                                 };
 117                                 core2 {
 118                                         cpu = <&cpu2>;
 119                                 };
 120                                 core3 {
 121                                         cpu = <&cpu3>;
 122                                 };
 123                         };
 124                 };
 125
 126                 cpu0: cpu@0 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53";
 129                         reg = <0x0>;
 130                         #cooling-cells = <2>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
 133                         i-cache-size = <0x8000>;
 134                         i-cache-line-size = <64>;
 135                         i-cache-sets = <256>;
 136                         d-cache-size = <0x8000>;
 137                         d-cache-line-size = <64>;
 138                         d-cache-sets = <256>;
 139                         next-level-cache = <&l2>;
 140                         clocks = <&mcucfg CLK_MCU_BUS_SEL>,
 141                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 142                         clock-names = "cpu", "intermediate";
 143                         operating-points-v2 = <&cluster0_opp>;
 144                 };
 145
 146                 cpu1: cpu@1 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53";
 149                         reg = <0x1>;
 150                         #cooling-cells = <2>;
 151                         enable-method = "psci";
 152                         cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
 153                         i-cache-size = <0x8000>;
 154                         i-cache-line-size = <64>;
 155                         i-cache-sets = <256>;
 156                         d-cache-size = <0x8000>;
 157                         d-cache-line-size = <64>;
 158                         d-cache-sets = <256>;
 159                         next-level-cache = <&l2>;
 160                         clocks = <&mcucfg CLK_MCU_BUS_SEL>,
 161                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 162                         clock-names = "cpu", "intermediate", "armpll";
 163                         operating-points-v2 = <&cluster0_opp>;
 164                 };
 165
 166                 cpu2: cpu@2 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53";
 169                         reg = <0x2>;
 170                         #cooling-cells = <2>;
 171                         enable-method = "psci";
 172                         cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
 173                         i-cache-size = <0x8000>;
 174                         i-cache-line-size = <64>;
 175                         i-cache-sets = <256>;
 176                         d-cache-size = <0x8000>;
 177                         d-cache-line-size = <64>;
 178                         d-cache-sets = <256>;
 179                         next-level-cache = <&l2>;
 180                         clocks = <&mcucfg CLK_MCU_BUS_SEL>,
 181                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 182                         clock-names = "cpu", "intermediate", "armpll";
 183                         operating-points-v2 = <&cluster0_opp>;
 184                 };
 185
 186                 cpu3: cpu@3 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a53";
 189                         reg = <0x3>;
 190                         #cooling-cells = <2>;
 191                         enable-method = "psci";
 192                         cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
 193                         i-cache-size = <0x8000>;
 194                         i-cache-line-size = <64>;
 195                         i-cache-sets = <256>;
 196                         d-cache-size = <0x8000>;
 197                         d-cache-line-size = <64>;
 198                         d-cache-sets = <256>;
 199                         next-level-cache = <&l2>;
 200                         clocks = <&mcucfg CLK_MCU_BUS_SEL>,
 201                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 202                         clock-names = "cpu", "intermediate", "armpll";
 203                         operating-points-v2 = <&cluster0_opp>;
 204                 };
 205
 206                 idle-states {
 207                         entry-method = "psci";
 208
 209                         CPU_MCDI: cpu-mcdi {
 210                                 compatible = "arm,idle-state";
 211                                 local-timer-stop;
 212                                 arm,psci-suspend-param = <0x00010001>;
 213                                 entry-latency-us = <300>;
 214                                 exit-latency-us = <200>;
 215                                 min-residency-us = <1000>;
 216                         };
 217
 218                         CLUSTER_MCDI: cluster-mcdi {
 219                                 compatible = "arm,idle-state";
 220                                 local-timer-stop;
 221                                 arm,psci-suspend-param = <0x01010001>;
 222                                 entry-latency-us = <350>;
 223                                 exit-latency-us = <250>;
 224                                 min-residency-us = <1200>;
 225                         };
 226
 227                         CLUSTER_DPIDLE: cluster-dpidle {
 228                                 compatible = "arm,idle-state";
 229                                 local-timer-stop;
 230                                 arm,psci-suspend-param = <0x01010004>;
 231                                 entry-latency-us = <300>;
 232                                 exit-latency-us = <800>;
 233                                 min-residency-us = <3300>;
 234                         };
 235                 };
 236
 237                 l2: l2-cache {
 238                         compatible = "cache";
 239                         cache-level = <2>;
 240                         cache-size = <0x80000>;
 241                         cache-line-size = <64>;
 242                         cache-sets = <512>;
 243                         cache-unified;
 244                 };
 245         };
 246
 247         clk26m: oscillator {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <26000000>;
 251                 clock-output-names = "clk26m";
 252         };
 253
 254         psci {
 255                 compatible = "arm,psci-1.0";
 256                 method = "smc";
 257         };
 258
 259         soc {
 260                 #address-cells = <2>;
 261                 #size-cells = <2>;
 262                 compatible = "simple-bus";
 263                 ranges;
 264
 265                 gic: interrupt-controller@c000000 {
 266                         compatible = "arm,gic-v3";
 267                         #interrupt-cells = <3>;
 268                         interrupt-parent = <&gic>;
 269                         interrupt-controller;
 270                         reg = <0 0x0c000000 0 0x10000>, /* GICD */
 271                               <0 0x0c080000 0 0x80000>, /* GICR */
 272                               <0 0x0c400000 0 0x2000>,  /* GICC */
 273                               <0 0x0c410000 0 0x1000>,  /* GICH */
 274                               <0 0x0c420000 0 0x2000>;  /* GICV */
 275
 276                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 277                 };
 278
 279                 topckgen: syscon@10000000 {
 280                         compatible = "mediatek,mt8365-topckgen", "syscon";
 281                         reg = <0 0x10000000 0 0x1000>;
 282                         #clock-cells = <1>;
 283                 };
 284
 285                 infracfg: syscon@10001000 {
 286                         compatible = "mediatek,mt8365-infracfg", "syscon";
 287                         reg = <0 0x10001000 0 0x1000>;
 288                         #clock-cells = <1>;
 289                 };
 290
 291                 pericfg: syscon@10003000 {
 292                         compatible = "mediatek,mt8365-pericfg", "syscon";
 293                         reg = <0 0x10003000 0 0x1000>;
 294                         #clock-cells = <1>;
 295                 };
 296
 297                 syscfg_pctl: syscfg-pctl@10005000 {
 298                         compatible = "mediatek,mt8365-syscfg", "syscon";
 299                         reg = <0 0x10005000 0 0x1000>;
 300                 };
 301
 302                 scpsys: syscon@10006000 {
 303                         compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
 304                         reg = <0 0x10006000 0 0x1000>;
 305                         #power-domain-cells = <1>;
 306
 307                         /* System Power Manager */
 308                         spm: power-controller {
 309                                 compatible = "mediatek,mt8365-power-controller";
 310                                 #address-cells = <1>;
 311                                 #size-cells = <0>;
 312                                 #power-domain-cells = <1>;
 313
 314                                 /* power domains of the SoC */
 315                                 power-domain@MT8365_POWER_DOMAIN_MM {
 316                                         reg = <MT8365_POWER_DOMAIN_MM>;
 317                                         clocks = <&topckgen CLK_TOP_MM_SEL>,
 318                                                  <&mmsys CLK_MM_MM_SMI_COMMON>,
 319                                                  <&mmsys CLK_MM_MM_SMI_COMM0>,
 320                                                  <&mmsys CLK_MM_MM_SMI_COMM1>,
 321                                                  <&mmsys CLK_MM_MM_SMI_LARB0>;
 322                                         clock-names = "mm", "mm-0", "mm-1",
 323                                                       "mm-2", "mm-3";
 324                                         #power-domain-cells = <0>;
 325                                         mediatek,infracfg = <&infracfg>;
 326                                         mediatek,infracfg-nao = <&infracfg_nao>;
 327                                         #address-cells = <1>;
 328                                         #size-cells = <0>;
 329
 330                                         power-domain@MT8365_POWER_DOMAIN_CAM {
 331                                                 reg = <MT8365_POWER_DOMAIN_CAM>;
 332                                                 clocks = <&camsys CLK_CAM_LARB2>,
 333                                                          <&camsys CLK_CAM_SENIF>,
 334                                                          <&camsys CLK_CAMSV0>,
 335                                                          <&camsys CLK_CAMSV1>,
 336                                                          <&camsys CLK_CAM_FDVT>,
 337                                                          <&camsys CLK_CAM_WPE>;
 338                                                 clock-names = "cam-0", "cam-1",
 339                                                               "cam-2", "cam-3",
 340                                                               "cam-4", "cam-5";
 341                                                 #power-domain-cells = <0>;
 342                                                 mediatek,infracfg = <&infracfg>;
 343                                                 mediatek,smi = <&smi_common>;
 344                                         };
 345
 346                                         power-domain@MT8365_POWER_DOMAIN_VDEC {
 347                                                 reg = <MT8365_POWER_DOMAIN_VDEC>;
 348                                                 #power-domain-cells = <0>;
 349                                                 mediatek,smi = <&smi_common>;
 350                                         };
 351
 352                                         power-domain@MT8365_POWER_DOMAIN_VENC {
 353                                                 reg = <MT8365_POWER_DOMAIN_VENC>;
 354                                                 #power-domain-cells = <0>;
 355                                                 mediatek,smi = <&smi_common>;
 356                                         };
 357
 358                                         power-domain@MT8365_POWER_DOMAIN_APU {
 359                                                 reg = <MT8365_POWER_DOMAIN_APU>;
 360                                                 clocks = <&infracfg CLK_IFR_APU_AXI>,
 361                                                          <&apu CLK_APU_IPU_CK>,
 362                                                          <&apu CLK_APU_AXI>,
 363                                                          <&apu CLK_APU_JTAG>,
 364                                                          <&apu CLK_APU_IF_CK>,
 365                                                          <&apu CLK_APU_EDMA>,
 366                                                          <&apu CLK_APU_AHB>;
 367                                                 clock-names = "apu", "apu-0",
 368                                                               "apu-1", "apu-2",
 369                                                               "apu-3", "apu-4",
 370                                                               "apu-5";
 371                                                 #power-domain-cells = <0>;
 372                                                 mediatek,infracfg = <&infracfg>;
 373                                                 mediatek,smi = <&smi_common>;
 374                                         };
 375                                 };
 376
 377                                 power-domain@MT8365_POWER_DOMAIN_CONN {
 378                                         reg = <MT8365_POWER_DOMAIN_CONN>;
 379                                         clocks = <&topckgen CLK_TOP_CONN_32K>,
 380                                                  <&topckgen CLK_TOP_CONN_26M>;
 381                                         clock-names = "conn", "conn1";
 382                                         #power-domain-cells = <0>;
 383                                         mediatek,infracfg = <&infracfg>;
 384                                 };
 385
 386                                 power-domain@MT8365_POWER_DOMAIN_MFG {
 387                                         reg = <MT8365_POWER_DOMAIN_MFG>;
 388                                         clocks = <&topckgen CLK_TOP_MFG_SEL>;
 389                                         clock-names = "mfg";
 390                                         #power-domain-cells = <0>;
 391                                         mediatek,infracfg = <&infracfg>;
 392                                 };
 393
 394                                 power-domain@MT8365_POWER_DOMAIN_AUDIO {
 395                                         reg = <MT8365_POWER_DOMAIN_AUDIO>;
 396                                         clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 397                                                  <&infracfg CLK_IFR_AUDIO>,
 398                                                  <&infracfg CLK_IFR_AUD_26M_BK>;
 399                                         clock-names = "audio", "audio1", "audio2";
 400                                         #power-domain-cells = <0>;
 401                                         mediatek,infracfg = <&infracfg>;
 402                                 };
 403
 404                                 power-domain@MT8365_POWER_DOMAIN_DSP {
 405                                         reg = <MT8365_POWER_DOMAIN_DSP>;
 406                                         clocks = <&topckgen CLK_TOP_DSP_SEL>,
 407                                                  <&topckgen CLK_TOP_DSP_26M>;
 408                                         clock-names = "dsp", "dsp1";
 409                                         #power-domain-cells = <0>;
 410                                         mediatek,infracfg = <&infracfg>;
 411                                 };
 412                         };
 413                 };
 414
 415                 watchdog: watchdog@10007000 {
 416                         compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
 417                         reg = <0 0x10007000 0 0x100>;
 418                         #reset-cells = <1>;
 419                 };
 420
 421                 pio: pinctrl@1000b000 {
 422                         compatible = "mediatek,mt8365-pinctrl";
 423                         reg = <0 0x1000b000 0 0x1000>;
 424                         mediatek,pctl-regmap = <&syscfg_pctl>;
 425                         gpio-controller;
 426                         #gpio-cells = <2>;
 427                         interrupt-controller;
 428                         #interrupt-cells = <2>;
 429                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 430                 };
 431
 432                 apmixedsys: syscon@1000c000 {
 433                         compatible = "mediatek,mt8365-apmixedsys", "syscon";
 434                         reg = <0 0x1000c000 0 0x1000>;
 435                         #clock-cells = <1>;
 436                 };
 437
 438                 pwrap: pwrap@1000d000 {
 439                         compatible = "mediatek,mt8365-pwrap";
 440                         reg = <0 0x1000d000 0 0x1000>;
 441                         reg-names = "pwrap";
 442                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
 444                                  <&infracfg CLK_IFR_PMIC_AP>,
 445                                  <&infracfg CLK_IFR_PWRAP_SYS>,
 446                                  <&infracfg CLK_IFR_PWRAP_TMR>;
 447                         clock-names = "spi", "wrap", "sys", "tmr";
 448                 };
 449
 450                 keypad: keypad@10010000 {
 451                         compatible = "mediatek,mt6779-keypad";
 452                         reg = <0 0x10010000 0 0x1000>;
 453                         wakeup-source;
 454                         interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
 455                         clocks = <&clk26m>;
 456                         clock-names = "kpd";
 457                         status = "disabled";
 458                 };
 459
 460                 mcucfg: syscon@10200000 {
 461                         compatible = "mediatek,mt8365-mcucfg", "syscon";
 462                         reg = <0 0x10200000 0 0x2000>;
 463                         #clock-cells = <1>;
 464                 };
 465
 466                 sysirq: interrupt-controller@10200a80 {
 467                         compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
 468                         interrupt-controller;
 469                         #interrupt-cells = <3>;
 470                         interrupt-parent = <&gic>;
 471                         reg = <0 0x10200a80 0 0x20>;
 472                 };
 473
 474                 iommu: iommu@10205000 {
 475                         compatible = "mediatek,mt8365-m4u";
 476                         reg = <0 0x10205000 0 0x1000>;
 477                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
 478                         mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>;
 479                         #iommu-cells = <1>;
 480                 };
 481
 482                 infracfg_nao: infracfg@1020e000 {
 483                         compatible = "mediatek,mt8365-infracfg", "syscon";
 484                         reg = <0 0x1020e000 0 0x1000>;
 485                         #clock-cells = <1>;
 486                 };
 487
 488                 rng: rng@1020f000 {
 489                         compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
 490                         reg = <0 0x1020f000 0 0x100>;
 491                         clocks = <&infracfg CLK_IFR_TRNG>;
 492                         clock-names = "rng";
 493                 };
 494
 495                 apdma: dma-controller@11000280 {
 496                         compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
 497                         reg = <0 0x11000280 0 0x80>,
 498                               <0 0x11000300 0 0x80>,
 499                               <0 0x11000380 0 0x80>,
 500                               <0 0x11000400 0 0x80>,
 501                               <0 0x11000580 0 0x80>,
 502                               <0 0x11000600 0 0x80>;
 503                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
 504                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
 505                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
 506                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
 507                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
 508                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 509                         dma-requests = <6>;
 510                         clocks = <&infracfg CLK_IFR_AP_DMA>;
 511                         clock-names = "apdma";
 512                         #dma-cells = <1>;
 513                 };
 514
 515                 uart0: serial@11002000 {
 516                         compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
 517                         reg = <0 0x11002000 0 0x1000>;
 518                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
 519                         clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
 520                         clock-names = "baud", "bus";
 521                         dmas = <&apdma 0>, <&apdma 1>;
 522                         dma-names = "tx", "rx";
 523                         status = "disabled";
 524                 };
 525
 526                 uart1: serial@11003000 {
 527                         compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
 528                         reg = <0 0x11003000 0 0x1000>;
 529                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
 530                         clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
 531                         clock-names = "baud", "bus";
 532                         dmas = <&apdma 2>, <&apdma 3>;
 533                         dma-names = "tx", "rx";
 534                         status = "disabled";
 535                 };
 536
 537                 uart2: serial@11004000 {
 538                         compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
 539                         reg = <0 0x11004000 0 0x1000>;
 540                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
 541                         clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
 542                         clock-names = "baud", "bus";
 543                         dmas = <&apdma 4>, <&apdma 5>;
 544                         dma-names = "tx", "rx";
 545                         status = "disabled";
 546                 };
 547
 548                 pwm: pwm@11006000 {
 549                         compatible = "mediatek,mt8365-pwm";
 550                         reg = <0 0x11006000 0 0x1000>;
 551                         #pwm-cells = <2>;
 552                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 553                         clocks = <&infracfg CLK_IFR_PWM_HCLK>,
 554                                  <&infracfg CLK_IFR_PWM>,
 555                                  <&infracfg CLK_IFR_PWM1>,
 556                                  <&infracfg CLK_IFR_PWM2>,
 557                                  <&infracfg CLK_IFR_PWM3>;
 558                         clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
 559                 };
 560
 561                 i2c0: i2c@11007000 {
 562                         compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
 563                         reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
 564                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
 565                         clock-div = <1>;
 566                         clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
 567                         clock-names = "main", "dma";
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                         status = "disabled";
 571                 };
 572
 573                 i2c1: i2c@11008000 {
 574                         compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
 575                         reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
 576                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
 577                         clock-div = <1>;
 578                         clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
 579                         clock-names = "main", "dma";
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         status = "disabled";
 583                 };
 584
 585                 i2c2: i2c@11009000 {
 586                         compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
 587                         reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
 588                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
 589                         clock-div = <1>;
 590                         clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
 591                         clock-names = "main", "dma";
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         status = "disabled";
 595                 };
 596
 597                 spi: spi@1100a000 {
 598                         compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
 599                         reg = <0 0x1100a000 0 0x100>;
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
 603                         clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 604                                  <&topckgen CLK_TOP_SPI_SEL>,
 605                                  <&infracfg CLK_IFR_SPI0>;
 606                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 607                         status = "disabled";
 608                 };
 609
 610                 i2c3: i2c@1100f000 {
 611                         compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
 612                         reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
 613                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
 614                         clock-div = <1>;
 615                         clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
 616                         clock-names = "main", "dma";
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                         status = "disabled";
 620                 };
 621
 622                 ssusb: usb@11201000 {
 623                         compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
 624                         reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
 625                         reg-names = "mac", "ippc";
 626                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
 627                         phys = <&u2port0 PHY_TYPE_USB2>,
 628                                <&u2port1 PHY_TYPE_USB2>;
 629                         clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
 630                                  <&infracfg CLK_IFR_SSUSB_REF>,
 631                                  <&infracfg CLK_IFR_SSUSB_SYS>,
 632                                  <&infracfg CLK_IFR_ICUSB>;
 633                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 634                         #address-cells = <2>;
 635                         #size-cells = <2>;
 636                         ranges;
 637                         status = "disabled";
 638
 639                         usb_host: usb@11200000 {
 640                                 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
 641                                 reg = <0 0x11200000 0 0x1000>;
 642                                 reg-names = "mac";
 643                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
 644                                 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
 645                                          <&infracfg CLK_IFR_SSUSB_REF>,
 646                                          <&infracfg CLK_IFR_SSUSB_SYS>,
 647                                          <&infracfg CLK_IFR_ICUSB>,
 648                                          <&infracfg CLK_IFR_SSUSB_XHCI>;
 649                                 clock-names = "sys_ck", "ref_ck", "mcu_ck",
 650                                               "dma_ck", "xhci_ck";
 651                                 status = "disabled";
 652                         };
 653                 };
 654
 655                 mmc0: mmc@11230000 {
 656                         compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
 657                         reg = <0 0x11230000 0 0x1000>,
 658                               <0 0x11cd0000 0 0x1000>;
 659                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
 660                         clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
 661                                  <&infracfg CLK_IFR_MSDC0_HCLK>,
 662                                  <&infracfg CLK_IFR_MSDC0_SRC>;
 663                         clock-names = "source", "hclk", "source_cg";
 664                         status = "disabled";
 665                 };
 666
 667                 mmc1: mmc@11240000 {
 668                         compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
 669                         reg = <0 0x11240000 0 0x1000>,
 670                               <0 0x11c90000 0 0x1000>;
 671                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
 672                         clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
 673                                  <&infracfg CLK_IFR_MSDC1_HCLK>,
 674                                  <&infracfg CLK_IFR_MSDC1_SRC>;
 675                         clock-names = "source", "hclk", "source_cg";
 676                         status = "disabled";
 677                 };
 678
 679                 mmc2: mmc@11250000 {
 680                         compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
 681                         reg = <0 0x11250000 0 0x1000>,
 682                               <0 0x11c60000 0 0x1000>;
 683                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
 684                         clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
 685                                  <&infracfg CLK_IFR_MSDC2_HCLK>,
 686                                  <&infracfg CLK_IFR_MSDC2_SRC>,
 687                                  <&infracfg CLK_IFR_MSDC2_BK>,
 688                                  <&infracfg CLK_IFR_AP_MSDC0>;
 689                         clock-names = "source", "hclk", "source_cg",
 690                                       "bus_clk", "sys_cg";
 691                         status = "disabled";
 692                 };
 693
 694                 ethernet: ethernet@112a0000 {
 695                         compatible = "mediatek,mt8365-eth";
 696                         reg = <0 0x112a0000 0 0x1000>;
 697                         mediatek,pericfg = <&infracfg>;
 698                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 699                         clocks = <&topckgen CLK_TOP_ETH_SEL>,
 700                                  <&infracfg CLK_IFR_NIC_AXI>,
 701                                  <&infracfg CLK_IFR_NIC_SLV_AXI>;
 702                         clock-names = "core", "reg", "trans";
 703                         status = "disabled";
 704                 };
 705
 706                 u3phy: t-phy@11cc0000 {
 707                         compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
 708                         #address-cells = <1>;
 709                         #size-cells = <1>;
 710                         ranges = <0 0 0x11cc0000 0x9000>;
 711
 712                         u2port0: usb-phy@0 {
 713                                 reg = <0x0 0x400>;
 714                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
 715                                          <&topckgen CLK_TOP_USB20_48M_EN>;
 716                                 clock-names = "ref", "da_ref";
 717                                 #phy-cells = <1>;
 718                         };
 719
 720                         u2port1: usb-phy@1000 {
 721                                 reg = <0x1000 0x400>;
 722                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
 723                                          <&topckgen CLK_TOP_USB20_48M_EN>;
 724                                 clock-names = "ref", "da_ref";
 725                                 #phy-cells = <1>;
 726                         };
 727                 };
 728
 729                 mmsys: syscon@14000000 {
 730                         compatible = "mediatek,mt8365-mmsys", "syscon";
 731                         reg = <0 0x14000000 0 0x1000>;
 732                         #clock-cells = <1>;
 733                 };
 734
 735                 smi_common: smi@14002000 {
 736                         compatible = "mediatek,mt8365-smi-common";
 737                         reg = <0 0x14002000 0 0x1000>;
 738                         clocks = <&mmsys CLK_MM_MM_SMI_COMMON>,
 739                                  <&mmsys CLK_MM_MM_SMI_COMMON>,
 740                                  <&mmsys CLK_MM_MM_SMI_COMM0>,
 741                                  <&mmsys CLK_MM_MM_SMI_COMM1>;
 742                         clock-names = "apb", "smi", "gals0", "gals1";
 743                         power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
 744                 };
 745
 746                 larb0: larb@14003000 {
 747                         compatible = "mediatek,mt8365-smi-larb",
 748                                      "mediatek,mt8186-smi-larb";
 749                         reg = <0 0x14003000 0 0x1000>;
 750                         mediatek,smi = <&smi_common>;
 751                         clocks = <&mmsys CLK_MM_MM_SMI_LARB0>,
 752                                  <&mmsys CLK_MM_MM_SMI_LARB0>;
 753                         clock-names = "apb", "smi";
 754                         power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
 755                         mediatek,larb-id = <0>;
 756                 };
 757
 758                 camsys: syscon@15000000 {
 759                         compatible = "mediatek,mt8365-imgsys", "syscon";
 760                         reg = <0 0x15000000 0 0x1000>;
 761                         #clock-cells = <1>;
 762                 };
 763
 764                 larb2: larb@15001000 {
 765                         compatible = "mediatek,mt8365-smi-larb",
 766                                      "mediatek,mt8186-smi-larb";
 767                         reg = <0 0x15001000 0 0x1000>;
 768                         mediatek,smi = <&smi_common>;
 769                         clocks = <&mmsys CLK_MM_MM_SMI_IMG>,
 770                                  <&camsys CLK_CAM_LARB2>;
 771                         clock-names = "apb", "smi";
 772                         power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
 773                         mediatek,larb-id = <2>;
 774                 };
 775
 776                 vdecsys: syscon@16000000 {
 777                         compatible = "mediatek,mt8365-vdecsys", "syscon";
 778                         reg = <0 0x16000000 0 0x1000>;
 779                         #clock-cells = <1>;
 780                 };
 781
 782                 larb3: larb@16010000 {
 783                         compatible = "mediatek,mt8365-smi-larb",
 784                                      "mediatek,mt8186-smi-larb";
 785                         reg = <0 0x16010000 0 0x1000>;
 786                         mediatek,smi = <&smi_common>;
 787                         clocks = <&vdecsys CLK_VDEC_LARB1>,
 788                                  <&vdecsys CLK_VDEC_LARB1>;
 789                         clock-names = "apb", "smi";
 790                         power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>;
 791                         mediatek,larb-id = <3>;
 792                 };
 793
 794                 vencsys: syscon@17000000 {
 795                         compatible = "mediatek,mt8365-vencsys", "syscon";
 796                         reg = <0 0x17000000 0 0x1000>;
 797                         #clock-cells = <1>;
 798                 };
 799
 800                 larb1: larb@17010000 {
 801                         compatible = "mediatek,mt8365-smi-larb",
 802                                      "mediatek,mt8186-smi-larb";
 803                         reg = <0 0x17010000 0 0x1000>;
 804                         mediatek,smi = <&smi_common>;
 805                         clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>;
 806                         clock-names = "apb", "smi";
 807                         power-domains = <&spm MT8365_POWER_DOMAIN_VENC>;
 808                         mediatek,larb-id = <1>;
 809                 };
 810
 811                 apu: syscon@19020000 {
 812                         compatible = "mediatek,mt8365-apu", "syscon";
 813                         reg = <0 0x19020000 0 0x1000>;
 814                         #clock-cells = <1>;
 815                 };
 816         };
 817
 818         timer {
 819                 compatible = "arm,armv8-timer";
 820                 interrupt-parent = <&gic>;
 821                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 822                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 823                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 824                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 825         };
 826
 827         system_clk: dummy13m {
 828                 compatible = "fixed-clock";
 829                 clock-frequency = <13000000>;
 830                 #clock-cells = <0>;
 831         };
 832
 833         systimer: timer@10017000 {
 834                 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
 835                 reg = <0 0x10017000 0 0x100>;
 836                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 837                 clocks = <&system_clk>;
 838                 clock-names = "clk13m";
 839         };
 840 };