arch/arm64/boot/dts/mediatek/mt8195.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8195-clk.h>
   9 #include <dt-bindings/gce/mt8195-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8195-memory-port.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  15 #include <dt-bindings/power/mt8195-power.h>
  16
  17 / {
  18         compatible = "mediatek,mt8195";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 gce0 = &gce0;
  25                 gce1 = &gce1;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu0: cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a55";
  35                         reg = <0x000>;
  36                         enable-method = "psci";
  37                         performance-domains = <&performance 0>;
  38                         clock-frequency = <1701000000>;
  39                         capacity-dmips-mhz = <308>;
  40                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  41                         next-level-cache = <&l2_0>;
  42                         #cooling-cells = <2>;
  43                 };
  44
  45                 cpu1: cpu@100 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a55";
  48                         reg = <0x100>;
  49                         enable-method = "psci";
  50                         performance-domains = <&performance 0>;
  51                         clock-frequency = <1701000000>;
  52                         capacity-dmips-mhz = <308>;
  53                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  54                         next-level-cache = <&l2_0>;
  55                         #cooling-cells = <2>;
  56                 };
  57
  58                 cpu2: cpu@200 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a55";
  61                         reg = <0x200>;
  62                         enable-method = "psci";
  63                         performance-domains = <&performance 0>;
  64                         clock-frequency = <1701000000>;
  65                         capacity-dmips-mhz = <308>;
  66                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  67                         next-level-cache = <&l2_0>;
  68                         #cooling-cells = <2>;
  69                 };
  70
  71                 cpu3: cpu@300 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a55";
  74                         reg = <0x300>;
  75                         enable-method = "psci";
  76                         performance-domains = <&performance 0>;
  77                         clock-frequency = <1701000000>;
  78                         capacity-dmips-mhz = <308>;
  79                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  80                         next-level-cache = <&l2_0>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 cpu4: cpu@400 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a78";
  87                         reg = <0x400>;
  88                         enable-method = "psci";
  89                         performance-domains = <&performance 1>;
  90                         clock-frequency = <2171000000>;
  91                         capacity-dmips-mhz = <1024>;
  92                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
  93                         next-level-cache = <&l2_1>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu5: cpu@500 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a78";
 100                         reg = <0x500>;
 101                         enable-method = "psci";
 102                         performance-domains = <&performance 1>;
 103                         clock-frequency = <2171000000>;
 104                         capacity-dmips-mhz = <1024>;
 105                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 106                         next-level-cache = <&l2_1>;
 107                         #cooling-cells = <2>;
 108                 };
 109
 110                 cpu6: cpu@600 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a78";
 113                         reg = <0x600>;
 114                         enable-method = "psci";
 115                         performance-domains = <&performance 1>;
 116                         clock-frequency = <2171000000>;
 117                         capacity-dmips-mhz = <1024>;
 118                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 119                         next-level-cache = <&l2_1>;
 120                         #cooling-cells = <2>;
 121                 };
 122
 123                 cpu7: cpu@700 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a78";
 126                         reg = <0x700>;
 127                         enable-method = "psci";
 128                         performance-domains = <&performance 1>;
 129                         clock-frequency = <2171000000>;
 130                         capacity-dmips-mhz = <1024>;
 131                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 132                         next-level-cache = <&l2_1>;
 133                         #cooling-cells = <2>;
 134                 };
 135
 136                 cpu-map {
 137                         cluster0 {
 138                                 core0 {
 139                                         cpu = <&cpu0>;
 140                                 };
 141
 142                                 core1 {
 143                                         cpu = <&cpu1>;
 144                                 };
 145
 146                                 core2 {
 147                                         cpu = <&cpu2>;
 148                                 };
 149
 150                                 core3 {
 151                                         cpu = <&cpu3>;
 152                                 };
 153
 154                                 core4 {
 155                                         cpu = <&cpu4>;
 156                                 };
 157
 158                                 core5 {
 159                                         cpu = <&cpu5>;
 160                                 };
 161
 162                                 core6 {
 163                                         cpu = <&cpu6>;
 164                                 };
 165
 166                                 core7 {
 167                                         cpu = <&cpu7>;
 168                                 };
 169                         };
 170                 };
 171
 172                 idle-states {
 173                         entry-method = "psci";
 174
 175                         cpu_off_l: cpu-off-l {
 176                                 compatible = "arm,idle-state";
 177                                 arm,psci-suspend-param = <0x00010001>;
 178                                 local-timer-stop;
 179                                 entry-latency-us = <50>;
 180                                 exit-latency-us = <95>;
 181                                 min-residency-us = <580>;
 182                         };
 183
 184                         cpu_off_b: cpu-off-b {
 185                                 compatible = "arm,idle-state";
 186                                 arm,psci-suspend-param = <0x00010001>;
 187                                 local-timer-stop;
 188                                 entry-latency-us = <45>;
 189                                 exit-latency-us = <140>;
 190                                 min-residency-us = <740>;
 191                         };
 192
 193                         cluster_off_l: cluster-off-l {
 194                                 compatible = "arm,idle-state";
 195                                 arm,psci-suspend-param = <0x01010002>;
 196                                 local-timer-stop;
 197                                 entry-latency-us = <55>;
 198                                 exit-latency-us = <155>;
 199                                 min-residency-us = <840>;
 200                         };
 201
 202                         cluster_off_b: cluster-off-b {
 203                                 compatible = "arm,idle-state";
 204                                 arm,psci-suspend-param = <0x01010002>;
 205                                 local-timer-stop;
 206                                 entry-latency-us = <50>;
 207                                 exit-latency-us = <200>;
 208                                 min-residency-us = <1000>;
 209                         };
 210                 };
 211
 212                 l2_0: l2-cache0 {
 213                         compatible = "cache";
 214                         next-level-cache = <&l3_0>;
 215                 };
 216
 217                 l2_1: l2-cache1 {
 218                         compatible = "cache";
 219                         next-level-cache = <&l3_0>;
 220                 };
 221
 222                 l3_0: l3-cache {
 223                         compatible = "cache";
 224                 };
 225         };
 226
 227         dsu-pmu {
 228                 compatible = "arm,dsu-pmu";
 229                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
 230                 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
 231                        <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 232                 status = "fail";
 233         };
 234
 235         dmic_codec: dmic-codec {
 236                 compatible = "dmic-codec";
 237                 num-channels = <2>;
 238                 wakeup-delay-ms = <50>;
 239         };
 240
 241         sound: mt8195-sound {
 242                 mediatek,platform = <&afe>;
 243                 status = "disabled";
 244         };
 245
 246         clk13m: fixed-factor-clock-13m {
 247                 compatible = "fixed-factor-clock";
 248                 #clock-cells = <0>;
 249                 clocks = <&clk26m>;
 250                 clock-div = <2>;
 251                 clock-mult = <1>;
 252                 clock-output-names = "clk13m";
 253         };
 254
 255         clk26m: oscillator-26m {
 256                 compatible = "fixed-clock";
 257                 #clock-cells = <0>;
 258                 clock-frequency = <26000000>;
 259                 clock-output-names = "clk26m";
 260         };
 261
 262         clk32k: oscillator-32k {
 263                 compatible = "fixed-clock";
 264                 #clock-cells = <0>;
 265                 clock-frequency = <32768>;
 266                 clock-output-names = "clk32k";
 267         };
 268
 269         performance: performance-controller@11bc10 {
 270                 compatible = "mediatek,cpufreq-hw";
 271                 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
 272                 #performance-domain-cells = <1>;
 273         };
 274
 275         pmu-a55 {
 276                 compatible = "arm,cortex-a55-pmu";
 277                 interrupt-parent = <&gic>;
 278                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 279         };
 280
 281         pmu-a78 {
 282                 compatible = "arm,cortex-a78-pmu";
 283                 interrupt-parent = <&gic>;
 284                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 285         };
 286
 287         psci {
 288                 compatible = "arm,psci-1.0";
 289                 method = "smc";
 290         };
 291
 292         timer: timer {
 293                 compatible = "arm,armv8-timer";
 294                 interrupt-parent = <&gic>;
 295                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 296                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 297                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 298                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 299         };
 300
 301         soc {
 302                 #address-cells = <2>;
 303                 #size-cells = <2>;
 304                 compatible = "simple-bus";
 305                 ranges;
 306
 307                 gic: interrupt-controller@c000000 {
 308                         compatible = "arm,gic-v3";
 309                         #interrupt-cells = <4>;
 310                         #redistributor-regions = <1>;
 311                         interrupt-parent = <&gic>;
 312                         interrupt-controller;
 313                         reg = <0 0x0c000000 0 0x40000>,
 314                               <0 0x0c040000 0 0x200000>;
 315                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 316
 317                         ppi-partitions {
 318                                 ppi_cluster0: interrupt-partition-0 {
 319                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 320                                 };
 321
 322                                 ppi_cluster1: interrupt-partition-1 {
 323                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 324                                 };
 325                         };
 326                 };
 327
 328                 topckgen: syscon@10000000 {
 329                         compatible = "mediatek,mt8195-topckgen", "syscon";
 330                         reg = <0 0x10000000 0 0x1000>;
 331                         #clock-cells = <1>;
 332                 };
 333
 334                 infracfg_ao: syscon@10001000 {
 335                         compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 336                         reg = <0 0x10001000 0 0x1000>;
 337                         #clock-cells = <1>;
 338                         #reset-cells = <1>;
 339                 };
 340
 341                 pericfg: syscon@10003000 {
 342                         compatible = "mediatek,mt8195-pericfg", "syscon";
 343                         reg = <0 0x10003000 0 0x1000>;
 344                         #clock-cells = <1>;
 345                 };
 346
 347                 pio: pinctrl@10005000 {
 348                         compatible = "mediatek,mt8195-pinctrl";
 349                         reg = <0 0x10005000 0 0x1000>,
 350                               <0 0x11d10000 0 0x1000>,
 351                               <0 0x11d30000 0 0x1000>,
 352                               <0 0x11d40000 0 0x1000>,
 353                               <0 0x11e20000 0 0x1000>,
 354                               <0 0x11eb0000 0 0x1000>,
 355                               <0 0x11f40000 0 0x1000>,
 356                               <0 0x1000b000 0 0x1000>;
 357                         reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
 358                                     "iocfg_br", "iocfg_lm", "iocfg_rb",
 359                                     "iocfg_tl", "eint";
 360                         gpio-controller;
 361                         #gpio-cells = <2>;
 362                         gpio-ranges = <&pio 0 0 144>;
 363                         interrupt-controller;
 364                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
 365                         #interrupt-cells = <2>;
 366                 };
 367
 368                 scpsys: syscon@10006000 {
 369                         compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
 370                         reg = <0 0x10006000 0 0x1000>;
 371
 372                         /* System Power Manager */
 373                         spm: power-controller {
 374                                 compatible = "mediatek,mt8195-power-controller";
 375                                 #address-cells = <1>;
 376                                 #size-cells = <0>;
 377                                 #power-domain-cells = <1>;
 378
 379                                 /* power domain of the SoC */
 380                                 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
 381                                         reg = <MT8195_POWER_DOMAIN_MFG0>;
 382                                         #address-cells = <1>;
 383                                         #size-cells = <0>;
 384                                         #power-domain-cells = <1>;
 385
 386                                         power-domain@MT8195_POWER_DOMAIN_MFG1 {
 387                                                 reg = <MT8195_POWER_DOMAIN_MFG1>;
 388                                                 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
 389                                                 clock-names = "mfg";
 390                                                 mediatek,infracfg = <&infracfg_ao>;
 391                                                 #address-cells = <1>;
 392                                                 #size-cells = <0>;
 393                                                 #power-domain-cells = <1>;
 394
 395                                                 power-domain@MT8195_POWER_DOMAIN_MFG2 {
 396                                                         reg = <MT8195_POWER_DOMAIN_MFG2>;
 397                                                         #power-domain-cells = <0>;
 398                                                 };
 399
 400                                                 power-domain@MT8195_POWER_DOMAIN_MFG3 {
 401                                                         reg = <MT8195_POWER_DOMAIN_MFG3>;
 402                                                         #power-domain-cells = <0>;
 403                                                 };
 404
 405                                                 power-domain@MT8195_POWER_DOMAIN_MFG4 {
 406                                                         reg = <MT8195_POWER_DOMAIN_MFG4>;
 407                                                         #power-domain-cells = <0>;
 408                                                 };
 409
 410                                                 power-domain@MT8195_POWER_DOMAIN_MFG5 {
 411                                                         reg = <MT8195_POWER_DOMAIN_MFG5>;
 412                                                         #power-domain-cells = <0>;
 413                                                 };
 414
 415                                                 power-domain@MT8195_POWER_DOMAIN_MFG6 {
 416                                                         reg = <MT8195_POWER_DOMAIN_MFG6>;
 417                                                         #power-domain-cells = <0>;
 418                                                 };
 419                                         };
 420                                 };
 421
 422                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
 423                                         reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
 424                                         clocks = <&topckgen CLK_TOP_VPP>,
 425                                                  <&topckgen CLK_TOP_CAM>,
 426                                                  <&topckgen CLK_TOP_CCU>,
 427                                                  <&topckgen CLK_TOP_IMG>,
 428                                                  <&topckgen CLK_TOP_VENC>,
 429                                                  <&topckgen CLK_TOP_VDEC>,
 430                                                  <&topckgen CLK_TOP_WPE_VPP>,
 431                                                  <&topckgen CLK_TOP_CFG_VPP0>,
 432                                                  <&vppsys0 CLK_VPP0_SMI_COMMON>,
 433                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
 434                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
 435                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
 436                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
 437                                                  <&vppsys0 CLK_VPP0_GALS_INFRA>,
 438                                                  <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
 439                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
 440                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
 441                                                  <&vppsys0 CLK_VPP0_SMI_REORDER>,
 442                                                  <&vppsys0 CLK_VPP0_SMI_IOMMU>,
 443                                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
 444                                                  <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
 445                                                  <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
 446                                                  <&vppsys0 CLK_VPP0_SMI_RSI>,
 447                                                  <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
 448                                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
 449                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
 450                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
 451                                         clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
 452                                                       "vppsys4", "vppsys5", "vppsys6", "vppsys7",
 453                                                       "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
 454                                                       "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
 455                                                       "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
 456                                                       "vppsys0-12", "vppsys0-13", "vppsys0-14",
 457                                                       "vppsys0-15", "vppsys0-16", "vppsys0-17",
 458                                                       "vppsys0-18";
 459                                         mediatek,infracfg = <&infracfg_ao>;
 460                                         #address-cells = <1>;
 461                                         #size-cells = <0>;
 462                                         #power-domain-cells = <1>;
 463
 464                                         power-domain@MT8195_POWER_DOMAIN_VDEC1 {
 465                                                 reg = <MT8195_POWER_DOMAIN_VDEC1>;
 466                                                 clocks = <&vdecsys CLK_VDEC_LARB1>;
 467                                                 clock-names = "vdec1-0";
 468                                                 mediatek,infracfg = <&infracfg_ao>;
 469                                                 #power-domain-cells = <0>;
 470                                         };
 471
 472                                         power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
 473                                                 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
 474                                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
 475                                                 clock-names = "venc1-larb";
 476                                                 mediatek,infracfg = <&infracfg_ao>;
 477                                                 #power-domain-cells = <0>;
 478                                         };
 479
 480                                         power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
 481                                                 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
 482                                                 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
 483                                                          <&vdosys0 CLK_VDO0_SMI_GALS>,
 484                                                          <&vdosys0 CLK_VDO0_SMI_COMMON>,
 485                                                          <&vdosys0 CLK_VDO0_SMI_EMI>,
 486                                                          <&vdosys0 CLK_VDO0_SMI_IOMMU>,
 487                                                          <&vdosys0 CLK_VDO0_SMI_LARB>,
 488                                                          <&vdosys0 CLK_VDO0_SMI_RSI>;
 489                                                 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
 490                                                               "vdosys0-2", "vdosys0-3",
 491                                                               "vdosys0-4", "vdosys0-5";
 492                                                 mediatek,infracfg = <&infracfg_ao>;
 493                                                 #address-cells = <1>;
 494                                                 #size-cells = <0>;
 495                                                 #power-domain-cells = <1>;
 496
 497                                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
 498                                                         reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
 499                                                         clocks = <&topckgen CLK_TOP_CFG_VPP1>,
 500                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
 501                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
 502                                                         clock-names = "vppsys1", "vppsys1-0",
 503                                                                       "vppsys1-1";
 504                                                         mediatek,infracfg = <&infracfg_ao>;
 505                                                         #power-domain-cells = <0>;
 506                                                 };
 507
 508                                                 power-domain@MT8195_POWER_DOMAIN_WPESYS {
 509                                                         reg = <MT8195_POWER_DOMAIN_WPESYS>;
 510                                                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
 511                                                                  <&wpesys CLK_WPE_SMI_LARB8>,
 512                                                                  <&wpesys CLK_WPE_SMI_LARB7_P>,
 513                                                                  <&wpesys CLK_WPE_SMI_LARB8_P>;
 514                                                         clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
 515                                                                       "wepsys-3";
 516                                                         mediatek,infracfg = <&infracfg_ao>;
 517                                                         #power-domain-cells = <0>;
 518                                                 };
 519
 520                                                 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
 521                                                         reg = <MT8195_POWER_DOMAIN_VDEC0>;
 522                                                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
 523                                                         clock-names = "vdec0-0";
 524                                                         mediatek,infracfg = <&infracfg_ao>;
 525                                                         #power-domain-cells = <0>;
 526                                                 };
 527
 528                                                 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
 529                                                         reg = <MT8195_POWER_DOMAIN_VDEC2>;
 530                                                         clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
 531                                                         clock-names = "vdec2-0";
 532                                                         mediatek,infracfg = <&infracfg_ao>;
 533                                                         #power-domain-cells = <0>;
 534                                                 };
 535
 536                                                 power-domain@MT8195_POWER_DOMAIN_VENC {
 537                                                         reg = <MT8195_POWER_DOMAIN_VENC>;
 538                                                         clocks = <&vencsys CLK_VENC_LARB>;
 539                                                         clock-names = "venc0-larb";
 540                                                         mediatek,infracfg = <&infracfg_ao>;
 541                                                         #power-domain-cells = <0>;
 542                                                 };
 543
 544                                                 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
 545                                                         reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
 546                                                         clocks = <&topckgen CLK_TOP_CFG_VDO1>,
 547                                                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
 548                                                                  <&vdosys1 CLK_VDO1_SMI_LARB3>,
 549                                                                  <&vdosys1 CLK_VDO1_GALS>;
 550                                                         clock-names = "vdosys1", "vdosys1-0",
 551                                                                       "vdosys1-1", "vdosys1-2";
 552                                                         mediatek,infracfg = <&infracfg_ao>;
 553                                                         #address-cells = <1>;
 554                                                         #size-cells = <0>;
 555                                                         #power-domain-cells = <1>;
 556
 557                                                         power-domain@MT8195_POWER_DOMAIN_DP_TX {
 558                                                                 reg = <MT8195_POWER_DOMAIN_DP_TX>;
 559                                                                 mediatek,infracfg = <&infracfg_ao>;
 560                                                                 #power-domain-cells = <0>;
 561                                                         };
 562
 563                                                         power-domain@MT8195_POWER_DOMAIN_EPD_TX {
 564                                                                 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
 565                                                                 mediatek,infracfg = <&infracfg_ao>;
 566                                                                 #power-domain-cells = <0>;
 567                                                         };
 568
 569                                                         power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
 570                                                                 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
 571                                                                 clocks = <&topckgen CLK_TOP_HDMI_APB>;
 572                                                                 clock-names = "hdmi_tx";
 573                                                                 #power-domain-cells = <0>;
 574                                                         };
 575                                                 };
 576
 577                                                 power-domain@MT8195_POWER_DOMAIN_IMG {
 578                                                         reg = <MT8195_POWER_DOMAIN_IMG>;
 579                                                         clocks = <&imgsys CLK_IMG_LARB9>,
 580                                                                  <&imgsys CLK_IMG_GALS>;
 581                                                         clock-names = "img-0", "img-1";
 582                                                         mediatek,infracfg = <&infracfg_ao>;
 583                                                         #address-cells = <1>;
 584                                                         #size-cells = <0>;
 585                                                         #power-domain-cells = <1>;
 586
 587                                                         power-domain@MT8195_POWER_DOMAIN_DIP {
 588                                                                 reg = <MT8195_POWER_DOMAIN_DIP>;
 589                                                                 #power-domain-cells = <0>;
 590                                                         };
 591
 592                                                         power-domain@MT8195_POWER_DOMAIN_IPE {
 593                                                                 reg = <MT8195_POWER_DOMAIN_IPE>;
 594                                                                 clocks = <&topckgen CLK_TOP_IPE>,
 595                                                                          <&imgsys CLK_IMG_IPE>,
 596                                                                          <&ipesys CLK_IPE_SMI_LARB12>;
 597                                                                 clock-names = "ipe", "ipe-0", "ipe-1";
 598                                                                 mediatek,infracfg = <&infracfg_ao>;
 599                                                                 #power-domain-cells = <0>;
 600                                                         };
 601                                                 };
 602
 603                                                 power-domain@MT8195_POWER_DOMAIN_CAM {
 604                                                         reg = <MT8195_POWER_DOMAIN_CAM>;
 605                                                         clocks = <&camsys CLK_CAM_LARB13>,
 606                                                                  <&camsys CLK_CAM_LARB14>,
 607                                                                  <&camsys CLK_CAM_CAM2MM0_GALS>,
 608                                                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
 609                                                                  <&camsys CLK_CAM_CAM2SYS_GALS>;
 610                                                         clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
 611                                                                       "cam-4";
 612                                                         mediatek,infracfg = <&infracfg_ao>;
 613                                                         #address-cells = <1>;
 614                                                         #size-cells = <0>;
 615                                                         #power-domain-cells = <1>;
 616
 617                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
 618                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
 619                                                                 #power-domain-cells = <0>;
 620                                                         };
 621
 622                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
 623                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
 624                                                                 #power-domain-cells = <0>;
 625                                                         };
 626
 627                                                         power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
 628                                                                 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
 629                                                                 #power-domain-cells = <0>;
 630                                                         };
 631                                                 };
 632                                         };
 633                                 };
 634
 635                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
 636                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
 637                                         mediatek,infracfg = <&infracfg_ao>;
 638                                         #power-domain-cells = <0>;
 639                                 };
 640
 641                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
 642                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
 643                                         mediatek,infracfg = <&infracfg_ao>;
 644                                         #power-domain-cells = <0>;
 645                                 };
 646
 647                                 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
 648                                         reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
 649                                         #power-domain-cells = <0>;
 650                                 };
 651
 652                                 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
 653                                         reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
 654                                         #power-domain-cells = <0>;
 655                                 };
 656
 657                                 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
 658                                         reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
 659                                         clocks = <&topckgen CLK_TOP_SENINF>,
 660                                                  <&topckgen CLK_TOP_SENINF2>;
 661                                         clock-names = "csi_rx_top", "csi_rx_top1";
 662                                         #power-domain-cells = <0>;
 663                                 };
 664
 665                                 power-domain@MT8195_POWER_DOMAIN_ETHER {
 666                                         reg = <MT8195_POWER_DOMAIN_ETHER>;
 667                                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
 668                                         clock-names = "ether";
 669                                         #power-domain-cells = <0>;
 670                                 };
 671
 672                                 power-domain@MT8195_POWER_DOMAIN_ADSP {
 673                                         reg = <MT8195_POWER_DOMAIN_ADSP>;
 674                                         clocks = <&topckgen CLK_TOP_ADSP>,
 675                                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
 676                                         clock-names = "adsp", "adsp1";
 677                                         #address-cells = <1>;
 678                                         #size-cells = <0>;
 679                                         mediatek,infracfg = <&infracfg_ao>;
 680                                         #power-domain-cells = <1>;
 681
 682                                         power-domain@MT8195_POWER_DOMAIN_AUDIO {
 683                                                 reg = <MT8195_POWER_DOMAIN_AUDIO>;
 684                                                 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
 685                                                          <&topckgen CLK_TOP_AUD_INTBUS>,
 686                                                          <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 687                                                          <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
 688                                                 clock-names = "audio", "audio1", "audio2",
 689                                                               "audio3";
 690                                                 mediatek,infracfg = <&infracfg_ao>;
 691                                                 #power-domain-cells = <0>;
 692                                         };
 693                                 };
 694                         };
 695                 };
 696
 697                 watchdog: watchdog@10007000 {
 698                         compatible = "mediatek,mt8195-wdt";
 699                         mediatek,disable-extrst;
 700                         reg = <0 0x10007000 0 0x100>;
 701                         #reset-cells = <1>;
 702                 };
 703
 704                 apmixedsys: syscon@1000c000 {
 705                         compatible = "mediatek,mt8195-apmixedsys", "syscon";
 706                         reg = <0 0x1000c000 0 0x1000>;
 707                         #clock-cells = <1>;
 708                 };
 709
 710                 systimer: timer@10017000 {
 711                         compatible = "mediatek,mt8195-timer",
 712                                      "mediatek,mt6765-timer";
 713                         reg = <0 0x10017000 0 0x1000>;
 714                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
 715                         clocks = <&clk13m>;
 716                 };
 717
 718                 pwrap: pwrap@10024000 {
 719                         compatible = "mediatek,mt8195-pwrap", "syscon";
 720                         reg = <0 0x10024000 0 0x1000>;
 721                         reg-names = "pwrap";
 722                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
 723                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 724                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 725                         clock-names = "spi", "wrap";
 726                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 727                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 728                 };
 729
 730                 spmi: spmi@10027000 {
 731                         compatible = "mediatek,mt8195-spmi";
 732                         reg = <0 0x10027000 0 0x000e00>,
 733                               <0 0x10029000 0 0x000100>;
 734                         reg-names = "pmif", "spmimst";
 735                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 736                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
 737                                  <&topckgen CLK_TOP_SPMI_M_MST>;
 738                         clock-names = "pmif_sys_ck",
 739                                       "pmif_tmr_ck",
 740                                       "spmimst_clk_mux";
 741                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 742                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 743                 };
 744
 745                 iommu_infra: infra-iommu@10315000 {
 746                         compatible = "mediatek,mt8195-iommu-infra";
 747                         reg = <0 0x10315000 0 0x5000>;
 748                         interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
 749                                      <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
 750                                      <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
 751                                      <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
 752                                      <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
 753                         #iommu-cells = <1>;
 754                 };
 755
 756                 gce0: mailbox@10320000 {
 757                         compatible = "mediatek,mt8195-gce";
 758                         reg = <0 0x10320000 0 0x4000>;
 759                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 760                         #mbox-cells = <2>;
 761                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
 762                 };
 763
 764                 gce1: mailbox@10330000 {
 765                         compatible = "mediatek,mt8195-gce";
 766                         reg = <0 0x10330000 0 0x4000>;
 767                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
 768                         #mbox-cells = <2>;
 769                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
 770                 };
 771
 772                 scp: scp@10500000 {
 773                         compatible = "mediatek,mt8195-scp";
 774                         reg = <0 0x10500000 0 0x100000>,
 775                               <0 0x10720000 0 0xe0000>,
 776                               <0 0x10700000 0 0x8000>;
 777                         reg-names = "sram", "cfg", "l1tcm";
 778                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
 779                         status = "disabled";
 780                 };
 781
 782                 scp_adsp: clock-controller@10720000 {
 783                         compatible = "mediatek,mt8195-scp_adsp";
 784                         reg = <0 0x10720000 0 0x1000>;
 785                         #clock-cells = <1>;
 786                 };
 787
 788                 adsp: dsp@10803000 {
 789                         compatible = "mediatek,mt8195-dsp";
 790                         reg = <0 0x10803000 0 0x1000>,
 791                               <0 0x10840000 0 0x40000>;
 792                         reg-names = "cfg", "sram";
 793                         clocks = <&topckgen CLK_TOP_ADSP>,
 794                                  <&clk26m>,
 795                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 796                                  <&topckgen CLK_TOP_MAINPLL_D7_D2>,
 797                                  <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
 798                                  <&topckgen CLK_TOP_AUDIO_H>;
 799                         clock-names = "adsp_sel",
 800                                  "clk26m_ck",
 801                                  "audio_local_bus",
 802                                  "mainpll_d7_d2",
 803                                  "scp_adsp_audiodsp",
 804                                  "audio_h";
 805                         power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
 806                         mbox-names = "rx", "tx";
 807                         mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
 808                         status = "disabled";
 809                 };
 810
 811                 adsp_mailbox0: mailbox@10816000 {
 812                         compatible = "mediatek,mt8195-adsp-mbox";
 813                         #mbox-cells = <0>;
 814                         reg = <0 0x10816000 0 0x1000>;
 815                         interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
 816                 };
 817
 818                 adsp_mailbox1: mailbox@10817000 {
 819                         compatible = "mediatek,mt8195-adsp-mbox";
 820                         #mbox-cells = <0>;
 821                         reg = <0 0x10817000 0 0x1000>;
 822                         interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
 823                 };
 824
 825                 afe: mt8195-afe-pcm@10890000 {
 826                         compatible = "mediatek,mt8195-audio";
 827                         reg = <0 0x10890000 0 0x10000>;
 828                         mediatek,topckgen = <&topckgen>;
 829                         power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
 830                         interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
 831                         resets = <&watchdog 14>;
 832                         reset-names = "audiosys";
 833                         clocks = <&clk26m>,
 834                                 <&apmixedsys CLK_APMIXED_APLL1>,
 835                                 <&apmixedsys CLK_APMIXED_APLL2>,
 836                                 <&topckgen CLK_TOP_APLL12_DIV0>,
 837                                 <&topckgen CLK_TOP_APLL12_DIV1>,
 838                                 <&topckgen CLK_TOP_APLL12_DIV2>,
 839                                 <&topckgen CLK_TOP_APLL12_DIV3>,
 840                                 <&topckgen CLK_TOP_APLL12_DIV9>,
 841                                 <&topckgen CLK_TOP_A1SYS_HP>,
 842                                 <&topckgen CLK_TOP_AUD_INTBUS>,
 843                                 <&topckgen CLK_TOP_AUDIO_H>,
 844                                 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 845                                 <&topckgen CLK_TOP_DPTX_MCK>,
 846                                 <&topckgen CLK_TOP_I2SO1_MCK>,
 847                                 <&topckgen CLK_TOP_I2SO2_MCK>,
 848                                 <&topckgen CLK_TOP_I2SI1_MCK>,
 849                                 <&topckgen CLK_TOP_I2SI2_MCK>,
 850                                 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
 851                                 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
 852                         clock-names = "clk26m",
 853                                 "apll1_ck",
 854                                 "apll2_ck",
 855                                 "apll12_div0",
 856                                 "apll12_div1",
 857                                 "apll12_div2",
 858                                 "apll12_div3",
 859                                 "apll12_div9",
 860                                 "a1sys_hp_sel",
 861                                 "aud_intbus_sel",
 862                                 "audio_h_sel",
 863                                 "audio_local_bus_sel",
 864                                 "dptx_m_sel",
 865                                 "i2so1_m_sel",
 866                                 "i2so2_m_sel",
 867                                 "i2si1_m_sel",
 868                                 "i2si2_m_sel",
 869                                 "infra_ao_audio_26m_b",
 870                                 "scp_adsp_audiodsp";
 871                         status = "disabled";
 872                 };
 873
 874                 uart0: serial@11001100 {
 875                         compatible = "mediatek,mt8195-uart",
 876                                      "mediatek,mt6577-uart";
 877                         reg = <0 0x11001100 0 0x100>;
 878                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
 879                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
 880                         clock-names = "baud", "bus";
 881                         status = "disabled";
 882                 };
 883
 884                 uart1: serial@11001200 {
 885                         compatible = "mediatek,mt8195-uart",
 886                                      "mediatek,mt6577-uart";
 887                         reg = <0 0x11001200 0 0x100>;
 888                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
 889                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
 890                         clock-names = "baud", "bus";
 891                         status = "disabled";
 892                 };
 893
 894                 uart2: serial@11001300 {
 895                         compatible = "mediatek,mt8195-uart",
 896                                      "mediatek,mt6577-uart";
 897                         reg = <0 0x11001300 0 0x100>;
 898                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
 899                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
 900                         clock-names = "baud", "bus";
 901                         status = "disabled";
 902                 };
 903
 904                 uart3: serial@11001400 {
 905                         compatible = "mediatek,mt8195-uart",
 906                                      "mediatek,mt6577-uart";
 907                         reg = <0 0x11001400 0 0x100>;
 908                         interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
 909                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
 910                         clock-names = "baud", "bus";
 911                         status = "disabled";
 912                 };
 913
 914                 uart4: serial@11001500 {
 915                         compatible = "mediatek,mt8195-uart",
 916                                      "mediatek,mt6577-uart";
 917                         reg = <0 0x11001500 0 0x100>;
 918                         interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
 919                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
 920                         clock-names = "baud", "bus";
 921                         status = "disabled";
 922                 };
 923
 924                 uart5: serial@11001600 {
 925                         compatible = "mediatek,mt8195-uart",
 926                                      "mediatek,mt6577-uart";
 927                         reg = <0 0x11001600 0 0x100>;
 928                         interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
 929                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
 930                         clock-names = "baud", "bus";
 931                         status = "disabled";
 932                 };
 933
 934                 auxadc: auxadc@11002000 {
 935                         compatible = "mediatek,mt8195-auxadc",
 936                                      "mediatek,mt8173-auxadc";
 937                         reg = <0 0x11002000 0 0x1000>;
 938                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
 939                         clock-names = "main";
 940                         #io-channel-cells = <1>;
 941                         status = "disabled";
 942                 };
 943
 944                 pericfg_ao: syscon@11003000 {
 945                         compatible = "mediatek,mt8195-pericfg_ao", "syscon";
 946                         reg = <0 0x11003000 0 0x1000>;
 947                         #clock-cells = <1>;
 948                 };
 949
 950                 spi0: spi@1100a000 {
 951                         compatible = "mediatek,mt8195-spi",
 952                                      "mediatek,mt6765-spi";
 953                         #address-cells = <1>;
 954                         #size-cells = <0>;
 955                         reg = <0 0x1100a000 0 0x1000>;
 956                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
 957                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 958                                  <&topckgen CLK_TOP_SPI>,
 959                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
 960                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 961                         status = "disabled";
 962                 };
 963
 964                 spi1: spi@11010000 {
 965                         compatible = "mediatek,mt8195-spi",
 966                                      "mediatek,mt6765-spi";
 967                         #address-cells = <1>;
 968                         #size-cells = <0>;
 969                         reg = <0 0x11010000 0 0x1000>;
 970                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
 971                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 972                                  <&topckgen CLK_TOP_SPI>,
 973                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
 974                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 975                         status = "disabled";
 976                 };
 977
 978                 spi2: spi@11012000 {
 979                         compatible = "mediatek,mt8195-spi",
 980                                      "mediatek,mt6765-spi";
 981                         #address-cells = <1>;
 982                         #size-cells = <0>;
 983                         reg = <0 0x11012000 0 0x1000>;
 984                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
 985                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
 986                                  <&topckgen CLK_TOP_SPI>,
 987                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
 988                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 989                         status = "disabled";
 990                 };
 991
 992                 spi3: spi@11013000 {
 993                         compatible = "mediatek,mt8195-spi",
 994                                      "mediatek,mt6765-spi";
 995                         #address-cells = <1>;
 996                         #size-cells = <0>;
 997                         reg = <0 0x11013000 0 0x1000>;
 998                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
 999                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1000                                  <&topckgen CLK_TOP_SPI>,
1001                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
1002                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1003                         status = "disabled";
1004                 };
1005
1006                 spi4: spi@11018000 {
1007                         compatible = "mediatek,mt8195-spi",
1008                                      "mediatek,mt6765-spi";
1009                         #address-cells = <1>;
1010                         #size-cells = <0>;
1011                         reg = <0 0x11018000 0 0x1000>;
1012                         interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1013                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1014                                  <&topckgen CLK_TOP_SPI>,
1015                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
1016                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1017                         status = "disabled";
1018                 };
1019
1020                 spi5: spi@11019000 {
1021                         compatible = "mediatek,mt8195-spi",
1022                                      "mediatek,mt6765-spi";
1023                         #address-cells = <1>;
1024                         #size-cells = <0>;
1025                         reg = <0 0x11019000 0 0x1000>;
1026                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1027                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1028                                  <&topckgen CLK_TOP_SPI>,
1029                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
1030                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1031                         status = "disabled";
1032                 };
1033
1034                 spis0: spi@1101d000 {
1035                         compatible = "mediatek,mt8195-spi-slave";
1036                         reg = <0 0x1101d000 0 0x1000>;
1037                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1038                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1039                         clock-names = "spi";
1040                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1041                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1042                         status = "disabled";
1043                 };
1044
1045                 spis1: spi@1101e000 {
1046                         compatible = "mediatek,mt8195-spi-slave";
1047                         reg = <0 0x1101e000 0 0x1000>;
1048                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1049                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1050                         clock-names = "spi";
1051                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1052                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1053                         status = "disabled";
1054                 };
1055
1056                 xhci0: usb@11200000 {
1057                         compatible = "mediatek,mt8195-xhci",
1058                                      "mediatek,mtk-xhci";
1059                         reg = <0 0x11200000 0 0x1000>,
1060                               <0 0x11203e00 0 0x0100>;
1061                         reg-names = "mac", "ippc";
1062                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1063                         phys = <&u2port0 PHY_TYPE_USB2>,
1064                                <&u3port0 PHY_TYPE_USB3>;
1065                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1066                                           <&topckgen CLK_TOP_SSUSB_XHCI>;
1067                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1068                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1069                         clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1070                                  <&topckgen CLK_TOP_SSUSB_REF>,
1071                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1072                                  <&clk26m>,
1073                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1074                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1075                                       "xhci_ck";
1076                         mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1077                         wakeup-source;
1078                         status = "disabled";
1079                 };
1080
1081                 mmc0: mmc@11230000 {
1082                         compatible = "mediatek,mt8195-mmc",
1083                                      "mediatek,mt8183-mmc";
1084                         reg = <0 0x11230000 0 0x10000>,
1085                               <0 0x11f50000 0 0x1000>;
1086                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1087                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
1088                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1089                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1090                         clock-names = "source", "hclk", "source_cg";
1091                         status = "disabled";
1092                 };
1093
1094                 mmc1: mmc@11240000 {
1095                         compatible = "mediatek,mt8195-mmc",
1096                                      "mediatek,mt8183-mmc";
1097                         reg = <0 0x11240000 0 0x1000>,
1098                               <0 0x11c70000 0 0x1000>;
1099                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1100                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
1101                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1102                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1103                         clock-names = "source", "hclk", "source_cg";
1104                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1105                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1106                         status = "disabled";
1107                 };
1108
1109                 mmc2: mmc@11250000 {
1110                         compatible = "mediatek,mt8195-mmc",
1111                                      "mediatek,mt8183-mmc";
1112                         reg = <0 0x11250000 0 0x1000>,
1113                               <0 0x11e60000 0 0x1000>;
1114                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1115                         clocks = <&topckgen CLK_TOP_MSDC30_2>,
1116                                  <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1117                                  <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1118                         clock-names = "source", "hclk", "source_cg";
1119                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1120                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1121                         status = "disabled";
1122                 };
1123
1124                 xhci1: usb@11290000 {
1125                         compatible = "mediatek,mt8195-xhci",
1126                                      "mediatek,mtk-xhci";
1127                         reg = <0 0x11290000 0 0x1000>,
1128                               <0 0x11293e00 0 0x0100>;
1129                         reg-names = "mac", "ippc";
1130                         interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1131                         phys = <&u2port1 PHY_TYPE_USB2>;
1132                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1133                                           <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1134                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1135                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1136                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1137                                  <&topckgen CLK_TOP_SSUSB_P1_REF>,
1138                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1139                                  <&clk26m>,
1140                                  <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1141                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1142                                       "xhci_ck";
1143                         mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1144                         wakeup-source;
1145                         status = "disabled";
1146                 };
1147
1148                 xhci2: usb@112a0000 {
1149                         compatible = "mediatek,mt8195-xhci",
1150                                      "mediatek,mtk-xhci";
1151                         reg = <0 0x112a0000 0 0x1000>,
1152                               <0 0x112a3e00 0 0x0100>;
1153                         reg-names = "mac", "ippc";
1154                         interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1155                         phys = <&u2port2 PHY_TYPE_USB2>;
1156                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1157                                           <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1158                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1159                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1160                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1161                                  <&topckgen CLK_TOP_SSUSB_P2_REF>,
1162                                  <&clk26m>,
1163                                  <&clk26m>,
1164                                  <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1165                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1166                                       "xhci_ck";
1167                         mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1168                         wakeup-source;
1169                         status = "disabled";
1170                 };
1171
1172                 xhci3: usb@112b0000 {
1173                         compatible = "mediatek,mt8195-xhci",
1174                                      "mediatek,mtk-xhci";
1175                         reg = <0 0x112b0000 0 0x1000>,
1176                               <0 0x112b3e00 0 0x0100>;
1177                         reg-names = "mac", "ippc";
1178                         interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1179                         phys = <&u2port3 PHY_TYPE_USB2>;
1180                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1181                                           <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1182                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1183                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1184                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1185                                  <&topckgen CLK_TOP_SSUSB_P3_REF>,
1186                                  <&clk26m>,
1187                                  <&clk26m>,
1188                                  <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1189                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1190                                       "xhci_ck";
1191                         mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1192                         wakeup-source;
1193                         status = "disabled";
1194                 };
1195
1196                 nor_flash: spi@1132c000 {
1197                         compatible = "mediatek,mt8195-nor",
1198                                      "mediatek,mt8173-nor";
1199                         reg = <0 0x1132c000 0 0x1000>;
1200                         interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1201                         clocks = <&topckgen CLK_TOP_SPINOR>,
1202                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1203                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1204                         clock-names = "spi", "sf", "axi";
1205                         #address-cells = <1>;
1206                         #size-cells = <0>;
1207                         status = "disabled";
1208                 };
1209
1210                 efuse: efuse@11c10000 {
1211                         compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1212                         reg = <0 0x11c10000 0 0x1000>;
1213                         #address-cells = <1>;
1214                         #size-cells = <1>;
1215                         u3_tx_imp_p0: usb3-tx-imp@184,1 {
1216                                 reg = <0x184 0x1>;
1217                                 bits = <0 5>;
1218                         };
1219                         u3_rx_imp_p0: usb3-rx-imp@184,2 {
1220                                 reg = <0x184 0x2>;
1221                                 bits = <5 5>;
1222                         };
1223                         u3_intr_p0: usb3-intr@185 {
1224                                 reg = <0x185 0x1>;
1225                                 bits = <2 6>;
1226                         };
1227                         comb_tx_imp_p1: usb3-tx-imp@186,1 {
1228                                 reg = <0x186 0x1>;
1229                                 bits = <0 5>;
1230                         };
1231                         comb_rx_imp_p1: usb3-rx-imp@186,2 {
1232                                 reg = <0x186 0x2>;
1233                                 bits = <5 5>;
1234                         };
1235                         comb_intr_p1: usb3-intr@187 {
1236                                 reg = <0x187 0x1>;
1237                                 bits = <2 6>;
1238                         };
1239                         u2_intr_p0: usb2-intr-p0@188,1 {
1240                                 reg = <0x188 0x1>;
1241                                 bits = <0 5>;
1242                         };
1243                         u2_intr_p1: usb2-intr-p1@188,2 {
1244                                 reg = <0x188 0x2>;
1245                                 bits = <5 5>;
1246                         };
1247                         u2_intr_p2: usb2-intr-p2@189,1 {
1248                                 reg = <0x189 0x1>;
1249                                 bits = <2 5>;
1250                         };
1251                         u2_intr_p3: usb2-intr-p3@189,2 {
1252                                 reg = <0x189 0x2>;
1253                                 bits = <7 5>;
1254                         };
1255                 };
1256
1257                 u3phy2: t-phy@11c40000 {
1258                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1259                         #address-cells = <1>;
1260                         #size-cells = <1>;
1261                         ranges = <0 0 0x11c40000 0x700>;
1262                         status = "disabled";
1263
1264                         u2port2: usb-phy@0 {
1265                                 reg = <0x0 0x700>;
1266                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1267                                 clock-names = "ref";
1268                                 #phy-cells = <1>;
1269                         };
1270                 };
1271
1272                 u3phy3: t-phy@11c50000 {
1273                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1274                         #address-cells = <1>;
1275                         #size-cells = <1>;
1276                         ranges = <0 0 0x11c50000 0x700>;
1277                         status = "disabled";
1278
1279                         u2port3: usb-phy@0 {
1280                                 reg = <0x0 0x700>;
1281                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1282                                 clock-names = "ref";
1283                                 #phy-cells = <1>;
1284                         };
1285                 };
1286
1287                 i2c5: i2c@11d00000 {
1288                         compatible = "mediatek,mt8195-i2c",
1289                                      "mediatek,mt8192-i2c";
1290                         reg = <0 0x11d00000 0 0x1000>,
1291                               <0 0x10220580 0 0x80>;
1292                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1293                         clock-div = <1>;
1294                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1295                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1296                         clock-names = "main", "dma";
1297                         #address-cells = <1>;
1298                         #size-cells = <0>;
1299                         status = "disabled";
1300                 };
1301
1302                 i2c6: i2c@11d01000 {
1303                         compatible = "mediatek,mt8195-i2c",
1304                                      "mediatek,mt8192-i2c";
1305                         reg = <0 0x11d01000 0 0x1000>,
1306                               <0 0x10220600 0 0x80>;
1307                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1308                         clock-div = <1>;
1309                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1310                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1311                         clock-names = "main", "dma";
1312                         #address-cells = <1>;
1313                         #size-cells = <0>;
1314                         status = "disabled";
1315                 };
1316
1317                 i2c7: i2c@11d02000 {
1318                         compatible = "mediatek,mt8195-i2c",
1319                                      "mediatek,mt8192-i2c";
1320                         reg = <0 0x11d02000 0 0x1000>,
1321                               <0 0x10220680 0 0x80>;
1322                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1323                         clock-div = <1>;
1324                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1325                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1326                         clock-names = "main", "dma";
1327                         #address-cells = <1>;
1328                         #size-cells = <0>;
1329                         status = "disabled";
1330                 };
1331
1332                 imp_iic_wrap_s: clock-controller@11d03000 {
1333                         compatible = "mediatek,mt8195-imp_iic_wrap_s";
1334                         reg = <0 0x11d03000 0 0x1000>;
1335                         #clock-cells = <1>;
1336                 };
1337
1338                 i2c0: i2c@11e00000 {
1339                         compatible = "mediatek,mt8195-i2c",
1340                                      "mediatek,mt8192-i2c";
1341                         reg = <0 0x11e00000 0 0x1000>,
1342                               <0 0x10220080 0 0x80>;
1343                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1344                         clock-div = <1>;
1345                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1346                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1347                         clock-names = "main", "dma";
1348                         #address-cells = <1>;
1349                         #size-cells = <0>;
1350                         status = "disabled";
1351                 };
1352
1353                 i2c1: i2c@11e01000 {
1354                         compatible = "mediatek,mt8195-i2c",
1355                                      "mediatek,mt8192-i2c";
1356                         reg = <0 0x11e01000 0 0x1000>,
1357                               <0 0x10220200 0 0x80>;
1358                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1359                         clock-div = <1>;
1360                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1361                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1362                         clock-names = "main", "dma";
1363                         #address-cells = <1>;
1364                         #size-cells = <0>;
1365                         status = "disabled";
1366                 };
1367
1368                 i2c2: i2c@11e02000 {
1369                         compatible = "mediatek,mt8195-i2c",
1370                                      "mediatek,mt8192-i2c";
1371                         reg = <0 0x11e02000 0 0x1000>,
1372                               <0 0x10220380 0 0x80>;
1373                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1374                         clock-div = <1>;
1375                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1376                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1377                         clock-names = "main", "dma";
1378                         #address-cells = <1>;
1379                         #size-cells = <0>;
1380                         status = "disabled";
1381                 };
1382
1383                 i2c3: i2c@11e03000 {
1384                         compatible = "mediatek,mt8195-i2c",
1385                                      "mediatek,mt8192-i2c";
1386                         reg = <0 0x11e03000 0 0x1000>,
1387                               <0 0x10220480 0 0x80>;
1388                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1389                         clock-div = <1>;
1390                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1391                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1392                         clock-names = "main", "dma";
1393                         #address-cells = <1>;
1394                         #size-cells = <0>;
1395                         status = "disabled";
1396                 };
1397
1398                 i2c4: i2c@11e04000 {
1399                         compatible = "mediatek,mt8195-i2c",
1400                                      "mediatek,mt8192-i2c";
1401                         reg = <0 0x11e04000 0 0x1000>,
1402                               <0 0x10220500 0 0x80>;
1403                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1404                         clock-div = <1>;
1405                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1406                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1407                         clock-names = "main", "dma";
1408                         #address-cells = <1>;
1409                         #size-cells = <0>;
1410                         status = "disabled";
1411                 };
1412
1413                 imp_iic_wrap_w: clock-controller@11e05000 {
1414                         compatible = "mediatek,mt8195-imp_iic_wrap_w";
1415                         reg = <0 0x11e05000 0 0x1000>;
1416                         #clock-cells = <1>;
1417                 };
1418
1419                 u3phy1: t-phy@11e30000 {
1420                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1421                         #address-cells = <1>;
1422                         #size-cells = <1>;
1423                         ranges = <0 0 0x11e30000 0xe00>;
1424                         power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1425                         status = "disabled";
1426
1427                         u2port1: usb-phy@0 {
1428                                 reg = <0x0 0x700>;
1429                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1430                                          <&clk26m>;
1431                                 clock-names = "ref", "da_ref";
1432                                 #phy-cells = <1>;
1433                         };
1434
1435                         u3port1: usb-phy@700 {
1436                                 reg = <0x700 0x700>;
1437                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1438                                          <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1439                                 clock-names = "ref", "da_ref";
1440                                 nvmem-cells = <&comb_intr_p1>,
1441                                               <&comb_rx_imp_p1>,
1442                                               <&comb_tx_imp_p1>;
1443                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1444                                 #phy-cells = <1>;
1445                         };
1446                 };
1447
1448                 u3phy0: t-phy@11e40000 {
1449                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1450                         #address-cells = <1>;
1451                         #size-cells = <1>;
1452                         ranges = <0 0 0x11e40000 0xe00>;
1453                         status = "disabled";
1454
1455                         u2port0: usb-phy@0 {
1456                                 reg = <0x0 0x700>;
1457                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1458                                          <&clk26m>;
1459                                 clock-names = "ref", "da_ref";
1460                                 #phy-cells = <1>;
1461                         };
1462
1463                         u3port0: usb-phy@700 {
1464                                 reg = <0x700 0x700>;
1465                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1466                                          <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1467                                 clock-names = "ref", "da_ref";
1468                                 nvmem-cells = <&u3_intr_p0>,
1469                                               <&u3_rx_imp_p0>,
1470                                               <&u3_tx_imp_p0>;
1471                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1472                                 #phy-cells = <1>;
1473                         };
1474                 };
1475
1476                 ufsphy: ufs-phy@11fa0000 {
1477                         compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1478                         reg = <0 0x11fa0000 0 0xc000>;
1479                         clocks = <&clk26m>, <&clk26m>;
1480                         clock-names = "unipro", "mp";
1481                         #phy-cells = <0>;
1482                         status = "disabled";
1483                 };
1484
1485                 mfgcfg: clock-controller@13fbf000 {
1486                         compatible = "mediatek,mt8195-mfgcfg";
1487                         reg = <0 0x13fbf000 0 0x1000>;
1488                         #clock-cells = <1>;
1489                 };
1490
1491                 vppsys0: clock-controller@14000000 {
1492                         compatible = "mediatek,mt8195-vppsys0";
1493                         reg = <0 0x14000000 0 0x1000>;
1494                         #clock-cells = <1>;
1495                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
1496                 };
1497
1498                 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1499                         compatible = "mediatek,mt8195-smi-sub-common";
1500                         reg = <0 0x14010000 0 0x1000>;
1501                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1502                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1503                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1504                         clock-names = "apb", "smi", "gals0";
1505                         mediatek,smi = <&smi_common_vpp>;
1506                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1507                 };
1508
1509                 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
1510                         compatible = "mediatek,mt8195-smi-sub-common";
1511                         reg = <0 0x14011000 0 0x1000>;
1512                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1513                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1514                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
1515                         clock-names = "apb", "smi", "gals0";
1516                         mediatek,smi = <&smi_common_vpp>;
1517                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1518                 };
1519
1520                 smi_common_vpp: smi@14012000 {
1521                         compatible = "mediatek,mt8195-smi-common-vpp";
1522                         reg = <0 0x14012000 0 0x1000>;
1523                         clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1524                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1525                                <&vppsys0 CLK_VPP0_SMI_RSI>,
1526                                <&vppsys0 CLK_VPP0_SMI_RSI>;
1527                         clock-names = "apb", "smi", "gals0", "gals1";
1528                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1529                 };
1530
1531                 larb4: larb@14013000 {
1532                         compatible = "mediatek,mt8195-smi-larb";
1533                         reg = <0 0x14013000 0 0x1000>;
1534                         mediatek,larb-id = <4>;
1535                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
1536                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1537                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
1538                         clock-names = "apb", "smi";
1539                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1540                 };
1541
1542                 iommu_vpp: iommu@14018000 {
1543                         compatible = "mediatek,mt8195-iommu-vpp";
1544                         reg = <0 0x14018000 0 0x1000>;
1545                         mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
1546                                           &larb12 &larb14 &larb16 &larb18
1547                                           &larb20 &larb22 &larb23 &larb26
1548                                           &larb27>;
1549                         interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
1550                         clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
1551                         clock-names = "bclk";
1552                         #iommu-cells = <1>;
1553                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1554                 };
1555
1556                 wpesys: clock-controller@14e00000 {
1557                         compatible = "mediatek,mt8195-wpesys";
1558                         reg = <0 0x14e00000 0 0x1000>;
1559                         #clock-cells = <1>;
1560                 };
1561
1562                 wpesys_vpp0: clock-controller@14e02000 {
1563                         compatible = "mediatek,mt8195-wpesys_vpp0";
1564                         reg = <0 0x14e02000 0 0x1000>;
1565                         #clock-cells = <1>;
1566                 };
1567
1568                 wpesys_vpp1: clock-controller@14e03000 {
1569                         compatible = "mediatek,mt8195-wpesys_vpp1";
1570                         reg = <0 0x14e03000 0 0x1000>;
1571                         #clock-cells = <1>;
1572                 };
1573
1574                 larb7: larb@14e04000 {
1575                         compatible = "mediatek,mt8195-smi-larb";
1576                         reg = <0 0x14e04000 0 0x1000>;
1577                         mediatek,larb-id = <7>;
1578                         mediatek,smi = <&smi_common_vdo>;
1579                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
1580                                  <&wpesys CLK_WPE_SMI_LARB7>;
1581                         clock-names = "apb", "smi";
1582                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1583                 };
1584
1585                 larb8: larb@14e05000 {
1586                         compatible = "mediatek,mt8195-smi-larb";
1587                         reg = <0 0x14e05000 0 0x1000>;
1588                         mediatek,larb-id = <8>;
1589                         mediatek,smi = <&smi_common_vpp>;
1590                         clocks = <&wpesys CLK_WPE_SMI_LARB8>,
1591                                <&wpesys CLK_WPE_SMI_LARB8>,
1592                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1593                         clock-names = "apb", "smi", "gals";
1594                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
1595                 };
1596
1597                 vppsys1: clock-controller@14f00000 {
1598                         compatible = "mediatek,mt8195-vppsys1";
1599                         reg = <0 0x14f00000 0 0x1000>;
1600                         #clock-cells = <1>;
1601                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
1602                 };
1603
1604                 larb5: larb@14f02000 {
1605                         compatible = "mediatek,mt8195-smi-larb";
1606                         reg = <0 0x14f02000 0 0x1000>;
1607                         mediatek,larb-id = <5>;
1608                         mediatek,smi = <&smi_common_vdo>;
1609                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1610                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1611                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
1612                         clock-names = "apb", "smi", "gals";
1613                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1614                 };
1615
1616                 larb6: larb@14f03000 {
1617                         compatible = "mediatek,mt8195-smi-larb";
1618                         reg = <0 0x14f03000 0 0x1000>;
1619                         mediatek,larb-id = <6>;
1620                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
1621                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
1622                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
1623                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
1624                         clock-names = "apb", "smi", "gals";
1625                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
1626                 };
1627
1628                 imgsys: clock-controller@15000000 {
1629                         compatible = "mediatek,mt8195-imgsys";
1630                         reg = <0 0x15000000 0 0x1000>;
1631                         #clock-cells = <1>;
1632                 };
1633
1634                 larb9: larb@15001000 {
1635                         compatible = "mediatek,mt8195-smi-larb";
1636                         reg = <0 0x15001000 0 0x1000>;
1637                         mediatek,larb-id = <9>;
1638                         mediatek,smi = <&smi_sub_common_img1_3x1>;
1639                         clocks = <&imgsys CLK_IMG_LARB9>,
1640                                  <&imgsys CLK_IMG_LARB9>,
1641                                  <&imgsys CLK_IMG_GALS>;
1642                         clock-names = "apb", "smi", "gals";
1643                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1644                 };
1645
1646                 smi_sub_common_img0_3x1: smi@15002000 {
1647                         compatible = "mediatek,mt8195-smi-sub-common";
1648                         reg = <0 0x15002000 0 0x1000>;
1649                         clocks = <&imgsys CLK_IMG_IPE>,
1650                                  <&imgsys CLK_IMG_IPE>,
1651                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
1652                         clock-names = "apb", "smi", "gals0";
1653                         mediatek,smi = <&smi_common_vpp>;
1654                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1655                 };
1656
1657                 smi_sub_common_img1_3x1: smi@15003000 {
1658                         compatible = "mediatek,mt8195-smi-sub-common";
1659                         reg = <0 0x15003000 0 0x1000>;
1660                         clocks = <&imgsys CLK_IMG_LARB9>,
1661                                  <&imgsys CLK_IMG_LARB9>,
1662                                  <&imgsys CLK_IMG_GALS>;
1663                         clock-names = "apb", "smi", "gals0";
1664                         mediatek,smi = <&smi_common_vdo>;
1665                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
1666                 };
1667
1668                 imgsys1_dip_top: clock-controller@15110000 {
1669                         compatible = "mediatek,mt8195-imgsys1_dip_top";
1670                         reg = <0 0x15110000 0 0x1000>;
1671                         #clock-cells = <1>;
1672                 };
1673
1674                 larb10: larb@15120000 {
1675                         compatible = "mediatek,mt8195-smi-larb";
1676                         reg = <0 0x15120000 0 0x1000>;
1677                         mediatek,larb-id = <10>;
1678                         mediatek,smi = <&smi_sub_common_img1_3x1>;
1679                         clocks = <&imgsys CLK_IMG_DIP0>,
1680                                <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
1681                         clock-names = "apb", "smi";
1682                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1683                 };
1684
1685                 imgsys1_dip_nr: clock-controller@15130000 {
1686                         compatible = "mediatek,mt8195-imgsys1_dip_nr";
1687                         reg = <0 0x15130000 0 0x1000>;
1688                         #clock-cells = <1>;
1689                 };
1690
1691                 imgsys1_wpe: clock-controller@15220000 {
1692                         compatible = "mediatek,mt8195-imgsys1_wpe";
1693                         reg = <0 0x15220000 0 0x1000>;
1694                         #clock-cells = <1>;
1695                 };
1696
1697                 larb11: larb@15230000 {
1698                         compatible = "mediatek,mt8195-smi-larb";
1699                         reg = <0 0x15230000 0 0x1000>;
1700                         mediatek,larb-id = <11>;
1701                         mediatek,smi = <&smi_sub_common_img1_3x1>;
1702                         clocks = <&imgsys CLK_IMG_WPE0>,
1703                                <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
1704                         clock-names = "apb", "smi";
1705                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
1706                 };
1707
1708                 ipesys: clock-controller@15330000 {
1709                         compatible = "mediatek,mt8195-ipesys";
1710                         reg = <0 0x15330000 0 0x1000>;
1711                         #clock-cells = <1>;
1712                 };
1713
1714                 larb12: larb@15340000 {
1715                         compatible = "mediatek,mt8195-smi-larb";
1716                         reg = <0 0x15340000 0 0x1000>;
1717                         mediatek,larb-id = <12>;
1718                         mediatek,smi = <&smi_sub_common_img0_3x1>;
1719                         clocks = <&ipesys CLK_IPE_SMI_LARB12>,
1720                                  <&ipesys CLK_IPE_SMI_LARB12>;
1721                         clock-names = "apb", "smi";
1722                         power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
1723                 };
1724
1725                 camsys: clock-controller@16000000 {
1726                         compatible = "mediatek,mt8195-camsys";
1727                         reg = <0 0x16000000 0 0x1000>;
1728                         #clock-cells = <1>;
1729                 };
1730
1731                 larb13: larb@16001000 {
1732                         compatible = "mediatek,mt8195-smi-larb";
1733                         reg = <0 0x16001000 0 0x1000>;
1734                         mediatek,larb-id = <13>;
1735                         mediatek,smi = <&smi_sub_common_cam_4x1>;
1736                         clocks = <&camsys CLK_CAM_LARB13>,
1737                                <&camsys CLK_CAM_LARB13>,
1738                                <&camsys CLK_CAM_CAM2MM0_GALS>;
1739                         clock-names = "apb", "smi", "gals";
1740                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1741                 };
1742
1743                 larb14: larb@16002000 {
1744                         compatible = "mediatek,mt8195-smi-larb";
1745                         reg = <0 0x16002000 0 0x1000>;
1746                         mediatek,larb-id = <14>;
1747                         mediatek,smi = <&smi_sub_common_cam_7x1>;
1748                         clocks = <&camsys CLK_CAM_LARB14>,
1749                                  <&camsys CLK_CAM_LARB14>;
1750                         clock-names = "apb", "smi";
1751                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1752                 };
1753
1754                 smi_sub_common_cam_4x1: smi@16004000 {
1755                         compatible = "mediatek,mt8195-smi-sub-common";
1756                         reg = <0 0x16004000 0 0x1000>;
1757                         clocks = <&camsys CLK_CAM_LARB13>,
1758                                  <&camsys CLK_CAM_LARB13>,
1759                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
1760                         clock-names = "apb", "smi", "gals0";
1761                         mediatek,smi = <&smi_common_vdo>;
1762                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1763                 };
1764
1765                 smi_sub_common_cam_7x1: smi@16005000 {
1766                         compatible = "mediatek,mt8195-smi-sub-common";
1767                         reg = <0 0x16005000 0 0x1000>;
1768                         clocks = <&camsys CLK_CAM_LARB14>,
1769                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
1770                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
1771                         clock-names = "apb", "smi", "gals0";
1772                         mediatek,smi = <&smi_common_vpp>;
1773                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1774                 };
1775
1776                 larb16: larb@16012000 {
1777                         compatible = "mediatek,mt8195-smi-larb";
1778                         reg = <0 0x16012000 0 0x1000>;
1779                         mediatek,larb-id = <16>;
1780                         mediatek,smi = <&smi_sub_common_cam_7x1>;
1781                         clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
1782                                  <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1783                         clock-names = "apb", "smi";
1784                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1785                 };
1786
1787                 larb17: larb@16013000 {
1788                         compatible = "mediatek,mt8195-smi-larb";
1789                         reg = <0 0x16013000 0 0x1000>;
1790                         mediatek,larb-id = <17>;
1791                         mediatek,smi = <&smi_sub_common_cam_4x1>;
1792                         clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
1793                                  <&camsys_yuva CLK_CAM_YUVA_LARBX>;
1794                         clock-names = "apb", "smi";
1795                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
1796                 };
1797
1798                 larb27: larb@16014000 {
1799                         compatible = "mediatek,mt8195-smi-larb";
1800                         reg = <0 0x16014000 0 0x1000>;
1801                         mediatek,larb-id = <27>;
1802                         mediatek,smi = <&smi_sub_common_cam_7x1>;
1803                         clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
1804                                  <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1805                         clock-names = "apb", "smi";
1806                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1807                 };
1808
1809                 larb28: larb@16015000 {
1810                         compatible = "mediatek,mt8195-smi-larb";
1811                         reg = <0 0x16015000 0 0x1000>;
1812                         mediatek,larb-id = <28>;
1813                         mediatek,smi = <&smi_sub_common_cam_4x1>;
1814                         clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
1815                                  <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
1816                         clock-names = "apb", "smi";
1817                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
1818                 };
1819
1820                 camsys_rawa: clock-controller@1604f000 {
1821                         compatible = "mediatek,mt8195-camsys_rawa";
1822                         reg = <0 0x1604f000 0 0x1000>;
1823                         #clock-cells = <1>;
1824                 };
1825
1826                 camsys_yuva: clock-controller@1606f000 {
1827                         compatible = "mediatek,mt8195-camsys_yuva";
1828                         reg = <0 0x1606f000 0 0x1000>;
1829                         #clock-cells = <1>;
1830                 };
1831
1832                 camsys_rawb: clock-controller@1608f000 {
1833                         compatible = "mediatek,mt8195-camsys_rawb";
1834                         reg = <0 0x1608f000 0 0x1000>;
1835                         #clock-cells = <1>;
1836                 };
1837
1838                 camsys_yuvb: clock-controller@160af000 {
1839                         compatible = "mediatek,mt8195-camsys_yuvb";
1840                         reg = <0 0x160af000 0 0x1000>;
1841                         #clock-cells = <1>;
1842                 };
1843
1844                 camsys_mraw: clock-controller@16140000 {
1845                         compatible = "mediatek,mt8195-camsys_mraw";
1846                         reg = <0 0x16140000 0 0x1000>;
1847                         #clock-cells = <1>;
1848                 };
1849
1850                 larb25: larb@16141000 {
1851                         compatible = "mediatek,mt8195-smi-larb";
1852                         reg = <0 0x16141000 0 0x1000>;
1853                         mediatek,larb-id = <25>;
1854                         mediatek,smi = <&smi_sub_common_cam_4x1>;
1855                         clocks = <&camsys CLK_CAM_LARB13>,
1856                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>,
1857                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
1858                         clock-names = "apb", "smi", "gals";
1859                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1860                 };
1861
1862                 larb26: larb@16142000 {
1863                         compatible = "mediatek,mt8195-smi-larb";
1864                         reg = <0 0x16142000 0 0x1000>;
1865                         mediatek,larb-id = <26>;
1866                         mediatek,smi = <&smi_sub_common_cam_7x1>;
1867                         clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
1868                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>;
1869                         clock-names = "apb", "smi";
1870                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
1871
1872                 };
1873
1874                 ccusys: clock-controller@17200000 {
1875                         compatible = "mediatek,mt8195-ccusys";
1876                         reg = <0 0x17200000 0 0x1000>;
1877                         #clock-cells = <1>;
1878                 };
1879
1880                 larb18: larb@17201000 {
1881                         compatible = "mediatek,mt8195-smi-larb";
1882                         reg = <0 0x17201000 0 0x1000>;
1883                         mediatek,larb-id = <18>;
1884                         mediatek,smi = <&smi_sub_common_cam_7x1>;
1885                         clocks = <&ccusys CLK_CCU_LARB18>,
1886                                  <&ccusys CLK_CCU_LARB18>;
1887                         clock-names = "apb", "smi";
1888                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
1889                 };
1890
1891                 larb24: larb@1800d000 {
1892                         compatible = "mediatek,mt8195-smi-larb";
1893                         reg = <0 0x1800d000 0 0x1000>;
1894                         mediatek,larb-id = <24>;
1895                         mediatek,smi = <&smi_common_vdo>;
1896                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1897                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1898                         clock-names = "apb", "smi";
1899                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1900                 };
1901
1902                 larb23: larb@1800e000 {
1903                         compatible = "mediatek,mt8195-smi-larb";
1904                         reg = <0 0x1800e000 0 0x1000>;
1905                         mediatek,larb-id = <23>;
1906                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
1907                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1908                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1909                         clock-names = "apb", "smi";
1910                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
1911                 };
1912
1913                 vdecsys_soc: clock-controller@1800f000 {
1914                         compatible = "mediatek,mt8195-vdecsys_soc";
1915                         reg = <0 0x1800f000 0 0x1000>;
1916                         #clock-cells = <1>;
1917                 };
1918
1919                 larb21: larb@1802e000 {
1920                         compatible = "mediatek,mt8195-smi-larb";
1921                         reg = <0 0x1802e000 0 0x1000>;
1922                         mediatek,larb-id = <21>;
1923                         mediatek,smi = <&smi_common_vdo>;
1924                         clocks = <&vdecsys CLK_VDEC_LARB1>,
1925                                  <&vdecsys CLK_VDEC_LARB1>;
1926                         clock-names = "apb", "smi";
1927                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
1928                 };
1929
1930                 vdecsys: clock-controller@1802f000 {
1931                         compatible = "mediatek,mt8195-vdecsys";
1932                         reg = <0 0x1802f000 0 0x1000>;
1933                         #clock-cells = <1>;
1934                 };
1935
1936                 larb22: larb@1803e000 {
1937                         compatible = "mediatek,mt8195-smi-larb";
1938                         reg = <0 0x1803e000 0 0x1000>;
1939                         mediatek,larb-id = <22>;
1940                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
1941                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1942                                  <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
1943                         clock-names = "apb", "smi";
1944                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
1945                 };
1946
1947                 vdecsys_core1: clock-controller@1803f000 {
1948                         compatible = "mediatek,mt8195-vdecsys_core1";
1949                         reg = <0 0x1803f000 0 0x1000>;
1950                         #clock-cells = <1>;
1951                 };
1952
1953                 apusys_pll: clock-controller@190f3000 {
1954                         compatible = "mediatek,mt8195-apusys_pll";
1955                         reg = <0 0x190f3000 0 0x1000>;
1956                         #clock-cells = <1>;
1957                 };
1958
1959                 vencsys: clock-controller@1a000000 {
1960                         compatible = "mediatek,mt8195-vencsys";
1961                         reg = <0 0x1a000000 0 0x1000>;
1962                         #clock-cells = <1>;
1963                 };
1964
1965                 larb19: larb@1a010000 {
1966                         compatible = "mediatek,mt8195-smi-larb";
1967                         reg = <0 0x1a010000 0 0x1000>;
1968                         mediatek,larb-id = <19>;
1969                         mediatek,smi = <&smi_common_vdo>;
1970                         clocks = <&vencsys CLK_VENC_VENC>,
1971                                  <&vencsys CLK_VENC_GALS>;
1972                         clock-names = "apb", "smi";
1973                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
1974                 };
1975
1976                 vencsys_core1: clock-controller@1b000000 {
1977                         compatible = "mediatek,mt8195-vencsys_core1";
1978                         reg = <0 0x1b000000 0 0x1000>;
1979                         #clock-cells = <1>;
1980                 };
1981
1982                 vdosys0: syscon@1c01a000 {
1983                         compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
1984                         reg = <0 0x1c01a000 0 0x1000>;
1985                         mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
1986                         #clock-cells = <1>;
1987                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
1988                 };
1989
1990                 larb20: larb@1b010000 {
1991                         compatible = "mediatek,mt8195-smi-larb";
1992                         reg = <0 0x1b010000 0 0x1000>;
1993                         mediatek,larb-id = <20>;
1994                         mediatek,smi = <&smi_common_vpp>;
1995                         clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
1996                                  <&vencsys_core1 CLK_VENC_CORE1_GALS>,
1997                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
1998                         clock-names = "apb", "smi", "gals";
1999                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2000                 };
2001
2002                 ovl0: ovl@1c000000 {
2003                         compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
2004                         reg = <0 0x1c000000 0 0x1000>;
2005                         interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
2006                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2007                         clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
2008                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
2009                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2010                 };
2011
2012                 rdma0: rdma@1c002000 {
2013                         compatible = "mediatek,mt8195-disp-rdma";
2014                         reg = <0 0x1c002000 0 0x1000>;
2015                         interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
2016                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2017                         clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
2018                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
2019                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2020                 };
2021
2022                 color0: color@1c003000 {
2023                         compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2024                         reg = <0 0x1c003000 0 0x1000>;
2025                         interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
2026                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2027                         clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
2028                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2029                 };
2030
2031                 ccorr0: ccorr@1c004000 {
2032                         compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2033                         reg = <0 0x1c004000 0 0x1000>;
2034                         interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
2035                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2036                         clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
2037                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2038                 };
2039
2040                 aal0: aal@1c005000 {
2041                         compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2042                         reg = <0 0x1c005000 0 0x1000>;
2043                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
2044                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2045                         clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
2046                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2047                 };
2048
2049                 gamma0: gamma@1c006000 {
2050                         compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2051                         reg = <0 0x1c006000 0 0x1000>;
2052                         interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
2053                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2054                         clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
2055                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2056                 };
2057
2058                 dither0: dither@1c007000 {
2059                         compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2060                         reg = <0 0x1c007000 0 0x1000>;
2061                         interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
2062                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2063                         clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
2064                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2065                 };
2066
2067                 dsc0: dsc@1c009000 {
2068                         compatible = "mediatek,mt8195-disp-dsc";
2069                         reg = <0 0x1c009000 0 0x1000>;
2070                         interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
2071                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2072                         clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
2073                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2074                 };
2075
2076                 merge0: merge@1c014000 {
2077                         compatible = "mediatek,mt8195-disp-merge";
2078                         reg = <0 0x1c014000 0 0x1000>;
2079                         interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2080                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2081                         clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2082                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2083                 };
2084
2085                 mutex: mutex@1c016000 {
2086                         compatible = "mediatek,mt8195-disp-mutex";
2087                         reg = <0 0x1c016000 0 0x1000>;
2088                         interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2089                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2090                         clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2091                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
2092                         mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2093                 };
2094
2095                 larb0: larb@1c018000 {
2096                         compatible = "mediatek,mt8195-smi-larb";
2097                         reg = <0 0x1c018000 0 0x1000>;
2098                         mediatek,larb-id = <0>;
2099                         mediatek,smi = <&smi_common_vdo>;
2100                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2101                                  <&vdosys0 CLK_VDO0_SMI_LARB>,
2102                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
2103                         clock-names = "apb", "smi", "gals";
2104                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2105                 };
2106
2107                 larb1: larb@1c019000 {
2108                         compatible = "mediatek,mt8195-smi-larb";
2109                         reg = <0 0x1c019000 0 0x1000>;
2110                         mediatek,larb-id = <1>;
2111                         mediatek,smi = <&smi_common_vpp>;
2112                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2113                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2114                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2115                         clock-names = "apb", "smi", "gals";
2116                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2117                 };
2118
2119                 vdosys1: syscon@1c100000 {
2120                         compatible = "mediatek,mt8195-vdosys1", "syscon";
2121                         reg = <0 0x1c100000 0 0x1000>;
2122                         #clock-cells = <1>;
2123                 };
2124
2125                 smi_common_vdo: smi@1c01b000 {
2126                         compatible = "mediatek,mt8195-smi-common-vdo";
2127                         reg = <0 0x1c01b000 0 0x1000>;
2128                         clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
2129                                  <&vdosys0 CLK_VDO0_SMI_EMI>,
2130                                  <&vdosys0 CLK_VDO0_SMI_RSI>,
2131                                  <&vdosys0 CLK_VDO0_SMI_GALS>;
2132                         clock-names = "apb", "smi", "gals0", "gals1";
2133                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2134
2135                 };
2136
2137                 iommu_vdo: iommu@1c01f000 {
2138                         compatible = "mediatek,mt8195-iommu-vdo";
2139                         reg = <0 0x1c01f000 0 0x1000>;
2140                         mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
2141                                           &larb10 &larb11 &larb13 &larb17
2142                                           &larb19 &larb21 &larb24 &larb25
2143                                           &larb28>;
2144                         interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
2145                         #iommu-cells = <1>;
2146                         clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
2147                         clock-names = "bclk";
2148                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2149                 };
2150
2151                 larb2: larb@1c102000 {
2152                         compatible = "mediatek,mt8195-smi-larb";
2153                         reg = <0 0x1c102000 0 0x1000>;
2154                         mediatek,larb-id = <2>;
2155                         mediatek,smi = <&smi_common_vdo>;
2156                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
2157                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
2158                                  <&vdosys1 CLK_VDO1_GALS>;
2159                         clock-names = "apb", "smi", "gals";
2160                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2161                 };
2162
2163                 larb3: larb@1c103000 {
2164                         compatible = "mediatek,mt8195-smi-larb";
2165                         reg = <0 0x1c103000 0 0x1000>;
2166                         mediatek,larb-id = <3>;
2167                         mediatek,smi = <&smi_common_vpp>;
2168                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2169                                  <&vdosys1 CLK_VDO1_GALS>,
2170                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2171                         clock-names = "apb", "smi", "gals";
2172                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2173                 };
2174         };
2175 };