arch/arm64/boot/dts/mediatek/mt8195-demo.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2022 BayLibre, SAS.
   4  * Author: Fabien Parent <fparent@baylibre.com>
   5  */
   6 /dts-v1/;
   7
   8 #include "mt8195.dtsi"
   9 #include "mt6359.dtsi"
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  14 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
  15
  16 / {
  17         model = "MediaTek MT8195 demo board";
  18         compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:921600n8";
  26         };
  27
  28         firmware {
  29                 optee {
  30                         compatible = "linaro,optee-tz";
  31                         method = "smc";
  32                 };
  33         };
  34
  35         gpio-keys {
  36                 compatible = "gpio-keys";
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&gpio_keys_pins>;
  39
  40                 key-0 {
  41                         gpios = <&pio 106 GPIO_ACTIVE_LOW>;
  42                         label = "volume_up";
  43                         linux,code = <KEY_VOLUMEUP>;
  44                         wakeup-source;
  45                         debounce-interval = <15>;
  46                 };
  47         };
  48
  49         memory@40000000 {
  50                 device_type = "memory";
  51                 reg = <0 0x40000000 0x2 0x00000000>;
  52         };
  53
  54         reserved-memory {
  55                 #address-cells = <2>;
  56                 #size-cells = <2>;
  57                 ranges;
  58
  59                 /*
  60                  * 12 MiB reserved for OP-TEE (BL32)
  61                  * +-----------------------+ 0x43e0_0000
  62                  * |      SHMEM 2MiB       |
  63                  * +-----------------------+ 0x43c0_0000
  64                  * |        | TA_RAM  8MiB |
  65                  * + TZDRAM +--------------+ 0x4340_0000
  66                  * |        | TEE_RAM 2MiB |
  67                  * +-----------------------+ 0x4320_0000
  68                  */
  69                 optee_reserved: optee@43200000 {
  70                         no-map;
  71                         reg = <0 0x43200000 0 0x00c00000>;
  72                 };
  73
  74                 scp_mem: memory@50000000 {
  75                         compatible = "shared-dma-pool";
  76                         reg = <0 0x50000000 0 0x2900000>;
  77                         no-map;
  78                 };
  79
  80                 vpu_mem: memory@53000000 {
  81                         compatible = "shared-dma-pool";
  82                         reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
  83                 };
  84
  85                 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
  86                 bl31_secmon_mem: memory@54600000 {
  87                         no-map;
  88                         reg = <0 0x54600000 0x0 0x200000>;
  89                 };
  90
  91                 snd_dma_mem: memory@60000000 {
  92                         compatible = "shared-dma-pool";
  93                         reg = <0 0x60000000 0 0x1100000>;
  94                         no-map;
  95                 };
  96
  97                 apu_mem: memory@62000000 {
  98                         compatible = "shared-dma-pool";
  99                         reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
 100                 };
 101         };
 102 };
 103
 104 &i2c6 {
 105         clock-frequency = <400000>;
 106         pinctrl-0 = <&i2c6_pins>;
 107         pinctrl-names = "default";
 108         status = "okay";
 109
 110         mt6360: pmic@34 {
 111                 compatible = "mediatek,mt6360";
 112                 reg = <0x34>;
 113                 interrupt-controller;
 114                 #interrupt-cells = <1>;
 115                 interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>;
 116                 interrupt-names = "IRQB";
 117
 118                 charger {
 119                         compatible = "mediatek,mt6360-chg";
 120                         richtek,vinovp-microvolt = <14500000>;
 121
 122                         otg_vbus_regulator: usb-otg-vbus-regulator {
 123                                 regulator-compatible = "usb-otg-vbus";
 124                                 regulator-name = "usb-otg-vbus";
 125                                 regulator-min-microvolt = <4425000>;
 126                                 regulator-max-microvolt = <5825000>;
 127                         };
 128                 };
 129
 130                 regulator {
 131                         compatible = "mediatek,mt6360-regulator";
 132                         LDO_VIN3-supply = <&mt6360_buck2>;
 133
 134                         mt6360_buck1: buck1 {
 135                                 regulator-compatible = "BUCK1";
 136                                 regulator-name = "mt6360,buck1";
 137                                 regulator-min-microvolt = <300000>;
 138                                 regulator-max-microvolt = <1300000>;
 139                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 140                                                            MT6360_OPMODE_LP
 141                                                            MT6360_OPMODE_ULP>;
 142                                 regulator-always-on;
 143                         };
 144
 145                         mt6360_buck2: buck2 {
 146                                 regulator-compatible = "BUCK2";
 147                                 regulator-name = "mt6360,buck2";
 148                                 regulator-min-microvolt = <300000>;
 149                                 regulator-max-microvolt = <1300000>;
 150                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 151                                                            MT6360_OPMODE_LP
 152                                                            MT6360_OPMODE_ULP>;
 153                                 regulator-always-on;
 154                         };
 155
 156                         mt6360_ldo1: ldo1 {
 157                                 regulator-compatible = "LDO1";
 158                                 regulator-name = "mt6360,ldo1";
 159                                 regulator-min-microvolt = <1200000>;
 160                                 regulator-max-microvolt = <3600000>;
 161                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 162                                                            MT6360_OPMODE_LP>;
 163                         };
 164
 165                         mt6360_ldo2: ldo2 {
 166                                 regulator-compatible = "LDO2";
 167                                 regulator-name = "mt6360,ldo2";
 168                                 regulator-min-microvolt = <1200000>;
 169                                 regulator-max-microvolt = <3600000>;
 170                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 171                                                            MT6360_OPMODE_LP>;
 172                         };
 173
 174                         mt6360_ldo3: ldo3 {
 175                                 regulator-compatible = "LDO3";
 176                                 regulator-name = "mt6360,ldo3";
 177                                 regulator-min-microvolt = <1200000>;
 178                                 regulator-max-microvolt = <3600000>;
 179                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 180                                                            MT6360_OPMODE_LP>;
 181                         };
 182
 183                         mt6360_ldo5: ldo5 {
 184                                 regulator-compatible = "LDO5";
 185                                 regulator-name = "mt6360,ldo5";
 186                                 regulator-min-microvolt = <2700000>;
 187                                 regulator-max-microvolt = <3600000>;
 188                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 189                                                            MT6360_OPMODE_LP>;
 190                         };
 191
 192                         mt6360_ldo6: ldo6 {
 193                                 regulator-compatible = "LDO6";
 194                                 regulator-name = "mt6360,ldo6";
 195                                 regulator-min-microvolt = <500000>;
 196                                 regulator-max-microvolt = <2100000>;
 197                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 198                                                            MT6360_OPMODE_LP>;
 199                         };
 200
 201                         mt6360_ldo7: ldo7 {
 202                                 regulator-compatible = "LDO7";
 203                                 regulator-name = "mt6360,ldo7";
 204                                 regulator-min-microvolt = <500000>;
 205                                 regulator-max-microvolt = <2100000>;
 206                                 regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 207                                                            MT6360_OPMODE_LP>;
 208                                 regulator-always-on;
 209                         };
 210                 };
 211         };
 212 };
 213
 214 &mmc0 {
 215         status = "okay";
 216         pinctrl-names = "default", "state_uhs";
 217         pinctrl-0 = <&mmc0_default_pins>;
 218         pinctrl-1 = <&mmc0_uhs_pins>;
 219         bus-width = <8>;
 220         max-frequency = <200000000>;
 221         cap-mmc-highspeed;
 222         mmc-hs200-1_8v;
 223         mmc-hs400-1_8v;
 224         cap-mmc-hw-reset;
 225         no-sdio;
 226         no-sd;
 227         hs400-ds-delay = <0x14c11>;
 228         vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
 229         vqmmc-supply = <&mt6359_vufs_ldo_reg>;
 230         non-removable;
 231 };
 232
 233 &mmc1 {
 234         pinctrl-names = "default", "state_uhs";
 235         pinctrl-0 = <&mmc1_default_pins>;
 236         pinctrl-1 = <&mmc1_uhs_pins>;
 237         cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>;
 238         bus-width = <4>;
 239         max-frequency = <200000000>;
 240         cap-sd-highspeed;
 241         sd-uhs-sdr50;
 242         sd-uhs-sdr104;
 243         vmmc-supply = <&mt6360_ldo5>;
 244         vqmmc-supply = <&mt6360_ldo3>;
 245         status = "okay";
 246 };
 247
 248 &mt6359_vbbck_ldo_reg {
 249         regulator-always-on;
 250 };
 251
 252 &mt6359_vcore_buck_reg {
 253         regulator-always-on;
 254 };
 255
 256 &mt6359_vgpu11_buck_reg {
 257         regulator-always-on;
 258 };
 259
 260 &mt6359_vproc1_buck_reg {
 261         regulator-always-on;
 262 };
 263
 264 &mt6359_vproc2_buck_reg {
 265         regulator-always-on;
 266 };
 267
 268 &mt6359_vpu_buck_reg {
 269         regulator-always-on;
 270 };
 271
 272 &mt6359_vrf12_ldo_reg {
 273         regulator-always-on;
 274 };
 275
 276 &mt6359_vsram_md_ldo_reg {
 277         regulator-always-on;
 278 };
 279
 280 &mt6359_vsram_others_ldo_reg {
 281         regulator-always-on;
 282 };
 283
 284 &pio {
 285         gpio_keys_pins: gpio-keys-pins {
 286                 pins {
 287                         pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
 288                         input-enable;
 289                 };
 290         };
 291
 292         i2c6_pins: i2c6-pins {
 293                 pins {
 294                         pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
 295                                  <PINMUX_GPIO26__FUNC_SCL6>;
 296                         bias-pull-up;
 297                 };
 298         };
 299
 300         mmc0_default_pins: mmc0-default-pins {
 301                 pins-clk {
 302                         pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
 303                         drive-strength = <MTK_DRIVE_6mA>;
 304                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 305                 };
 306
 307                 pins-cmd-dat {
 308                         pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
 309                                  <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
 310                                  <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
 311                                  <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
 312                                  <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
 313                                  <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
 314                                  <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
 315                                  <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
 316                                  <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
 317                         input-enable;
 318                         drive-strength = <MTK_DRIVE_6mA>;
 319                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 320                 };
 321
 322                 pins-rst {
 323                         pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
 324                         drive-strength = <MTK_DRIVE_6mA>;
 325                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 326                 };
 327         };
 328
 329         mmc0_uhs_pins: mmc0-uhs-pins {
 330                 pins-clk {
 331                         pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
 332                         drive-strength = <MTK_DRIVE_8mA>;
 333                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 334                 };
 335
 336                 pins-cmd-dat {
 337                         pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
 338                                  <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
 339                                  <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
 340                                  <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
 341                                  <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
 342                                  <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
 343                                  <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
 344                                  <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
 345                                  <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
 346                         input-enable;
 347                         drive-strength = <MTK_DRIVE_8mA>;
 348                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 349                 };
 350
 351                 pins-ds {
 352                         pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
 353                         drive-strength = <MTK_DRIVE_8mA>;
 354                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 355                 };
 356
 357                 pins-rst {
 358                         pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
 359                         drive-strength = <MTK_DRIVE_8mA>;
 360                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 361                 };
 362         };
 363
 364         mmc1_default_pins: mmc1-default-pins {
 365                 pins-clk {
 366                         pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
 367                         drive-strength = <MTK_DRIVE_8mA>;
 368                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 369                 };
 370
 371                 pins-cmd-dat {
 372                         pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
 373                                  <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
 374                                  <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
 375                                  <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
 376                                  <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
 377                         input-enable;
 378                         drive-strength = <MTK_DRIVE_8mA>;
 379                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 380                 };
 381
 382                 pins-insert {
 383                         pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
 384                         bias-pull-up;
 385                 };
 386         };
 387
 388         mmc1_uhs_pins: mmc1-uhs-pins {
 389                 pins-clk {
 390                         pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
 391                         drive-strength = <MTK_DRIVE_8mA>;
 392                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 393                 };
 394
 395                 pins-cmd-dat {
 396                         pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
 397                                  <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
 398                                  <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
 399                                  <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
 400                                  <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
 401                         input-enable;
 402                         drive-strength = <MTK_DRIVE_8mA>;
 403                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 404                 };
 405         };
 406
 407         uart0_pins: uart0-pins {
 408                 pins {
 409                         pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
 410                                  <PINMUX_GPIO99__FUNC_URXD0>;
 411                 };
 412         };
 413
 414         uart1_pins: uart1-pins {
 415                 pins {
 416                         pinmux = <PINMUX_GPIO102__FUNC_UTXD1>,
 417                                  <PINMUX_GPIO103__FUNC_URXD1>;
 418                 };
 419         };
 420 };
 421
 422
 423 &pmic {
 424         interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
 425 };
 426
 427 &uart0 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&uart0_pins>;
 430         status = "okay";
 431 };
 432
 433 &uart1 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&uart1_pins>;
 436         status = "okay";
 437 };
 438
 439 &u3phy0 {
 440         status = "okay";
 441 };
 442
 443 &u3phy1 {
 444         status = "okay";
 445 };
 446
 447 &u3phy2 {
 448         status = "okay";
 449 };
 450
 451 &u3phy3 {
 452         status = "okay";
 453 };
 454
 455 &xhci0 {
 456         vusb33-supply = <&mt6359_vusb_ldo_reg>;
 457         vbus-supply = <&otg_vbus_regulator>;
 458         status = "okay";
 459 };
 460
 461 &xhci1 {
 462         vusb33-supply = <&mt6359_vusb_ldo_reg>;
 463         status = "okay";
 464 };
 465
 466 &xhci2 {
 467         vusb33-supply = <&mt6359_vusb_ldo_reg>;
 468         status = "okay";
 469 };
 470
 471 &xhci3 {
 472         vusb33-supply = <&mt6359_vusb_ldo_reg>;
 473         status = "okay";
 474 };