arch/arm64/boot/dts/mediatek/mt8192.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2020 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8192-clk.h>
   9 #include <dt-bindings/gce/mt8192-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8192-larb-port.h>
  13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
  14 #include <dt-bindings/phy/phy.h>
  15 #include <dt-bindings/power/mt8192-power.h>
  16 #include <dt-bindings/reset/mt8192-resets.h>
  17
  18 / {
  19         compatible = "mediatek,mt8192";
  20         interrupt-parent = <&gic>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 ovl0 = &ovl0;
  26                 ovl-2l0 = &ovl_2l0;
  27                 ovl-2l2 = &ovl_2l2;
  28                 rdma0 = &rdma0;
  29                 rdma4 = &rdma4;
  30         };
  31
  32         clk13m: fixed-factor-clock-13m {
  33                 compatible = "fixed-factor-clock";
  34                 #clock-cells = <0>;
  35                 clocks = <&clk26m>;
  36                 clock-div = <2>;
  37                 clock-mult = <1>;
  38                 clock-output-names = "clk13m";
  39         };
  40
  41         clk26m: oscillator0 {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <26000000>;
  45                 clock-output-names = "clk26m";
  46         };
  47
  48         clk32k: oscillator1 {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <32768>;
  52                 clock-output-names = "clk32k";
  53         };
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu0: cpu@0 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a55";
  62                         reg = <0x000>;
  63                         enable-method = "psci";
  64                         clock-frequency = <1701000000>;
  65                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  66                         next-level-cache = <&l2_0>;
  67                         performance-domains = <&performance 0>;
  68                         capacity-dmips-mhz = <427>;
  69                 };
  70
  71                 cpu1: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a55";
  74                         reg = <0x100>;
  75                         enable-method = "psci";
  76                         clock-frequency = <1701000000>;
  77                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  78                         next-level-cache = <&l2_0>;
  79                         performance-domains = <&performance 0>;
  80                         capacity-dmips-mhz = <427>;
  81                 };
  82
  83                 cpu2: cpu@200 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a55";
  86                         reg = <0x200>;
  87                         enable-method = "psci";
  88                         clock-frequency = <1701000000>;
  89                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
  90                         next-level-cache = <&l2_0>;
  91                         performance-domains = <&performance 0>;
  92                         capacity-dmips-mhz = <427>;
  93                 };
  94
  95                 cpu3: cpu@300 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a55";
  98                         reg = <0x300>;
  99                         enable-method = "psci";
 100                         clock-frequency = <1701000000>;
 101                         cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
 102                         next-level-cache = <&l2_0>;
 103                         performance-domains = <&performance 0>;
 104                         capacity-dmips-mhz = <427>;
 105                 };
 106
 107                 cpu4: cpu@400 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a76";
 110                         reg = <0x400>;
 111                         enable-method = "psci";
 112                         clock-frequency = <2171000000>;
 113                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 114                         next-level-cache = <&l2_1>;
 115                         performance-domains = <&performance 1>;
 116                         capacity-dmips-mhz = <1024>;
 117                 };
 118
 119                 cpu5: cpu@500 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a76";
 122                         reg = <0x500>;
 123                         enable-method = "psci";
 124                         clock-frequency = <2171000000>;
 125                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 126                         next-level-cache = <&l2_1>;
 127                         performance-domains = <&performance 1>;
 128                         capacity-dmips-mhz = <1024>;
 129                 };
 130
 131                 cpu6: cpu@600 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a76";
 134                         reg = <0x600>;
 135                         enable-method = "psci";
 136                         clock-frequency = <2171000000>;
 137                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 138                         next-level-cache = <&l2_1>;
 139                         performance-domains = <&performance 1>;
 140                         capacity-dmips-mhz = <1024>;
 141                 };
 142
 143                 cpu7: cpu@700 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a76";
 146                         reg = <0x700>;
 147                         enable-method = "psci";
 148                         clock-frequency = <2171000000>;
 149                         cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
 150                         next-level-cache = <&l2_1>;
 151                         performance-domains = <&performance 1>;
 152                         capacity-dmips-mhz = <1024>;
 153                 };
 154
 155                 cpu-map {
 156                         cluster0 {
 157                                 core0 {
 158                                         cpu = <&cpu0>;
 159                                 };
 160                                 core1 {
 161                                         cpu = <&cpu1>;
 162                                 };
 163                                 core2 {
 164                                         cpu = <&cpu2>;
 165                                 };
 166                                 core3 {
 167                                         cpu = <&cpu3>;
 168                                 };
 169                                 core4 {
 170                                         cpu = <&cpu4>;
 171                                 };
 172                                 core5 {
 173                                         cpu = <&cpu5>;
 174                                 };
 175                                 core6 {
 176                                         cpu = <&cpu6>;
 177                                 };
 178                                 core7 {
 179                                         cpu = <&cpu7>;
 180                                 };
 181                         };
 182                 };
 183
 184                 l2_0: l2-cache0 {
 185                         compatible = "cache";
 186                         next-level-cache = <&l3_0>;
 187                 };
 188
 189                 l2_1: l2-cache1 {
 190                         compatible = "cache";
 191                         next-level-cache = <&l3_0>;
 192                 };
 193
 194                 l3_0: l3-cache {
 195                         compatible = "cache";
 196                 };
 197
 198                 idle-states {
 199                         entry-method = "psci";
 200                         cpu_sleep_l: cpu-sleep-l {
 201                                 compatible = "arm,idle-state";
 202                                 arm,psci-suspend-param = <0x00010001>;
 203                                 local-timer-stop;
 204                                 entry-latency-us = <55>;
 205                                 exit-latency-us = <140>;
 206                                 min-residency-us = <780>;
 207                         };
 208                         cpu_sleep_b: cpu-sleep-b {
 209                                 compatible = "arm,idle-state";
 210                                 arm,psci-suspend-param = <0x00010001>;
 211                                 local-timer-stop;
 212                                 entry-latency-us = <35>;
 213                                 exit-latency-us = <145>;
 214                                 min-residency-us = <720>;
 215                         };
 216                         cluster_sleep_l: cluster-sleep-l {
 217                                 compatible = "arm,idle-state";
 218                                 arm,psci-suspend-param = <0x01010002>;
 219                                 local-timer-stop;
 220                                 entry-latency-us = <60>;
 221                                 exit-latency-us = <155>;
 222                                 min-residency-us = <860>;
 223                         };
 224                         cluster_sleep_b: cluster-sleep-b {
 225                                 compatible = "arm,idle-state";
 226                                 arm,psci-suspend-param = <0x01010002>;
 227                                 local-timer-stop;
 228                                 entry-latency-us = <40>;
 229                                 exit-latency-us = <155>;
 230                                 min-residency-us = <780>;
 231                         };
 232                 };
 233         };
 234
 235         pmu-a55 {
 236                 compatible = "arm,cortex-a55-pmu";
 237                 interrupt-parent = <&gic>;
 238                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 239         };
 240
 241         pmu-a76 {
 242                 compatible = "arm,cortex-a76-pmu";
 243                 interrupt-parent = <&gic>;
 244                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 245         };
 246
 247         psci {
 248                 compatible = "arm,psci-1.0";
 249                 method = "smc";
 250         };
 251
 252         timer: timer {
 253                 compatible = "arm,armv8-timer";
 254                 interrupt-parent = <&gic>;
 255                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 256                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 257                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 258                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 259                 clock-frequency = <13000000>;
 260         };
 261
 262         soc {
 263                 #address-cells = <2>;
 264                 #size-cells = <2>;
 265                 compatible = "simple-bus";
 266                 ranges;
 267
 268                 performance: performance-controller@11bc10 {
 269                         compatible = "mediatek,cpufreq-hw";
 270                         reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
 271                         #performance-domain-cells = <1>;
 272                 };
 273
 274                 gic: interrupt-controller@c000000 {
 275                         compatible = "arm,gic-v3";
 276                         #interrupt-cells = <4>;
 277                         #redistributor-regions = <1>;
 278                         interrupt-parent = <&gic>;
 279                         interrupt-controller;
 280                         reg = <0 0x0c000000 0 0x40000>,
 281                               <0 0x0c040000 0 0x200000>;
 282                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 283
 284                         ppi-partitions {
 285                                 ppi_cluster0: interrupt-partition-0 {
 286                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 287                                 };
 288                                 ppi_cluster1: interrupt-partition-1 {
 289                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 290                                 };
 291                         };
 292                 };
 293
 294                 topckgen: syscon@10000000 {
 295                         compatible = "mediatek,mt8192-topckgen", "syscon";
 296                         reg = <0 0x10000000 0 0x1000>;
 297                         #clock-cells = <1>;
 298                 };
 299
 300                 infracfg: syscon@10001000 {
 301                         compatible = "mediatek,mt8192-infracfg", "syscon";
 302                         reg = <0 0x10001000 0 0x1000>;
 303                         #clock-cells = <1>;
 304                         #reset-cells = <1>;
 305                 };
 306
 307                 pericfg: syscon@10003000 {
 308                         compatible = "mediatek,mt8192-pericfg", "syscon";
 309                         reg = <0 0x10003000 0 0x1000>;
 310                         #clock-cells = <1>;
 311                 };
 312
 313                 pio: pinctrl@10005000 {
 314                         compatible = "mediatek,mt8192-pinctrl";
 315                         reg = <0 0x10005000 0 0x1000>,
 316                               <0 0x11c20000 0 0x1000>,
 317                               <0 0x11d10000 0 0x1000>,
 318                               <0 0x11d30000 0 0x1000>,
 319                               <0 0x11d40000 0 0x1000>,
 320                               <0 0x11e20000 0 0x1000>,
 321                               <0 0x11e70000 0 0x1000>,
 322                               <0 0x11ea0000 0 0x1000>,
 323                               <0 0x11f20000 0 0x1000>,
 324                               <0 0x11f30000 0 0x1000>,
 325                               <0 0x1000b000 0 0x1000>;
 326                         reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
 327                                     "iocfg_bl", "iocfg_br", "iocfg_lm",
 328                                     "iocfg_lb", "iocfg_rt", "iocfg_lt",
 329                                     "iocfg_tl", "eint";
 330                         gpio-controller;
 331                         #gpio-cells = <2>;
 332                         gpio-ranges = <&pio 0 0 220>;
 333                         interrupt-controller;
 334                         interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
 335                         #interrupt-cells = <2>;
 336                 };
 337
 338                 scpsys: syscon@10006000 {
 339                         compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
 340                         reg = <0 0x10006000 0 0x1000>;
 341
 342                         /* System Power Manager */
 343                         spm: power-controller {
 344                                 compatible = "mediatek,mt8192-power-controller";
 345                                 #address-cells = <1>;
 346                                 #size-cells = <0>;
 347                                 #power-domain-cells = <1>;
 348
 349                                 /* power domain of the SoC */
 350                                 power-domain@MT8192_POWER_DOMAIN_AUDIO {
 351                                         reg = <MT8192_POWER_DOMAIN_AUDIO>;
 352                                         clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 353                                                  <&infracfg CLK_INFRA_AUDIO_26M_B>,
 354                                                  <&infracfg CLK_INFRA_AUDIO>;
 355                                         clock-names = "audio", "audio1", "audio2";
 356                                         mediatek,infracfg = <&infracfg>;
 357                                         #power-domain-cells = <0>;
 358                                 };
 359
 360                                 power-domain@MT8192_POWER_DOMAIN_CONN {
 361                                         reg = <MT8192_POWER_DOMAIN_CONN>;
 362                                         clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
 363                                         clock-names = "conn";
 364                                         mediatek,infracfg = <&infracfg>;
 365                                         #power-domain-cells = <0>;
 366                                 };
 367
 368                                 power-domain@MT8192_POWER_DOMAIN_MFG0 {
 369                                         reg = <MT8192_POWER_DOMAIN_MFG0>;
 370                                         clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
 371                                         clock-names = "mfg";
 372                                         #address-cells = <1>;
 373                                         #size-cells = <0>;
 374                                         #power-domain-cells = <1>;
 375
 376                                         power-domain@MT8192_POWER_DOMAIN_MFG1 {
 377                                                 reg = <MT8192_POWER_DOMAIN_MFG1>;
 378                                                 mediatek,infracfg = <&infracfg>;
 379                                                 #address-cells = <1>;
 380                                                 #size-cells = <0>;
 381                                                 #power-domain-cells = <1>;
 382
 383                                                 power-domain@MT8192_POWER_DOMAIN_MFG2 {
 384                                                         reg = <MT8192_POWER_DOMAIN_MFG2>;
 385                                                         #power-domain-cells = <0>;
 386                                                 };
 387
 388                                                 power-domain@MT8192_POWER_DOMAIN_MFG3 {
 389                                                         reg = <MT8192_POWER_DOMAIN_MFG3>;
 390                                                         #power-domain-cells = <0>;
 391                                                 };
 392
 393                                                 power-domain@MT8192_POWER_DOMAIN_MFG4 {
 394                                                         reg = <MT8192_POWER_DOMAIN_MFG4>;
 395                                                         #power-domain-cells = <0>;
 396                                                 };
 397
 398                                                 power-domain@MT8192_POWER_DOMAIN_MFG5 {
 399                                                         reg = <MT8192_POWER_DOMAIN_MFG5>;
 400                                                         #power-domain-cells = <0>;
 401                                                 };
 402
 403                                                 power-domain@MT8192_POWER_DOMAIN_MFG6 {
 404                                                         reg = <MT8192_POWER_DOMAIN_MFG6>;
 405                                                         #power-domain-cells = <0>;
 406                                                 };
 407                                         };
 408                                 };
 409
 410                                 power-domain@MT8192_POWER_DOMAIN_DISP {
 411                                         reg = <MT8192_POWER_DOMAIN_DISP>;
 412                                         clocks = <&topckgen CLK_TOP_DISP_SEL>,
 413                                                  <&mmsys CLK_MM_SMI_INFRA>,
 414                                                  <&mmsys CLK_MM_SMI_COMMON>,
 415                                                  <&mmsys CLK_MM_SMI_GALS>,
 416                                                  <&mmsys CLK_MM_SMI_IOMMU>;
 417                                         clock-names = "disp", "disp-0", "disp-1", "disp-2",
 418                                                       "disp-3";
 419                                         mediatek,infracfg = <&infracfg>;
 420                                         #address-cells = <1>;
 421                                         #size-cells = <0>;
 422                                         #power-domain-cells = <1>;
 423
 424                                         power-domain@MT8192_POWER_DOMAIN_IPE {
 425                                                 reg = <MT8192_POWER_DOMAIN_IPE>;
 426                                                 clocks = <&topckgen CLK_TOP_IPE_SEL>,
 427                                                          <&ipesys CLK_IPE_LARB19>,
 428                                                          <&ipesys CLK_IPE_LARB20>,
 429                                                          <&ipesys CLK_IPE_SMI_SUBCOM>,
 430                                                          <&ipesys CLK_IPE_GALS>;
 431                                                 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
 432                                                               "ipe-3";
 433                                                 mediatek,infracfg = <&infracfg>;
 434                                                 #power-domain-cells = <0>;
 435                                         };
 436
 437                                         power-domain@MT8192_POWER_DOMAIN_ISP {
 438                                                 reg = <MT8192_POWER_DOMAIN_ISP>;
 439                                                 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
 440                                                          <&imgsys CLK_IMG_LARB9>,
 441                                                          <&imgsys CLK_IMG_GALS>;
 442                                                 clock-names = "isp", "isp-0", "isp-1";
 443                                                 mediatek,infracfg = <&infracfg>;
 444                                                 #power-domain-cells = <0>;
 445                                         };
 446
 447                                         power-domain@MT8192_POWER_DOMAIN_ISP2 {
 448                                                 reg = <MT8192_POWER_DOMAIN_ISP2>;
 449                                                 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
 450                                                          <&imgsys2 CLK_IMG2_LARB11>,
 451                                                          <&imgsys2 CLK_IMG2_GALS>;
 452                                                 clock-names = "isp2", "isp2-0", "isp2-1";
 453                                                 mediatek,infracfg = <&infracfg>;
 454                                                 #power-domain-cells = <0>;
 455                                         };
 456
 457                                         power-domain@MT8192_POWER_DOMAIN_MDP {
 458                                                 reg = <MT8192_POWER_DOMAIN_MDP>;
 459                                                 clocks = <&topckgen CLK_TOP_MDP_SEL>,
 460                                                          <&mdpsys CLK_MDP_SMI0>;
 461                                                 clock-names = "mdp", "mdp-0";
 462                                                 mediatek,infracfg = <&infracfg>;
 463                                                 #power-domain-cells = <0>;
 464                                         };
 465
 466                                         power-domain@MT8192_POWER_DOMAIN_VENC {
 467                                                 reg = <MT8192_POWER_DOMAIN_VENC>;
 468                                                 clocks = <&topckgen CLK_TOP_VENC_SEL>,
 469                                                          <&vencsys CLK_VENC_SET1_VENC>;
 470                                                 clock-names = "venc", "venc-0";
 471                                                 mediatek,infracfg = <&infracfg>;
 472                                                 #power-domain-cells = <0>;
 473                                         };
 474
 475                                         power-domain@MT8192_POWER_DOMAIN_VDEC {
 476                                                 reg = <MT8192_POWER_DOMAIN_VDEC>;
 477                                                 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
 478                                                          <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
 479                                                          <&vdecsys_soc CLK_VDEC_SOC_LAT>,
 480                                                          <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
 481                                                 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
 482                                                 mediatek,infracfg = <&infracfg>;
 483                                                 #address-cells = <1>;
 484                                                 #size-cells = <0>;
 485                                                 #power-domain-cells = <1>;
 486
 487                                                 power-domain@MT8192_POWER_DOMAIN_VDEC2 {
 488                                                         reg = <MT8192_POWER_DOMAIN_VDEC2>;
 489                                                         clocks = <&vdecsys CLK_VDEC_VDEC>,
 490                                                                  <&vdecsys CLK_VDEC_LAT>,
 491                                                                  <&vdecsys CLK_VDEC_LARB1>;
 492                                                         clock-names = "vdec2-0", "vdec2-1",
 493                                                                       "vdec2-2";
 494                                                         #power-domain-cells = <0>;
 495                                                 };
 496                                         };
 497
 498                                         power-domain@MT8192_POWER_DOMAIN_CAM {
 499                                                 reg = <MT8192_POWER_DOMAIN_CAM>;
 500                                                 clocks = <&topckgen CLK_TOP_CAM_SEL>,
 501                                                          <&camsys CLK_CAM_LARB13>,
 502                                                          <&camsys CLK_CAM_LARB14>,
 503                                                          <&camsys CLK_CAM_CCU_GALS>,
 504                                                          <&camsys CLK_CAM_CAM2MM_GALS>;
 505                                                 clock-names = "cam", "cam-0", "cam-1", "cam-2",
 506                                                               "cam-3";
 507                                                 mediatek,infracfg = <&infracfg>;
 508                                                 #address-cells = <1>;
 509                                                 #size-cells = <0>;
 510                                                 #power-domain-cells = <1>;
 511
 512                                                 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
 513                                                         reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
 514                                                         clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
 515                                                         clock-names = "cam_rawa-0";
 516                                                         #power-domain-cells = <0>;
 517                                                 };
 518
 519                                                 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
 520                                                         reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
 521                                                         clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
 522                                                         clock-names = "cam_rawb-0";
 523                                                         #power-domain-cells = <0>;
 524                                                 };
 525
 526                                                 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
 527                                                         reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
 528                                                         clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
 529                                                         clock-names = "cam_rawc-0";
 530                                                         #power-domain-cells = <0>;
 531                                                 };
 532                                         };
 533                                 };
 534                         };
 535                 };
 536
 537                 watchdog: watchdog@10007000 {
 538                         compatible = "mediatek,mt8192-wdt";
 539                         reg = <0 0x10007000 0 0x100>;
 540                         #reset-cells = <1>;
 541                 };
 542
 543                 apmixedsys: syscon@1000c000 {
 544                         compatible = "mediatek,mt8192-apmixedsys", "syscon";
 545                         reg = <0 0x1000c000 0 0x1000>;
 546                         #clock-cells = <1>;
 547                 };
 548
 549                 systimer: timer@10017000 {
 550                         compatible = "mediatek,mt8192-timer",
 551                                      "mediatek,mt6765-timer";
 552                         reg = <0 0x10017000 0 0x1000>;
 553                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
 554                         clocks = <&clk13m>;
 555                 };
 556
 557                 pwrap: pwrap@10026000 {
 558                         compatible = "mediatek,mt6873-pwrap";
 559                         reg = <0 0x10026000 0 0x1000>;
 560                         reg-names = "pwrap";
 561                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
 562                         clocks = <&infracfg CLK_INFRA_PMIC_AP>,
 563                                  <&infracfg CLK_INFRA_PMIC_TMR>;
 564                         clock-names = "spi", "wrap";
 565                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
 566                         assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 567                 };
 568
 569                 spmi: spmi@10027000 {
 570                         compatible = "mediatek,mt6873-spmi";
 571                         reg = <0 0x10027000 0 0x000e00>,
 572                               <0 0x10029000 0 0x000100>;
 573                         reg-names = "pmif", "spmimst";
 574                         clocks = <&infracfg CLK_INFRA_PMIC_AP>,
 575                                  <&infracfg CLK_INFRA_PMIC_TMR>,
 576                                  <&topckgen CLK_TOP_SPMI_MST_SEL>;
 577                         clock-names = "pmif_sys_ck",
 578                                       "pmif_tmr_ck",
 579                                       "spmimst_clk_mux";
 580                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
 581                         assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
 582                 };
 583
 584                 gce: mailbox@10228000 {
 585                         compatible = "mediatek,mt8192-gce";
 586                         reg = <0 0x10228000 0 0x4000>;
 587                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
 588                         #mbox-cells = <2>;
 589                         clocks = <&infracfg CLK_INFRA_GCE>;
 590                         clock-names = "gce";
 591                 };
 592
 593                 scp_adsp: clock-controller@10720000 {
 594                         compatible = "mediatek,mt8192-scp_adsp";
 595                         reg = <0 0x10720000 0 0x1000>;
 596                         #clock-cells = <1>;
 597                         /* power domain dependency not upstreamed */
 598                         status = "fail";
 599                 };
 600
 601                 uart0: serial@11002000 {
 602                         compatible = "mediatek,mt8192-uart",
 603                                      "mediatek,mt6577-uart";
 604                         reg = <0 0x11002000 0 0x1000>;
 605                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
 606                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 607                         clock-names = "baud", "bus";
 608                         status = "disabled";
 609                 };
 610
 611                 uart1: serial@11003000 {
 612                         compatible = "mediatek,mt8192-uart",
 613                                      "mediatek,mt6577-uart";
 614                         reg = <0 0x11003000 0 0x1000>;
 615                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 616                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 617                         clock-names = "baud", "bus";
 618                         status = "disabled";
 619                 };
 620
 621                 imp_iic_wrap_c: clock-controller@11007000 {
 622                         compatible = "mediatek,mt8192-imp_iic_wrap_c";
 623                         reg = <0 0x11007000 0 0x1000>;
 624                         #clock-cells = <1>;
 625                 };
 626
 627                 spi0: spi@1100a000 {
 628                         compatible = "mediatek,mt8192-spi",
 629                                      "mediatek,mt6765-spi";
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                         reg = <0 0x1100a000 0 0x1000>;
 633                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
 634                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 635                                  <&topckgen CLK_TOP_SPI_SEL>,
 636                                  <&infracfg CLK_INFRA_SPI0>;
 637                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 638                         status = "disabled";
 639                 };
 640
 641                 pwm0: pwm@1100e000 {
 642                         compatible = "mediatek,mt8183-disp-pwm";
 643                         reg = <0 0x1100e000 0 0x1000>;
 644                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
 645                         #pwm-cells = <2>;
 646                         clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
 647                                  <&infracfg CLK_INFRA_DISP_PWM>;
 648                         clock-names = "main", "mm";
 649                         status = "disabled";
 650                 };
 651
 652                 spi1: spi@11010000 {
 653                         compatible = "mediatek,mt8192-spi",
 654                                      "mediatek,mt6765-spi";
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         reg = <0 0x11010000 0 0x1000>;
 658                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
 659                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 660                                  <&topckgen CLK_TOP_SPI_SEL>,
 661                                  <&infracfg CLK_INFRA_SPI1>;
 662                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 663                         status = "disabled";
 664                 };
 665
 666                 spi2: spi@11012000 {
 667                         compatible = "mediatek,mt8192-spi",
 668                                      "mediatek,mt6765-spi";
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         reg = <0 0x11012000 0 0x1000>;
 672                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
 673                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 674                                  <&topckgen CLK_TOP_SPI_SEL>,
 675                                  <&infracfg CLK_INFRA_SPI2>;
 676                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 677                         status = "disabled";
 678                 };
 679
 680                 spi3: spi@11013000 {
 681                         compatible = "mediatek,mt8192-spi",
 682                                      "mediatek,mt6765-spi";
 683                         #address-cells = <1>;
 684                         #size-cells = <0>;
 685                         reg = <0 0x11013000 0 0x1000>;
 686                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
 687                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 688                                  <&topckgen CLK_TOP_SPI_SEL>,
 689                                  <&infracfg CLK_INFRA_SPI3>;
 690                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 691                         status = "disabled";
 692                 };
 693
 694                 spi4: spi@11018000 {
 695                         compatible = "mediatek,mt8192-spi",
 696                                      "mediatek,mt6765-spi";
 697                         #address-cells = <1>;
 698                         #size-cells = <0>;
 699                         reg = <0 0x11018000 0 0x1000>;
 700                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
 701                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 702                                  <&topckgen CLK_TOP_SPI_SEL>,
 703                                  <&infracfg CLK_INFRA_SPI4>;
 704                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 705                         status = "disabled";
 706                 };
 707
 708                 spi5: spi@11019000 {
 709                         compatible = "mediatek,mt8192-spi",
 710                                      "mediatek,mt6765-spi";
 711                         #address-cells = <1>;
 712                         #size-cells = <0>;
 713                         reg = <0 0x11019000 0 0x1000>;
 714                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
 715                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 716                                  <&topckgen CLK_TOP_SPI_SEL>,
 717                                  <&infracfg CLK_INFRA_SPI5>;
 718                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 719                         status = "disabled";
 720                 };
 721
 722                 spi6: spi@1101d000 {
 723                         compatible = "mediatek,mt8192-spi",
 724                                      "mediatek,mt6765-spi";
 725                         #address-cells = <1>;
 726                         #size-cells = <0>;
 727                         reg = <0 0x1101d000 0 0x1000>;
 728                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
 729                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 730                                  <&topckgen CLK_TOP_SPI_SEL>,
 731                                  <&infracfg CLK_INFRA_SPI6>;
 732                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 733                         status = "disabled";
 734                 };
 735
 736                 spi7: spi@1101e000 {
 737                         compatible = "mediatek,mt8192-spi",
 738                                      "mediatek,mt6765-spi";
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                         reg = <0 0x1101e000 0 0x1000>;
 742                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
 743                         clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
 744                                  <&topckgen CLK_TOP_SPI_SEL>,
 745                                  <&infracfg CLK_INFRA_SPI7>;
 746                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 747                         status = "disabled";
 748                 };
 749
 750                 scp: scp@10500000 {
 751                         compatible = "mediatek,mt8192-scp";
 752                         reg = <0 0x10500000 0 0x100000>,
 753                               <0 0x10720000 0 0xe0000>,
 754                               <0 0x10700000 0 0x8000>;
 755                         reg-names = "sram", "cfg", "l1tcm";
 756                         interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>;
 757                         clocks = <&infracfg CLK_INFRA_SCPSYS>;
 758                         clock-names = "main";
 759                         status = "disabled";
 760                 };
 761
 762                 xhci: usb@11200000 {
 763                         compatible = "mediatek,mt8192-xhci",
 764                                      "mediatek,mtk-xhci";
 765                         reg = <0 0x11200000 0 0x1000>,
 766                               <0 0x11203e00 0 0x0100>;
 767                         reg-names = "mac", "ippc";
 768                         interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 769                         interrupt-names = "host";
 770                         phys = <&u2port0 PHY_TYPE_USB2>,
 771                                <&u3port0 PHY_TYPE_USB3>;
 772                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
 773                                           <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
 774                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
 775                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 776                         clocks = <&infracfg CLK_INFRA_SSUSB>,
 777                                  <&apmixedsys CLK_APMIXED_USBPLL>,
 778                                  <&clk26m>,
 779                                  <&clk26m>,
 780                                  <&infracfg CLK_INFRA_SSUSB_XHCI>;
 781                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
 782                                       "xhci_ck";
 783                         wakeup-source;
 784                         mediatek,syscon-wakeup = <&pericfg 0x420 102>;
 785                         status = "disabled";
 786                 };
 787
 788                 audsys: syscon@11210000 {
 789                         compatible = "mediatek,mt8192-audsys", "syscon";
 790                         reg = <0 0x11210000 0 0x2000>;
 791                         #clock-cells = <1>;
 792
 793                         afe: mt8192-afe-pcm {
 794                                 compatible = "mediatek,mt8192-audio";
 795                                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
 796                                 resets = <&watchdog 17>;
 797                                 reset-names = "audiosys";
 798                                 mediatek,apmixedsys = <&apmixedsys>;
 799                                 mediatek,infracfg = <&infracfg>;
 800                                 mediatek,topckgen = <&topckgen>;
 801                                 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>;
 802                                 clocks = <&audsys CLK_AUD_AFE>,
 803                                          <&audsys CLK_AUD_DAC>,
 804                                          <&audsys CLK_AUD_DAC_PREDIS>,
 805                                          <&audsys CLK_AUD_ADC>,
 806                                          <&audsys CLK_AUD_ADDA6_ADC>,
 807                                          <&audsys CLK_AUD_22M>,
 808                                          <&audsys CLK_AUD_24M>,
 809                                          <&audsys CLK_AUD_APLL_TUNER>,
 810                                          <&audsys CLK_AUD_APLL2_TUNER>,
 811                                          <&audsys CLK_AUD_TDM>,
 812                                          <&audsys CLK_AUD_TML>,
 813                                          <&audsys CLK_AUD_NLE>,
 814                                          <&audsys CLK_AUD_DAC_HIRES>,
 815                                          <&audsys CLK_AUD_ADC_HIRES>,
 816                                          <&audsys CLK_AUD_ADC_HIRES_TML>,
 817                                          <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
 818                                          <&audsys CLK_AUD_3RD_DAC>,
 819                                          <&audsys CLK_AUD_3RD_DAC_PREDIS>,
 820                                          <&audsys CLK_AUD_3RD_DAC_TML>,
 821                                          <&audsys CLK_AUD_3RD_DAC_HIRES>,
 822                                          <&infracfg CLK_INFRA_AUDIO>,
 823                                          <&infracfg CLK_INFRA_AUDIO_26M_B>,
 824                                          <&topckgen CLK_TOP_AUDIO_SEL>,
 825                                          <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 826                                          <&topckgen CLK_TOP_MAINPLL_D4_D4>,
 827                                          <&topckgen CLK_TOP_AUD_1_SEL>,
 828                                          <&topckgen CLK_TOP_APLL1>,
 829                                          <&topckgen CLK_TOP_AUD_2_SEL>,
 830                                          <&topckgen CLK_TOP_APLL2>,
 831                                          <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
 832                                          <&topckgen CLK_TOP_APLL1_D4>,
 833                                          <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
 834                                          <&topckgen CLK_TOP_APLL2_D4>,
 835                                          <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
 836                                          <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
 837                                          <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
 838                                          <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
 839                                          <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
 840                                          <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
 841                                          <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
 842                                          <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
 843                                          <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
 844                                          <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
 845                                          <&topckgen CLK_TOP_APLL12_DIV0>,
 846                                          <&topckgen CLK_TOP_APLL12_DIV1>,
 847                                          <&topckgen CLK_TOP_APLL12_DIV2>,
 848                                          <&topckgen CLK_TOP_APLL12_DIV3>,
 849                                          <&topckgen CLK_TOP_APLL12_DIV4>,
 850                                          <&topckgen CLK_TOP_APLL12_DIVB>,
 851                                          <&topckgen CLK_TOP_APLL12_DIV5>,
 852                                          <&topckgen CLK_TOP_APLL12_DIV6>,
 853                                          <&topckgen CLK_TOP_APLL12_DIV7>,
 854                                          <&topckgen CLK_TOP_APLL12_DIV8>,
 855                                          <&topckgen CLK_TOP_APLL12_DIV9>,
 856                                          <&topckgen CLK_TOP_AUDIO_H_SEL>,
 857                                          <&clk26m>;
 858                                 clock-names = "aud_afe_clk",
 859                                               "aud_dac_clk",
 860                                               "aud_dac_predis_clk",
 861                                               "aud_adc_clk",
 862                                               "aud_adda6_adc_clk",
 863                                               "aud_apll22m_clk",
 864                                               "aud_apll24m_clk",
 865                                               "aud_apll1_tuner_clk",
 866                                               "aud_apll2_tuner_clk",
 867                                               "aud_tdm_clk",
 868                                               "aud_tml_clk",
 869                                               "aud_nle",
 870                                               "aud_dac_hires_clk",
 871                                               "aud_adc_hires_clk",
 872                                               "aud_adc_hires_tml",
 873                                               "aud_adda6_adc_hires_clk",
 874                                               "aud_3rd_dac_clk",
 875                                               "aud_3rd_dac_predis_clk",
 876                                               "aud_3rd_dac_tml",
 877                                               "aud_3rd_dac_hires_clk",
 878                                               "aud_infra_clk",
 879                                               "aud_infra_26m_clk",
 880                                               "top_mux_audio",
 881                                               "top_mux_audio_int",
 882                                               "top_mainpll_d4_d4",
 883                                               "top_mux_aud_1",
 884                                               "top_apll1_ck",
 885                                               "top_mux_aud_2",
 886                                               "top_apll2_ck",
 887                                               "top_mux_aud_eng1",
 888                                               "top_apll1_d4",
 889                                               "top_mux_aud_eng2",
 890                                               "top_apll2_d4",
 891                                               "top_i2s0_m_sel",
 892                                               "top_i2s1_m_sel",
 893                                               "top_i2s2_m_sel",
 894                                               "top_i2s3_m_sel",
 895                                               "top_i2s4_m_sel",
 896                                               "top_i2s5_m_sel",
 897                                               "top_i2s6_m_sel",
 898                                               "top_i2s7_m_sel",
 899                                               "top_i2s8_m_sel",
 900                                               "top_i2s9_m_sel",
 901                                               "top_apll12_div0",
 902                                               "top_apll12_div1",
 903                                               "top_apll12_div2",
 904                                               "top_apll12_div3",
 905                                               "top_apll12_div4",
 906                                               "top_apll12_divb",
 907                                               "top_apll12_div5",
 908                                               "top_apll12_div6",
 909                                               "top_apll12_div7",
 910                                               "top_apll12_div8",
 911                                               "top_apll12_div9",
 912                                               "top_mux_audio_h",
 913                                               "top_clk26m_clk";
 914                         };
 915                 };
 916
 917                 pcie: pcie@11230000 {
 918                         compatible = "mediatek,mt8192-pcie";
 919                         device_type = "pci";
 920                         reg = <0 0x11230000 0 0x2000>;
 921                         reg-names = "pcie-mac";
 922                         #address-cells = <3>;
 923                         #size-cells = <2>;
 924                         clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>,
 925                                  <&infracfg CLK_INFRA_PCIE_TL_26M>,
 926                                  <&infracfg CLK_INFRA_PCIE_TL_96M>,
 927                                  <&infracfg CLK_INFRA_PCIE_TL_32K>,
 928                                  <&infracfg CLK_INFRA_PCIE_PERI_26M>,
 929                                  <&infracfg CLK_INFRA_PCIE_TOP_H_133M>;
 930                         clock-names = "pl_250m", "tl_26m", "tl_96m",
 931                                       "tl_32k", "peri_26m", "top_133m";
 932                         assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
 933                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
 934                         interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
 935                         bus-range = <0x00 0xff>;
 936                         ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>,
 937                                  <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>;
 938                         #interrupt-cells = <1>;
 939                         interrupt-map-mask = <0 0 0 7>;
 940                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 941                                         <0 0 0 2 &pcie_intc0 1>,
 942                                         <0 0 0 3 &pcie_intc0 2>,
 943                                         <0 0 0 4 &pcie_intc0 3>;
 944
 945                         pcie_intc0: interrupt-controller {
 946                                 interrupt-controller;
 947                                 #address-cells = <0>;
 948                                 #interrupt-cells = <1>;
 949                         };
 950                 };
 951
 952                 nor_flash: spi@11234000 {
 953                         compatible = "mediatek,mt8192-nor";
 954                         reg = <0 0x11234000 0 0xe0>;
 955                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
 956                         clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
 957                                  <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
 958                                  <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
 959                         clock-names = "spi", "sf", "axi";
 960                         assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
 961                         assigned-clock-parents = <&clk26m>;
 962                         #address-cells = <1>;
 963                         #size-cells = <0>;
 964                         status = "disabled";
 965                 };
 966
 967                 efuse: efuse@11c10000 {
 968                         compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
 969                         reg = <0 0x11c10000 0 0x1000>;
 970                         #address-cells = <1>;
 971                         #size-cells = <1>;
 972
 973                         lvts_e_data1: data1@1c0 {
 974                                 reg = <0x1c0 0x58>;
 975                         };
 976
 977                         svs_calibration: calib@580 {
 978                                 reg = <0x580 0x68>;
 979                         };
 980                 };
 981
 982                 i2c3: i2c@11cb0000 {
 983                         compatible = "mediatek,mt8192-i2c";
 984                         reg = <0 0x11cb0000 0 0x1000>,
 985                               <0 0x10217300 0 0x80>;
 986                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 987                         clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
 988                                  <&infracfg CLK_INFRA_AP_DMA>;
 989                         clock-names = "main", "dma";
 990                         clock-div = <1>;
 991                         #address-cells = <1>;
 992                         #size-cells = <0>;
 993                         status = "disabled";
 994                 };
 995
 996                 imp_iic_wrap_e: clock-controller@11cb1000 {
 997                         compatible = "mediatek,mt8192-imp_iic_wrap_e";
 998                         reg = <0 0x11cb1000 0 0x1000>;
 999                         #clock-cells = <1>;
1000                 };
1001
1002                 i2c7: i2c@11d00000 {
1003                         compatible = "mediatek,mt8192-i2c";
1004                         reg = <0 0x11d00000 0 0x1000>,
1005                               <0 0x10217600 0 0x180>;
1006                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1007                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1008                                  <&infracfg CLK_INFRA_AP_DMA>;
1009                         clock-names = "main", "dma";
1010                         clock-div = <1>;
1011                         #address-cells = <1>;
1012                         #size-cells = <0>;
1013                         status = "disabled";
1014                 };
1015
1016                 i2c8: i2c@11d01000 {
1017                         compatible = "mediatek,mt8192-i2c";
1018                         reg = <0 0x11d01000 0 0x1000>,
1019                               <0 0x10217780 0 0x180>;
1020                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1021                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
1022                                  <&infracfg CLK_INFRA_AP_DMA>;
1023                         clock-names = "main", "dma";
1024                         clock-div = <1>;
1025                         #address-cells = <1>;
1026                         #size-cells = <0>;
1027                         status = "disabled";
1028                 };
1029
1030                 i2c9: i2c@11d02000 {
1031                         compatible = "mediatek,mt8192-i2c";
1032                         reg = <0 0x11d02000 0 0x1000>,
1033                               <0 0x10217900 0 0x180>;
1034                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1035                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
1036                                  <&infracfg CLK_INFRA_AP_DMA>;
1037                         clock-names = "main", "dma";
1038                         clock-div = <1>;
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                         status = "disabled";
1042                 };
1043
1044                 imp_iic_wrap_s: clock-controller@11d03000 {
1045                         compatible = "mediatek,mt8192-imp_iic_wrap_s";
1046                         reg = <0 0x11d03000 0 0x1000>;
1047                         #clock-cells = <1>;
1048                 };
1049
1050                 i2c1: i2c@11d20000 {
1051                         compatible = "mediatek,mt8192-i2c";
1052                         reg = <0 0x11d20000 0 0x1000>,
1053                               <0 0x10217100 0 0x80>;
1054                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1055                         clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
1056                                  <&infracfg CLK_INFRA_AP_DMA>;
1057                         clock-names = "main", "dma";
1058                         clock-div = <1>;
1059                         #address-cells = <1>;
1060                         #size-cells = <0>;
1061                         status = "disabled";
1062                 };
1063
1064                 i2c2: i2c@11d21000 {
1065                         compatible = "mediatek,mt8192-i2c";
1066                         reg = <0 0x11d21000 0 0x1000>,
1067                               <0 0x10217180 0 0x180>;
1068                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1069                         clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
1070                                  <&infracfg CLK_INFRA_AP_DMA>;
1071                         clock-names = "main", "dma";
1072                         clock-div = <1>;
1073                         #address-cells = <1>;
1074                         #size-cells = <0>;
1075                         status = "disabled";
1076                 };
1077
1078                 i2c4: i2c@11d22000 {
1079                         compatible = "mediatek,mt8192-i2c";
1080                         reg = <0 0x11d22000 0 0x1000>,
1081                               <0 0x10217380 0 0x180>;
1082                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1083                         clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
1084                                  <&infracfg CLK_INFRA_AP_DMA>;
1085                         clock-names = "main", "dma";
1086                         clock-div = <1>;
1087                         #address-cells = <1>;
1088                         #size-cells = <0>;
1089                         status = "disabled";
1090                 };
1091
1092                 imp_iic_wrap_ws: clock-controller@11d23000 {
1093                         compatible = "mediatek,mt8192-imp_iic_wrap_ws";
1094                         reg = <0 0x11d23000 0 0x1000>;
1095                         #clock-cells = <1>;
1096                 };
1097
1098                 i2c5: i2c@11e00000 {
1099                         compatible = "mediatek,mt8192-i2c";
1100                         reg = <0 0x11e00000 0 0x1000>,
1101                               <0 0x10217500 0 0x80>;
1102                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1103                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
1104                                  <&infracfg CLK_INFRA_AP_DMA>;
1105                         clock-names = "main", "dma";
1106                         clock-div = <1>;
1107                         #address-cells = <1>;
1108                         #size-cells = <0>;
1109                         status = "disabled";
1110                 };
1111
1112                 imp_iic_wrap_w: clock-controller@11e01000 {
1113                         compatible = "mediatek,mt8192-imp_iic_wrap_w";
1114                         reg = <0 0x11e01000 0 0x1000>;
1115                         #clock-cells = <1>;
1116                 };
1117
1118                 u3phy0: t-phy@11e40000 {
1119                         compatible = "mediatek,mt8192-tphy",
1120                                      "mediatek,generic-tphy-v2";
1121                         #address-cells = <1>;
1122                         #size-cells = <1>;
1123                         ranges = <0x0 0x0 0x11e40000 0x1000>;
1124
1125                         u2port0: usb-phy@0 {
1126                                 reg = <0x0 0x700>;
1127                                 clocks = <&clk26m>;
1128                                 clock-names = "ref";
1129                                 #phy-cells = <1>;
1130                         };
1131
1132                         u3port0: usb-phy@700 {
1133                                 reg = <0x700 0x900>;
1134                                 clocks = <&clk26m>;
1135                                 clock-names = "ref";
1136                                 #phy-cells = <1>;
1137                         };
1138                 };
1139
1140                 mipi_tx0: dsi-phy@11e50000 {
1141                         compatible = "mediatek,mt8183-mipi-tx";
1142                         reg = <0 0x11e50000 0 0x1000>;
1143                         clocks = <&apmixedsys CLK_APMIXED_MIPID26M>;
1144                         #clock-cells = <0>;
1145                         #phy-cells = <0>;
1146                         clock-output-names = "mipi_tx0_pll";
1147                         status = "disabled";
1148                 };
1149
1150                 i2c0: i2c@11f00000 {
1151                         compatible = "mediatek,mt8192-i2c";
1152                         reg = <0 0x11f00000 0 0x1000>,
1153                               <0 0x10217080 0 0x80>;
1154                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1155                         clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
1156                                  <&infracfg CLK_INFRA_AP_DMA>;
1157                         clock-names = "main", "dma";
1158                         clock-div = <1>;
1159                         #address-cells = <1>;
1160                         #size-cells = <0>;
1161                         status = "disabled";
1162                 };
1163
1164                 i2c6: i2c@11f01000 {
1165                         compatible = "mediatek,mt8192-i2c";
1166                         reg = <0 0x11f01000 0 0x1000>,
1167                               <0 0x10217580 0 0x80>;
1168                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1169                         clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
1170                                  <&infracfg CLK_INFRA_AP_DMA>;
1171                         clock-names = "main", "dma";
1172                         clock-div = <1>;
1173                         #address-cells = <1>;
1174                         #size-cells = <0>;
1175                         status = "disabled";
1176                 };
1177
1178                 imp_iic_wrap_n: clock-controller@11f02000 {
1179                         compatible = "mediatek,mt8192-imp_iic_wrap_n";
1180                         reg = <0 0x11f02000 0 0x1000>;
1181                         #clock-cells = <1>;
1182                 };
1183
1184                 msdc_top: clock-controller@11f10000 {
1185                         compatible = "mediatek,mt8192-msdc_top";
1186                         reg = <0 0x11f10000 0 0x1000>;
1187                         #clock-cells = <1>;
1188                 };
1189
1190                 mmc0: mmc@11f60000 {
1191                         compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1192                         reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
1193                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
1194                         clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1195                                  <&msdc_top CLK_MSDC_TOP_H_MST_0P>,
1196                                  <&msdc_top CLK_MSDC_TOP_SRC_0P>,
1197                                  <&msdc_top CLK_MSDC_TOP_P_CFG>,
1198                                  <&msdc_top CLK_MSDC_TOP_P_MSDC0>,
1199                                  <&msdc_top CLK_MSDC_TOP_AXI>,
1200                                  <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1201                         clock-names = "source", "hclk", "source_cg", "sys_cg",
1202                                       "pclk_cg", "axi_cg", "ahb_cg";
1203                         status = "disabled";
1204                 };
1205
1206                 mmc1: mmc@11f70000 {
1207                         compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
1208                         reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
1209                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
1210                         clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1211                                  <&msdc_top CLK_MSDC_TOP_H_MST_1P>,
1212                                  <&msdc_top CLK_MSDC_TOP_SRC_1P>,
1213                                  <&msdc_top CLK_MSDC_TOP_P_CFG>,
1214                                  <&msdc_top CLK_MSDC_TOP_P_MSDC1>,
1215                                  <&msdc_top CLK_MSDC_TOP_AXI>,
1216                                  <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
1217                         clock-names = "source", "hclk", "source_cg", "sys_cg",
1218                                       "pclk_cg", "axi_cg", "ahb_cg";
1219                         status = "disabled";
1220                 };
1221
1222                 mfgcfg: clock-controller@13fbf000 {
1223                         compatible = "mediatek,mt8192-mfgcfg";
1224                         reg = <0 0x13fbf000 0 0x1000>;
1225                         #clock-cells = <1>;
1226                 };
1227
1228                 mmsys: syscon@14000000 {
1229                         compatible = "mediatek,mt8192-mmsys", "syscon";
1230                         reg = <0 0x14000000 0 0x1000>;
1231                         #clock-cells = <1>;
1232                         #reset-cells = <1>;
1233                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1234                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1235                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1236                 };
1237
1238                 mutex: mutex@14001000 {
1239                         compatible = "mediatek,mt8192-disp-mutex";
1240                         reg = <0 0x14001000 0 0x1000>;
1241                         interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
1242                         clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1243                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
1244                         mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1245                                               <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1246                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1247                 };
1248
1249                 smi_common: smi@14002000 {
1250                         compatible = "mediatek,mt8192-smi-common";
1251                         reg = <0 0x14002000 0 0x1000>;
1252                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1253                                  <&mmsys CLK_MM_SMI_INFRA>,
1254                                  <&mmsys CLK_MM_SMI_GALS>,
1255                                  <&mmsys CLK_MM_SMI_GALS>;
1256                         clock-names = "apb", "smi", "gals0", "gals1";
1257                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1258                 };
1259
1260                 larb0: larb@14003000 {
1261                         compatible = "mediatek,mt8192-smi-larb";
1262                         reg = <0 0x14003000 0 0x1000>;
1263                         mediatek,larb-id = <0>;
1264                         mediatek,smi = <&smi_common>;
1265                         clocks = <&clk26m>, <&clk26m>;
1266                         clock-names = "apb", "smi";
1267                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1268                 };
1269
1270                 larb1: larb@14004000 {
1271                         compatible = "mediatek,mt8192-smi-larb";
1272                         reg = <0 0x14004000 0 0x1000>;
1273                         mediatek,larb-id = <1>;
1274                         mediatek,smi = <&smi_common>;
1275                         clocks = <&clk26m>, <&clk26m>;
1276                         clock-names = "apb", "smi";
1277                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1278                 };
1279
1280                 ovl0: ovl@14005000 {
1281                         compatible = "mediatek,mt8192-disp-ovl";
1282                         reg = <0 0x14005000 0 0x1000>;
1283                         interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
1284                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1285                         iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
1286                                  <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
1287                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1288                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1289                 };
1290
1291                 ovl_2l0: ovl@14006000 {
1292                         compatible = "mediatek,mt8192-disp-ovl-2l";
1293                         reg = <0 0x14006000 0 0x1000>;
1294                         interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
1295                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1296                         clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1297                         iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
1298                                  <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
1299                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1300                 };
1301
1302                 rdma0: rdma@14007000 {
1303                         compatible = "mediatek,mt8192-disp-rdma",
1304                                      "mediatek,mt8183-disp-rdma";
1305                         reg = <0 0x14007000 0 0x1000>;
1306                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
1307                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1308                         iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
1309                         mediatek,rdma-fifo-size = <5120>;
1310                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1311                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1312                 };
1313
1314                 color0: color@14009000 {
1315                         compatible = "mediatek,mt8192-disp-color",
1316                                      "mediatek,mt8173-disp-color";
1317                         reg = <0 0x14009000 0 0x1000>;
1318                         interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
1319                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1320                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1321                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1322                 };
1323
1324                 ccorr0: ccorr@1400a000 {
1325                         compatible = "mediatek,mt8192-disp-ccorr";
1326                         reg = <0 0x1400a000 0 0x1000>;
1327                         interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
1328                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1329                         clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1330                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1331                 };
1332
1333                 aal0: aal@1400b000 {
1334                         compatible = "mediatek,mt8192-disp-aal",
1335                                      "mediatek,mt8183-disp-aal";
1336                         reg = <0 0x1400b000 0 0x1000>;
1337                         interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
1338                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1339                         clocks = <&mmsys CLK_MM_DISP_AAL0>;
1340                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1341                 };
1342
1343                 gamma0: gamma@1400c000 {
1344                         compatible = "mediatek,mt8192-disp-gamma",
1345                                      "mediatek,mt8183-disp-gamma";
1346                         reg = <0 0x1400c000 0 0x1000>;
1347                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
1348                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1349                         clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1350                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1351                 };
1352
1353                 postmask0: postmask@1400d000 {
1354                         compatible = "mediatek,mt8192-disp-postmask";
1355                         reg = <0 0x1400d000 0 0x1000>;
1356                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
1357                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1358                         clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1359                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1360                 };
1361
1362                 dither0: dither@1400e000 {
1363                         compatible = "mediatek,mt8192-disp-dither",
1364                                      "mediatek,mt8183-disp-dither";
1365                         reg = <0 0x1400e000 0 0x1000>;
1366                         interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
1367                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1368                         clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1369                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1370                 };
1371
1372                 dsi0: dsi@14010000 {
1373                         compatible = "mediatek,mt8183-dsi";
1374                         reg = <0 0x14010000 0 0x1000>;
1375                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
1376                         clocks = <&mmsys CLK_MM_DSI0>,
1377                                  <&mmsys CLK_MM_DSI_DSI0>,
1378                                  <&mipi_tx0>;
1379                         clock-names = "engine", "digital", "hs";
1380                         phys = <&mipi_tx0>;
1381                         phy-names = "dphy";
1382                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1383                         resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
1384                         status = "disabled";
1385
1386                         port {
1387                                 dsi_out: endpoint { };
1388                         };
1389                 };
1390
1391                 ovl_2l2: ovl@14014000 {
1392                         compatible = "mediatek,mt8192-disp-ovl-2l";
1393                         reg = <0 0x14014000 0 0x1000>;
1394                         interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
1395                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1396                         clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
1397                         iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
1398                                  <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
1399                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1400                 };
1401
1402                 rdma4: rdma@14015000 {
1403                         compatible = "mediatek,mt8192-disp-rdma",
1404                                      "mediatek,mt8183-disp-rdma";
1405                         reg = <0 0x14015000 0 0x1000>;
1406                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
1407                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1408                         clocks = <&mmsys CLK_MM_DISP_RDMA4>;
1409                         iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
1410                         mediatek,rdma-fifo-size = <2048>;
1411                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1412                 };
1413
1414                 dpi0: dpi@14016000 {
1415                         compatible = "mediatek,mt8192-dpi";
1416                         reg = <0 0x14016000 0 0x1000>;
1417                         interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
1418                         clocks = <&mmsys CLK_MM_DPI_DPI0>,
1419                                  <&mmsys CLK_MM_DISP_DPI0>,
1420                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1421                         clock-names = "pixel", "engine", "pll";
1422                         status = "disabled";
1423                 };
1424
1425                 iommu0: m4u@1401d000 {
1426                         compatible = "mediatek,mt8192-m4u";
1427                         reg = <0 0x1401d000 0 0x1000>;
1428                         mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
1429                                          <&larb4>, <&larb5>, <&larb7>,
1430                                          <&larb9>, <&larb11>, <&larb13>,
1431                                          <&larb14>, <&larb16>, <&larb17>,
1432                                          <&larb18>, <&larb19>, <&larb20>;
1433                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1434                         clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1435                         clock-names = "bclk";
1436                         power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
1437                         #iommu-cells = <1>;
1438                 };
1439
1440                 imgsys: clock-controller@15020000 {
1441                         compatible = "mediatek,mt8192-imgsys";
1442                         reg = <0 0x15020000 0 0x1000>;
1443                         #clock-cells = <1>;
1444                 };
1445
1446                 larb9: larb@1502e000 {
1447                         compatible = "mediatek,mt8192-smi-larb";
1448                         reg = <0 0x1502e000 0 0x1000>;
1449                         mediatek,larb-id = <9>;
1450                         mediatek,smi = <&smi_common>;
1451                         clocks = <&imgsys CLK_IMG_LARB9>,
1452                                  <&imgsys CLK_IMG_LARB9>;
1453                         clock-names = "apb", "smi";
1454                         power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
1455                 };
1456
1457                 imgsys2: clock-controller@15820000 {
1458                         compatible = "mediatek,mt8192-imgsys2";
1459                         reg = <0 0x15820000 0 0x1000>;
1460                         #clock-cells = <1>;
1461                 };
1462
1463                 larb11: larb@1582e000 {
1464                         compatible = "mediatek,mt8192-smi-larb";
1465                         reg = <0 0x1582e000 0 0x1000>;
1466                         mediatek,larb-id = <11>;
1467                         mediatek,smi = <&smi_common>;
1468                         clocks = <&imgsys2 CLK_IMG2_LARB11>,
1469                                  <&imgsys2 CLK_IMG2_LARB11>;
1470                         clock-names = "apb", "smi";
1471                         power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
1472                 };
1473
1474                 larb5: larb@1600d000 {
1475                         compatible = "mediatek,mt8192-smi-larb";
1476                         reg = <0 0x1600d000 0 0x1000>;
1477                         mediatek,larb-id = <5>;
1478                         mediatek,smi = <&smi_common>;
1479                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
1480                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
1481                         clock-names = "apb", "smi";
1482                         power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
1483                 };
1484
1485                 vdecsys_soc: clock-controller@1600f000 {
1486                         compatible = "mediatek,mt8192-vdecsys_soc";
1487                         reg = <0 0x1600f000 0 0x1000>;
1488                         #clock-cells = <1>;
1489                 };
1490
1491                 larb4: larb@1602e000 {
1492                         compatible = "mediatek,mt8192-smi-larb";
1493                         reg = <0 0x1602e000 0 0x1000>;
1494                         mediatek,larb-id = <4>;
1495                         mediatek,smi = <&smi_common>;
1496                         clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
1497                                  <&vdecsys CLK_VDEC_SOC_LARB1>;
1498                         clock-names = "apb", "smi";
1499                         power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
1500                 };
1501
1502                 vdecsys: clock-controller@1602f000 {
1503                         compatible = "mediatek,mt8192-vdecsys";
1504                         reg = <0 0x1602f000 0 0x1000>;
1505                         #clock-cells = <1>;
1506                 };
1507
1508                 vencsys: clock-controller@17000000 {
1509                         compatible = "mediatek,mt8192-vencsys";
1510                         reg = <0 0x17000000 0 0x1000>;
1511                         #clock-cells = <1>;
1512                 };
1513
1514                 larb7: larb@17010000 {
1515                         compatible = "mediatek,mt8192-smi-larb";
1516                         reg = <0 0x17010000 0 0x1000>;
1517                         mediatek,larb-id = <7>;
1518                         mediatek,smi = <&smi_common>;
1519                         clocks = <&vencsys CLK_VENC_SET0_LARB>,
1520                                  <&vencsys CLK_VENC_SET1_VENC>;
1521                         clock-names = "apb", "smi";
1522                         power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1523                 };
1524
1525                 vcodec_enc: vcodec@17020000 {
1526                         compatible = "mediatek,mt8192-vcodec-enc";
1527                         reg = <0 0x17020000 0 0x2000>;
1528                         iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1529                                  <&iommu0 M4U_PORT_L7_VENC_REC>,
1530                                  <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1531                                  <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1532                                  <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1533                                  <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1534                                  <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1535                                  <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1536                                  <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1537                                  <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1538                                  <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;
1539                         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>;
1540                         mediatek,scp = <&scp>;
1541                         power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
1542                         clocks = <&vencsys CLK_VENC_SET1_VENC>;
1543                         clock-names = "venc_sel";
1544                         assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1545                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
1546                 };
1547
1548                 camsys: clock-controller@1a000000 {
1549                         compatible = "mediatek,mt8192-camsys";
1550                         reg = <0 0x1a000000 0 0x1000>;
1551                         #clock-cells = <1>;
1552                 };
1553
1554                 larb13: larb@1a001000 {
1555                         compatible = "mediatek,mt8192-smi-larb";
1556                         reg = <0 0x1a001000 0 0x1000>;
1557                         mediatek,larb-id = <13>;
1558                         mediatek,smi = <&smi_common>;
1559                         clocks = <&camsys CLK_CAM_CAM>,
1560                                  <&camsys CLK_CAM_LARB13>;
1561                         clock-names = "apb", "smi";
1562                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1563                 };
1564
1565                 larb14: larb@1a002000 {
1566                         compatible = "mediatek,mt8192-smi-larb";
1567                         reg = <0 0x1a002000 0 0x1000>;
1568                         mediatek,larb-id = <14>;
1569                         mediatek,smi = <&smi_common>;
1570                         clocks = <&camsys CLK_CAM_CAM>,
1571                                  <&camsys CLK_CAM_LARB14>;
1572                         clock-names = "apb", "smi";
1573                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
1574                 };
1575
1576                 larb16: larb@1a00f000 {
1577                         compatible = "mediatek,mt8192-smi-larb";
1578                         reg = <0 0x1a00f000 0 0x1000>;
1579                         mediatek,larb-id = <16>;
1580                         mediatek,smi = <&smi_common>;
1581                         clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
1582                                  <&camsys_rawa CLK_CAM_RAWA_LARBX>;
1583                         clock-names = "apb", "smi";
1584                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
1585                 };
1586
1587                 larb17: larb@1a010000 {
1588                         compatible = "mediatek,mt8192-smi-larb";
1589                         reg = <0 0x1a010000 0 0x1000>;
1590                         mediatek,larb-id = <17>;
1591                         mediatek,smi = <&smi_common>;
1592                         clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
1593                                  <&camsys_rawb CLK_CAM_RAWB_LARBX>;
1594                         clock-names = "apb", "smi";
1595                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
1596                 };
1597
1598                 larb18: larb@1a011000 {
1599                         compatible = "mediatek,mt8192-smi-larb";
1600                         reg = <0 0x1a011000 0 0x1000>;
1601                         mediatek,larb-id = <18>;
1602                         mediatek,smi = <&smi_common>;
1603                         clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
1604                                  <&camsys_rawc CLK_CAM_RAWC_CAM>;
1605                         clock-names = "apb", "smi";
1606                         power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
1607                 };
1608
1609                 camsys_rawa: clock-controller@1a04f000 {
1610                         compatible = "mediatek,mt8192-camsys_rawa";
1611                         reg = <0 0x1a04f000 0 0x1000>;
1612                         #clock-cells = <1>;
1613                 };
1614
1615                 camsys_rawb: clock-controller@1a06f000 {
1616                         compatible = "mediatek,mt8192-camsys_rawb";
1617                         reg = <0 0x1a06f000 0 0x1000>;
1618                         #clock-cells = <1>;
1619                 };
1620
1621                 camsys_rawc: clock-controller@1a08f000 {
1622                         compatible = "mediatek,mt8192-camsys_rawc";
1623                         reg = <0 0x1a08f000 0 0x1000>;
1624                         #clock-cells = <1>;
1625                 };
1626
1627                 ipesys: clock-controller@1b000000 {
1628                         compatible = "mediatek,mt8192-ipesys";
1629                         reg = <0 0x1b000000 0 0x1000>;
1630                         #clock-cells = <1>;
1631                 };
1632
1633                 larb20: larb@1b00f000 {
1634                         compatible = "mediatek,mt8192-smi-larb";
1635                         reg = <0 0x1b00f000 0 0x1000>;
1636                         mediatek,larb-id = <20>;
1637                         mediatek,smi = <&smi_common>;
1638                         clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1639                                  <&ipesys CLK_IPE_LARB20>;
1640                         clock-names = "apb", "smi";
1641                         power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1642                 };
1643
1644                 larb19: larb@1b10f000 {
1645                         compatible = "mediatek,mt8192-smi-larb";
1646                         reg = <0 0x1b10f000 0 0x1000>;
1647                         mediatek,larb-id = <19>;
1648                         mediatek,smi = <&smi_common>;
1649                         clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
1650                                  <&ipesys CLK_IPE_LARB19>;
1651                         clock-names = "apb", "smi";
1652                         power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
1653                 };
1654
1655                 mdpsys: clock-controller@1f000000 {
1656                         compatible = "mediatek,mt8192-mdpsys";
1657                         reg = <0 0x1f000000 0 0x1000>;
1658                         #clock-cells = <1>;
1659                 };
1660
1661                 larb2: larb@1f002000 {
1662                         compatible = "mediatek,mt8192-smi-larb";
1663                         reg = <0 0x1f002000 0 0x1000>;
1664                         mediatek,larb-id = <2>;
1665                         mediatek,smi = <&smi_common>;
1666                         clocks = <&mdpsys CLK_MDP_SMI0>,
1667                                  <&mdpsys CLK_MDP_SMI0>;
1668                         clock-names = "apb", "smi";
1669                         power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
1670                 };
1671         };
1672 };