arch/arm64/boot/dts/mediatek/mt8186.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (C) 2022 MediaTek Inc.
   4  * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
   5  */
   6 /dts-v1/;
   7 #include <dt-bindings/clock/mt8186-clk.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
  11 #include <dt-bindings/power/mt8186-power.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/reset/mt8186-resets.h>
  14
  15 / {
  16         compatible = "mediatek,mt8186";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu0>;
  29                                 };
  30
  31                                 core1 {
  32                                         cpu = <&cpu1>;
  33                                 };
  34
  35                                 core2 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38
  39                                 core3 {
  40                                         cpu = <&cpu3>;
  41                                 };
  42
  43                                 core4 {
  44                                         cpu = <&cpu4>;
  45                                 };
  46
  47                                 core5 {
  48                                         cpu = <&cpu5>;
  49                                 };
  50
  51                                 core6 {
  52                                         cpu = <&cpu6>;
  53                                 };
  54
  55                                 core7 {
  56                                         cpu = <&cpu7>;
  57                                 };
  58                         };
  59                 };
  60
  61                 cpu0: cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a55";
  64                         reg = <0x000>;
  65                         enable-method = "psci";
  66                         clock-frequency = <2000000000>;
  67                         capacity-dmips-mhz = <382>;
  68                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  69                         next-level-cache = <&l2_0>;
  70                         #cooling-cells = <2>;
  71                 };
  72
  73                 cpu1: cpu@100 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a55";
  76                         reg = <0x100>;
  77                         enable-method = "psci";
  78                         clock-frequency = <2000000000>;
  79                         capacity-dmips-mhz = <382>;
  80                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  81                         next-level-cache = <&l2_0>;
  82                         #cooling-cells = <2>;
  83                 };
  84
  85                 cpu2: cpu@200 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a55";
  88                         reg = <0x200>;
  89                         enable-method = "psci";
  90                         clock-frequency = <2000000000>;
  91                         capacity-dmips-mhz = <382>;
  92                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
  93                         next-level-cache = <&l2_0>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu3: cpu@300 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a55";
 100                         reg = <0x300>;
 101                         enable-method = "psci";
 102                         clock-frequency = <2000000000>;
 103                         capacity-dmips-mhz = <382>;
 104                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
 105                         next-level-cache = <&l2_0>;
 106                         #cooling-cells = <2>;
 107                 };
 108
 109                 cpu4: cpu@400 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a55";
 112                         reg = <0x400>;
 113                         enable-method = "psci";
 114                         clock-frequency = <2000000000>;
 115                         capacity-dmips-mhz = <382>;
 116                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
 117                         next-level-cache = <&l2_0>;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu5: cpu@500 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a55";
 124                         reg = <0x500>;
 125                         enable-method = "psci";
 126                         clock-frequency = <2000000000>;
 127                         capacity-dmips-mhz = <382>;
 128                         cpu-idle-states = <&cpu_off_l &cluster_off_l>;
 129                         next-level-cache = <&l2_0>;
 130                         #cooling-cells = <2>;
 131                 };
 132
 133                 cpu6: cpu@600 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a76";
 136                         reg = <0x600>;
 137                         enable-method = "psci";
 138                         clock-frequency = <2050000000>;
 139                         capacity-dmips-mhz = <1024>;
 140                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 141                         next-level-cache = <&l2_1>;
 142                         #cooling-cells = <2>;
 143                 };
 144
 145                 cpu7: cpu@700 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a76";
 148                         reg = <0x700>;
 149                         enable-method = "psci";
 150                         clock-frequency = <2050000000>;
 151                         capacity-dmips-mhz = <1024>;
 152                         cpu-idle-states = <&cpu_off_b &cluster_off_b>;
 153                         next-level-cache = <&l2_1>;
 154                         #cooling-cells = <2>;
 155                 };
 156
 157                 idle-states {
 158                         entry-method = "psci";
 159
 160                         cpu_off_l: cpu-off-l {
 161                                 compatible = "arm,idle-state";
 162                                 arm,psci-suspend-param = <0x00010001>;
 163                                 local-timer-stop;
 164                                 entry-latency-us = <50>;
 165                                 exit-latency-us = <100>;
 166                                 min-residency-us = <1600>;
 167                         };
 168
 169                         cpu_off_b: cpu-off-b {
 170                                 compatible = "arm,idle-state";
 171                                 arm,psci-suspend-param = <0x00010001>;
 172                                 local-timer-stop;
 173                                 entry-latency-us = <50>;
 174                                 exit-latency-us = <100>;
 175                                 min-residency-us = <1400>;
 176                         };
 177
 178                         cluster_off_l: cluster-off-l {
 179                                 compatible = "arm,idle-state";
 180                                 arm,psci-suspend-param = <0x01010001>;
 181                                 local-timer-stop;
 182                                 entry-latency-us = <100>;
 183                                 exit-latency-us = <250>;
 184                                 min-residency-us = <2100>;
 185                         };
 186
 187                         cluster_off_b: cluster-off-b {
 188                                 compatible = "arm,idle-state";
 189                                 arm,psci-suspend-param = <0x01010001>;
 190                                 local-timer-stop;
 191                                 entry-latency-us = <100>;
 192                                 exit-latency-us = <250>;
 193                                 min-residency-us = <1900>;
 194                         };
 195                 };
 196
 197                 l2_0: l2-cache0 {
 198                         compatible = "cache";
 199                         next-level-cache = <&l3_0>;
 200                 };
 201
 202                 l2_1: l2-cache1 {
 203                         compatible = "cache";
 204                         next-level-cache = <&l3_0>;
 205                 };
 206
 207                 l3_0: l3-cache {
 208                         compatible = "cache";
 209                 };
 210         };
 211
 212         clk13m: fixed-factor-clock-13m {
 213                 compatible = "fixed-factor-clock";
 214                 #clock-cells = <0>;
 215                 clocks = <&clk26m>;
 216                 clock-div = <2>;
 217                 clock-mult = <1>;
 218                 clock-output-names = "clk13m";
 219         };
 220
 221         clk26m: oscillator-26m {
 222                 compatible = "fixed-clock";
 223                 #clock-cells = <0>;
 224                 clock-frequency = <26000000>;
 225                 clock-output-names = "clk26m";
 226         };
 227
 228         clk32k: oscillator-32k {
 229                 compatible = "fixed-clock";
 230                 #clock-cells = <0>;
 231                 clock-frequency = <32768>;
 232                 clock-output-names = "clk32k";
 233         };
 234
 235         pmu-a55 {
 236                 compatible = "arm,cortex-a55-pmu";
 237                 interrupt-parent = <&gic>;
 238                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 239         };
 240
 241         pmu-a76 {
 242                 compatible = "arm,cortex-a76-pmu";
 243                 interrupt-parent = <&gic>;
 244                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 245         };
 246
 247         psci {
 248                 compatible = "arm,psci-1.0";
 249                 method = "smc";
 250         };
 251
 252         timer {
 253                 compatible = "arm,armv8-timer";
 254                 interrupt-parent = <&gic>;
 255                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 256                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 257                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 258                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 259         };
 260
 261         soc {
 262                 #address-cells = <2>;
 263                 #size-cells = <2>;
 264                 compatible = "simple-bus";
 265                 ranges;
 266
 267                 gic: interrupt-controller@c000000 {
 268                         compatible = "arm,gic-v3";
 269                         #interrupt-cells = <4>;
 270                         #redistributor-regions = <1>;
 271                         interrupt-parent = <&gic>;
 272                         interrupt-controller;
 273                         reg = <0 0x0c000000 0 0x40000>,
 274                               <0 0x0c040000 0 0x200000>;
 275                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 276
 277                         ppi-partitions {
 278                                 ppi_cluster0: interrupt-partition-0 {
 279                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
 280                                 };
 281
 282                                 ppi_cluster1: interrupt-partition-1 {
 283                                         affinity = <&cpu6 &cpu7>;
 284                                 };
 285                         };
 286                 };
 287
 288                 mcusys: syscon@c53a000 {
 289                         compatible = "mediatek,mt8186-mcusys", "syscon";
 290                         reg = <0 0xc53a000 0 0x1000>;
 291                         #clock-cells = <1>;
 292                 };
 293
 294                 topckgen: syscon@10000000 {
 295                         compatible = "mediatek,mt8186-topckgen", "syscon";
 296                         reg = <0 0x10000000 0 0x1000>;
 297                         #clock-cells = <1>;
 298                 };
 299
 300                 infracfg_ao: syscon@10001000 {
 301                         compatible = "mediatek,mt8186-infracfg_ao", "syscon";
 302                         reg = <0 0x10001000 0 0x1000>;
 303                         #clock-cells = <1>;
 304                         #reset-cells = <1>;
 305                 };
 306
 307                 pericfg: syscon@10003000 {
 308                         compatible = "mediatek,mt8186-pericfg", "syscon";
 309                         reg = <0 0x10003000 0 0x1000>;
 310                 };
 311
 312                 pio: pinctrl@10005000 {
 313                         compatible = "mediatek,mt8186-pinctrl";
 314                         reg = <0 0x10005000 0 0x1000>,
 315                               <0 0x10002000 0 0x0200>,
 316                               <0 0x10002200 0 0x0200>,
 317                               <0 0x10002400 0 0x0200>,
 318                               <0 0x10002600 0 0x0200>,
 319                               <0 0x10002a00 0 0x0200>,
 320                               <0 0x10002c00 0 0x0200>,
 321                               <0 0x1000b000 0 0x1000>;
 322                         reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
 323                                     "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
 324                         gpio-controller;
 325                         #gpio-cells = <2>;
 326                         gpio-ranges = <&pio 0 0 185>;
 327                         interrupt-controller;
 328                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
 329                         #interrupt-cells = <2>;
 330                 };
 331
 332                 watchdog: watchdog@10007000 {
 333                         compatible = "mediatek,mt8186-wdt";
 334                         mediatek,disable-extrst;
 335                         reg = <0 0x10007000 0 0x1000>;
 336                         #reset-cells = <1>;
 337                 };
 338
 339                 apmixedsys: syscon@1000c000 {
 340                         compatible = "mediatek,mt8186-apmixedsys", "syscon";
 341                         reg = <0 0x1000c000 0 0x1000>;
 342                         #clock-cells = <1>;
 343                 };
 344
 345                 pwrap: pwrap@1000d000 {
 346                         compatible = "mediatek,mt8186-pwrap", "syscon";
 347                         reg = <0 0x1000d000 0 0x1000>;
 348                         reg-names = "pwrap";
 349                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
 350                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 351                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 352                         clock-names = "spi", "wrap";
 353                 };
 354
 355                 systimer: timer@10017000 {
 356                         compatible = "mediatek,mt8186-timer",
 357                                      "mediatek,mt6765-timer";
 358                         reg = <0 0x10017000 0 0x1000>;
 359                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
 360                         clocks = <&clk13m>;
 361                 };
 362
 363                 scp: scp@10500000 {
 364                         compatible = "mediatek,mt8186-scp";
 365                         reg = <0 0x10500000 0 0x40000>,
 366                               <0 0x105c0000 0 0x19080>;
 367                         reg-names = "sram", "cfg";
 368                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 };
 370
 371                 nor_flash: spi@11000000 {
 372                         compatible = "mediatek,mt8186-nor";
 373                         reg = <0 0x11000000 0 0x1000>;
 374                         clocks = <&topckgen CLK_TOP_SPINOR>,
 375                                  <&infracfg_ao CLK_INFRA_AO_SPINOR>,
 376                                  <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
 377                                  <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
 378                         clock-names = "spi", "sf", "axi", "axi_s";
 379                         assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
 380                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
 381                         interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
 382                         status = "disabled";
 383                 };
 384
 385                 auxadc: adc@11001000 {
 386                         compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
 387                         reg = <0 0x11001000 0 0x1000>;
 388                         #io-channel-cells = <1>;
 389                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
 390                         clock-names = "main";
 391                 };
 392
 393                 uart0: serial@11002000 {
 394                         compatible = "mediatek,mt8186-uart",
 395                                      "mediatek,mt6577-uart";
 396                         reg = <0 0x11002000 0 0x1000>;
 397                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
 398                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
 399                         clock-names = "baud", "bus";
 400                         status = "disabled";
 401                 };
 402
 403                 uart1: serial@11003000 {
 404                         compatible = "mediatek,mt8186-uart",
 405                                      "mediatek,mt6577-uart";
 406                         reg = <0 0x11003000 0 0x1000>;
 407                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
 408                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
 409                         clock-names = "baud", "bus";
 410                         status = "disabled";
 411                 };
 412
 413                 i2c0: i2c@11007000 {
 414                         compatible = "mediatek,mt8186-i2c";
 415                         reg = <0 0x11007000 0 0x1000>,
 416                               <0 0x10200100 0 0x100>;
 417                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 418                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
 419                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 420                         clock-names = "main", "dma";
 421                         clock-div = <1>;
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         status = "disabled";
 425                 };
 426
 427                 i2c1: i2c@11008000 {
 428                         compatible = "mediatek,mt8186-i2c";
 429                         reg = <0 0x11008000 0 0x1000>,
 430                               <0 0x10200200 0 0x100>;
 431                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
 432                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
 433                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 434                         clock-names = "main", "dma";
 435                         clock-div = <1>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         status = "disabled";
 439                 };
 440
 441                 i2c2: i2c@11009000 {
 442                         compatible = "mediatek,mt8186-i2c";
 443                         reg = <0 0x11009000 0 0x1000>,
 444                               <0 0x10200300 0 0x180>;
 445                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
 446                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
 447                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 448                         clock-names = "main", "dma";
 449                         clock-div = <1>;
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         status = "disabled";
 453                 };
 454
 455                 i2c3: i2c@1100f000 {
 456                         compatible = "mediatek,mt8186-i2c";
 457                         reg = <0 0x1100f000 0 0x1000>,
 458                               <0 0x10200480 0 0x100>;
 459                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
 460                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
 461                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 462                         clock-names = "main", "dma";
 463                         clock-div = <1>;
 464                         #address-cells = <1>;
 465                         #size-cells = <0>;
 466                         status = "disabled";
 467                 };
 468
 469                 i2c4: i2c@11011000 {
 470                         compatible = "mediatek,mt8186-i2c";
 471                         reg = <0 0x11011000 0 0x1000>,
 472                               <0 0x10200580 0 0x180>;
 473                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
 474                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
 475                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 476                         clock-names = "main", "dma";
 477                         clock-div = <1>;
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         status = "disabled";
 481                 };
 482
 483                 i2c5: i2c@11016000 {
 484                         compatible = "mediatek,mt8186-i2c";
 485                         reg = <0 0x11016000 0 0x1000>,
 486                               <0 0x10200700 0 0x100>;
 487                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
 488                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
 489                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 490                         clock-names = "main", "dma";
 491                         clock-div = <1>;
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         status = "disabled";
 495                 };
 496
 497                 i2c6: i2c@1100d000 {
 498                         compatible = "mediatek,mt8186-i2c";
 499                         reg = <0 0x1100d000 0 0x1000>,
 500                               <0 0x10200800 0 0x100>;
 501                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
 502                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
 503                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 504                         clock-names = "main", "dma";
 505                         clock-div = <1>;
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                         status = "disabled";
 509                 };
 510
 511                 i2c7: i2c@11004000 {
 512                         compatible = "mediatek,mt8186-i2c";
 513                         reg = <0 0x11004000 0 0x1000>,
 514                               <0 0x10200900 0 0x180>;
 515                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 516                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
 517                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 518                         clock-names = "main", "dma";
 519                         clock-div = <1>;
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         status = "disabled";
 523                 };
 524
 525                 i2c8: i2c@11005000 {
 526                         compatible = "mediatek,mt8186-i2c";
 527                         reg = <0 0x11005000 0 0x1000>,
 528                               <0 0x10200A80 0 0x180>;
 529                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
 530                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
 531                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 532                         clock-names = "main", "dma";
 533                         clock-div = <1>;
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         status = "disabled";
 537                 };
 538
 539                 spi0: spi@1100a000 {
 540                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 541                         #address-cells = <1>;
 542                         #size-cells = <0>;
 543                         reg = <0 0x1100a000 0 0x1000>;
 544                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
 545                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 546                                  <&topckgen CLK_TOP_SPI>,
 547                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
 548                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 549                         status = "disabled";
 550                 };
 551
 552                 pwm0: pwm@1100e000 {
 553                         compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
 554                         reg = <0 0x1100e000 0 0x1000>;
 555                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
 556                         #pwm-cells = <2>;
 557                         clocks = <&topckgen CLK_TOP_DISP_PWM>,
 558                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
 559                         clock-names = "main", "mm";
 560                         status = "disabled";
 561                 };
 562
 563                 spi1: spi@11010000 {
 564                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         reg = <0 0x11010000 0 0x1000>;
 568                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
 569                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 570                                  <&topckgen CLK_TOP_SPI>,
 571                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
 572                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 573                         status = "disabled";
 574                 };
 575
 576                 spi2: spi@11012000 {
 577                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         reg = <0 0x11012000 0 0x1000>;
 581                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
 582                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 583                                  <&topckgen CLK_TOP_SPI>,
 584                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
 585                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 586                         status = "disabled";
 587                 };
 588
 589                 spi3: spi@11013000 {
 590                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 591                         #address-cells = <1>;
 592                         #size-cells = <0>;
 593                         reg = <0 0x11013000 0 0x1000>;
 594                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
 595                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 596                                  <&topckgen CLK_TOP_SPI>,
 597                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
 598                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 599                         status = "disabled";
 600                 };
 601
 602                 spi4: spi@11014000 {
 603                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606                         reg = <0 0x11014000 0 0x1000>;
 607                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 608                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 609                                  <&topckgen CLK_TOP_SPI>,
 610                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
 611                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 612                         status = "disabled";
 613                 };
 614
 615                 spi5: spi@11015000 {
 616                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                         reg = <0 0x11015000 0 0x1000>;
 620                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 621                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
 622                                  <&topckgen CLK_TOP_SPI>,
 623                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
 624                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 625                         status = "disabled";
 626                 };
 627
 628                 imp_iic_wrap: clock-controller@11017000 {
 629                         compatible = "mediatek,mt8186-imp_iic_wrap";
 630                         reg = <0 0x11017000 0 0x1000>;
 631                         #clock-cells = <1>;
 632                 };
 633
 634                 uart2: serial@11018000 {
 635                         compatible = "mediatek,mt8186-uart",
 636                                      "mediatek,mt6577-uart";
 637                         reg = <0 0x11018000 0 0x1000>;
 638                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
 639                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
 640                         clock-names = "baud", "bus";
 641                         status = "disabled";
 642                 };
 643
 644                 i2c9: i2c@11019000 {
 645                         compatible = "mediatek,mt8186-i2c";
 646                         reg = <0 0x11019000 0 0x1000>,
 647                               <0 0x10200c00 0 0x180>;
 648                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
 649                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
 650                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
 651                         clock-names = "main", "dma";
 652                         clock-div = <1>;
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         status = "disabled";
 656                 };
 657
 658                 mmc0: mmc@11230000 {
 659                         compatible = "mediatek,mt8186-mmc",
 660                                      "mediatek,mt8183-mmc";
 661                         reg = <0 0x11230000 0 0x1000>,
 662                               <0 0x11cd0000 0 0x1000>;
 663                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
 664                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
 665                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
 666                         clock-names = "source", "hclk", "source_cg";
 667                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 668                         assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
 669                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
 670                         status = "disabled";
 671                 };
 672
 673                 mmc1: mmc@11240000 {
 674                         compatible = "mediatek,mt8186-mmc",
 675                                      "mediatek,mt8183-mmc";
 676                         reg = <0 0x11240000 0 0x1000>,
 677                               <0 0x11c90000 0 0x1000>;
 678                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
 679                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
 680                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
 681                         clock-names = "source", "hclk", "source_cg";
 682                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 683                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
 684                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
 685                         status = "disabled";
 686                 };
 687
 688                 u3phy0: t-phy@11c80000 {
 689                         compatible = "mediatek,mt8186-tphy",
 690                                      "mediatek,generic-tphy-v2";
 691                         #address-cells = <1>;
 692                         #size-cells = <1>;
 693                         ranges = <0x0 0x0 0x11c80000 0x1000>;
 694                         status = "disabled";
 695
 696                         u2port1: usb-phy@0 {
 697                                 reg = <0x0 0x700>;
 698                                 clocks = <&clk26m>;
 699                                 clock-names = "ref";
 700                                 #phy-cells = <1>;
 701                         };
 702
 703                         u3port1: usb-phy@700 {
 704                                 reg = <0x700 0x900>;
 705                                 clocks = <&clk26m>;
 706                                 clock-names = "ref";
 707                                 #phy-cells = <1>;
 708                         };
 709                 };
 710
 711                 u3phy1: t-phy@11ca0000 {
 712                         compatible = "mediatek,mt8186-tphy",
 713                                      "mediatek,generic-tphy-v2";
 714                         #address-cells = <1>;
 715                         #size-cells = <1>;
 716                         ranges = <0x0 0x0 0x11ca0000 0x1000>;
 717                         status = "disabled";
 718
 719                         u2port0: usb-phy@0 {
 720                                 reg = <0x0 0x700>;
 721                                 clocks = <&clk26m>;
 722                                 clock-names = "ref";
 723                                 #phy-cells = <1>;
 724                                 mediatek,discth = <0x8>;
 725                         };
 726                 };
 727
 728                 efuse: efuse@11cb0000 {
 729                         compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
 730                         reg = <0 0x11cb0000 0 0x1000>;
 731                         #address-cells = <1>;
 732                         #size-cells = <1>;
 733                 };
 734
 735                 mipi_tx0: dsi-phy@11cc0000 {
 736                         compatible = "mediatek,mt8183-mipi-tx";
 737                         reg = <0 0x11cc0000 0 0x1000>;
 738                         clocks = <&clk26m>;
 739                         #clock-cells = <0>;
 740                         #phy-cells = <0>;
 741                         clock-output-names = "mipi_tx0_pll";
 742                         status = "disabled";
 743                 };
 744
 745                 mfgsys: clock-controller@13000000 {
 746                         compatible = "mediatek,mt8186-mfgsys";
 747                         reg = <0 0x13000000 0 0x1000>;
 748                         #clock-cells = <1>;
 749                 };
 750
 751                 mmsys: syscon@14000000 {
 752                         compatible = "mediatek,mt8186-mmsys", "syscon";
 753                         reg = <0 0x14000000 0 0x1000>;
 754                         #clock-cells = <1>;
 755                         #reset-cells = <1>;
 756                 };
 757
 758                 wpesys: clock-controller@14020000 {
 759                         compatible = "mediatek,mt8186-wpesys";
 760                         reg = <0 0x14020000 0 0x1000>;
 761                         #clock-cells = <1>;
 762                 };
 763
 764                 imgsys1: clock-controller@15020000 {
 765                         compatible = "mediatek,mt8186-imgsys1";
 766                         reg = <0 0x15020000 0 0x1000>;
 767                         #clock-cells = <1>;
 768                 };
 769
 770                 imgsys2: clock-controller@15820000 {
 771                         compatible = "mediatek,mt8186-imgsys2";
 772                         reg = <0 0x15820000 0 0x1000>;
 773                         #clock-cells = <1>;
 774                 };
 775
 776                 vdecsys: clock-controller@1602f000 {
 777                         compatible = "mediatek,mt8186-vdecsys";
 778                         reg = <0 0x1602f000 0 0x1000>;
 779                         #clock-cells = <1>;
 780                 };
 781
 782                 vencsys: clock-controller@17000000 {
 783                         compatible = "mediatek,mt8186-vencsys";
 784                         reg = <0 0x17000000 0 0x1000>;
 785                         #clock-cells = <1>;
 786                 };
 787
 788                 camsys: clock-controller@1a000000 {
 789                         compatible = "mediatek,mt8186-camsys";
 790                         reg = <0 0x1a000000 0 0x1000>;
 791                         #clock-cells = <1>;
 792                 };
 793
 794                 camsys_rawa: clock-controller@1a04f000 {
 795                         compatible = "mediatek,mt8186-camsys_rawa";
 796                         reg = <0 0x1a04f000 0 0x1000>;
 797                         #clock-cells = <1>;
 798                 };
 799
 800                 camsys_rawb: clock-controller@1a06f000 {
 801                         compatible = "mediatek,mt8186-camsys_rawb";
 802                         reg = <0 0x1a06f000 0 0x1000>;
 803                         #clock-cells = <1>;
 804                 };
 805
 806                 mdpsys: clock-controller@1b000000 {
 807                         compatible = "mediatek,mt8186-mdpsys";
 808                         reg = <0 0x1b000000 0 0x1000>;
 809                         #clock-cells = <1>;
 810                 };
 811
 812                 ipesys: clock-controller@1c000000 {
 813                         compatible = "mediatek,mt8186-ipesys";
 814                         reg = <0 0x1c000000 0 0x1000>;
 815                         #clock-cells = <1>;
 816                 };
 817         };
 818 };