arch/arm64/boot/dts/mediatek/mt8186.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (C) 2022 MediaTek Inc.
   4  * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
   5  */
   6 /dts-v1/;
   7 #include <dt-bindings/clock/mt8186-clk.h>
   8 #include <dt-bindings/gce/mt8186-gce.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/memory/mt8186-memory-port.h>
  12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
  13 #include <dt-bindings/power/mt8186-power.h>
  14 #include <dt-bindings/phy/phy.h>
  15 #include <dt-bindings/reset/mt8186-resets.h>
  16
  17 / {
  18         compatible = "mediatek,mt8186";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 ovl0 = &ovl0;
  25                 ovl_2l0 = &ovl_2l0;
  26                 rdma0 = &rdma0;
  27                 rdma1 = &rdma1;
  28         };
  29
  30         cci: cci {
  31                 compatible = "mediatek,mt8186-cci";
  32                 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
  33                          <&apmixedsys CLK_APMIXED_MAINPLL>;
  34                 clock-names = "cci", "intermediate";
  35                 operating-points-v2 = <&cci_opp>;
  36         };
  37
  38         cci_opp: opp-table-cci {
  39                 compatible = "operating-points-v2";
  40                 opp-shared;
  41
  42                 cci_opp_0: opp-500000000 {
  43                         opp-hz = /bits/ 64 <500000000>;
  44                         opp-microvolt = <600000>;
  45                 };
  46
  47                 cci_opp_1: opp-560000000 {
  48                         opp-hz = /bits/ 64 <560000000>;
  49                         opp-microvolt = <675000>;
  50                 };
  51
  52                 cci_opp_2: opp-612000000 {
  53                         opp-hz = /bits/ 64 <612000000>;
  54                         opp-microvolt = <693750>;
  55                 };
  56
  57                 cci_opp_3: opp-682000000 {
  58                         opp-hz = /bits/ 64 <682000000>;
  59                         opp-microvolt = <718750>;
  60                 };
  61
  62                 cci_opp_4: opp-752000000 {
  63                         opp-hz = /bits/ 64 <752000000>;
  64                         opp-microvolt = <743750>;
  65                 };
  66
  67                 cci_opp_5: opp-822000000 {
  68                         opp-hz = /bits/ 64 <822000000>;
  69                         opp-microvolt = <768750>;
  70                 };
  71
  72                 cci_opp_6: opp-875000000 {
  73                         opp-hz = /bits/ 64 <875000000>;
  74                         opp-microvolt = <781250>;
  75                 };
  76
  77                 cci_opp_7: opp-927000000 {
  78                         opp-hz = /bits/ 64 <927000000>;
  79                         opp-microvolt = <800000>;
  80                 };
  81
  82                 cci_opp_8: opp-980000000 {
  83                         opp-hz = /bits/ 64 <980000000>;
  84                         opp-microvolt = <818750>;
  85                 };
  86
  87                 cci_opp_9: opp-1050000000 {
  88                         opp-hz = /bits/ 64 <1050000000>;
  89                         opp-microvolt = <843750>;
  90                 };
  91
  92                 cci_opp_10: opp-1120000000 {
  93                         opp-hz = /bits/ 64 <1120000000>;
  94                         opp-microvolt = <862500>;
  95                 };
  96
  97                 cci_opp_11: opp-1155000000 {
  98                         opp-hz = /bits/ 64 <1155000000>;
  99                         opp-microvolt = <887500>;
 100                 };
 101
 102                 cci_opp_12: opp-1190000000 {
 103                         opp-hz = /bits/ 64 <1190000000>;
 104                         opp-microvolt = <906250>;
 105                 };
 106
 107                 cci_opp_13: opp-1260000000 {
 108                         opp-hz = /bits/ 64 <1260000000>;
 109                         opp-microvolt = <950000>;
 110                 };
 111
 112                 cci_opp_14: opp-1330000000 {
 113                         opp-hz = /bits/ 64 <1330000000>;
 114                         opp-microvolt = <993750>;
 115                 };
 116
 117                 cci_opp_15: opp-1400000000 {
 118                         opp-hz = /bits/ 64 <1400000000>;
 119                         opp-microvolt = <1031250>;
 120                 };
 121         };
 122
 123         cluster0_opp: opp-table-cluster0 {
 124                 compatible = "operating-points-v2";
 125                 opp-shared;
 126
 127                 opp-500000000 {
 128                         opp-hz = /bits/ 64 <500000000>;
 129                         opp-microvolt = <600000>;
 130                         required-opps = <&cci_opp_0>;
 131                 };
 132
 133                 opp-774000000 {
 134                         opp-hz = /bits/ 64 <774000000>;
 135                         opp-microvolt = <675000>;
 136                         required-opps = <&cci_opp_1>;
 137                 };
 138
 139                 opp-875000000 {
 140                         opp-hz = /bits/ 64 <875000000>;
 141                         opp-microvolt = <700000>;
 142                         required-opps = <&cci_opp_2>;
 143                 };
 144
 145                 opp-975000000 {
 146                         opp-hz = /bits/ 64 <975000000>;
 147                         opp-microvolt = <725000>;
 148                         required-opps = <&cci_opp_3>;
 149                 };
 150
 151                 opp-1075000000 {
 152                         opp-hz = /bits/ 64 <1075000000>;
 153                         opp-microvolt = <750000>;
 154                         required-opps = <&cci_opp_4>;
 155                 };
 156
 157                 opp-1175000000 {
 158                         opp-hz = /bits/ 64 <1175000000>;
 159                         opp-microvolt = <775000>;
 160                         required-opps = <&cci_opp_5>;
 161                 };
 162
 163                 opp-1275000000 {
 164                         opp-hz = /bits/ 64 <1275000000>;
 165                         opp-microvolt = <800000>;
 166                         required-opps = <&cci_opp_6>;
 167                 };
 168
 169                 opp-1375000000 {
 170                         opp-hz = /bits/ 64 <1375000000>;
 171                         opp-microvolt = <825000>;
 172                         required-opps = <&cci_opp_7>;
 173                 };
 174
 175                 opp-1500000000 {
 176                         opp-hz = /bits/ 64 <1500000000>;
 177                         opp-microvolt = <856250>;
 178                         required-opps = <&cci_opp_8>;
 179                 };
 180
 181                 opp-1618000000 {
 182                         opp-hz = /bits/ 64 <1618000000>;
 183                         opp-microvolt = <875000>;
 184                         required-opps = <&cci_opp_9>;
 185                 };
 186
 187                 opp-1666000000 {
 188                         opp-hz = /bits/ 64 <1666000000>;
 189                         opp-microvolt = <900000>;
 190                         required-opps = <&cci_opp_10>;
 191                 };
 192
 193                 opp-1733000000 {
 194                         opp-hz = /bits/ 64 <1733000000>;
 195                         opp-microvolt = <925000>;
 196                         required-opps = <&cci_opp_11>;
 197                 };
 198
 199                 opp-1800000000 {
 200                         opp-hz = /bits/ 64 <1800000000>;
 201                         opp-microvolt = <950000>;
 202                         required-opps = <&cci_opp_12>;
 203                 };
 204
 205                 opp-1866000000 {
 206                         opp-hz = /bits/ 64 <1866000000>;
 207                         opp-microvolt = <981250>;
 208                         required-opps = <&cci_opp_13>;
 209                 };
 210
 211                 opp-1933000000 {
 212                         opp-hz = /bits/ 64 <1933000000>;
 213                         opp-microvolt = <1006250>;
 214                         required-opps = <&cci_opp_14>;
 215                 };
 216
 217                 opp-2000000000 {
 218                         opp-hz = /bits/ 64 <2000000000>;
 219                         opp-microvolt = <1031250>;
 220                         required-opps = <&cci_opp_15>;
 221                 };
 222         };
 223
 224         cluster1_opp: opp-table-cluster1 {
 225                 compatible = "operating-points-v2";
 226                 opp-shared;
 227
 228                 opp-774000000 {
 229                         opp-hz = /bits/ 64 <774000000>;
 230                         opp-microvolt = <675000>;
 231                         required-opps = <&cci_opp_0>;
 232                 };
 233
 234                 opp-835000000 {
 235                         opp-hz = /bits/ 64 <835000000>;
 236                         opp-microvolt = <693750>;
 237                         required-opps = <&cci_opp_1>;
 238                 };
 239
 240                 opp-919000000 {
 241                         opp-hz = /bits/ 64 <919000000>;
 242                         opp-microvolt = <718750>;
 243                         required-opps = <&cci_opp_2>;
 244                 };
 245
 246                 opp-1002000000 {
 247                         opp-hz = /bits/ 64 <1002000000>;
 248                         opp-microvolt = <743750>;
 249                         required-opps = <&cci_opp_3>;
 250                 };
 251
 252                 opp-1085000000 {
 253                         opp-hz = /bits/ 64 <1085000000>;
 254                         opp-microvolt = <775000>;
 255                         required-opps = <&cci_opp_4>;
 256                 };
 257
 258                 opp-1169000000 {
 259                         opp-hz = /bits/ 64 <1169000000>;
 260                         opp-microvolt = <800000>;
 261                         required-opps = <&cci_opp_5>;
 262                 };
 263
 264                 opp-1308000000 {
 265                         opp-hz = /bits/ 64 <1308000000>;
 266                         opp-microvolt = <843750>;
 267                         required-opps = <&cci_opp_6>;
 268                 };
 269
 270                 opp-1419000000 {
 271                         opp-hz = /bits/ 64 <1419000000>;
 272                         opp-microvolt = <875000>;
 273                         required-opps = <&cci_opp_7>;
 274                 };
 275
 276                 opp-1530000000 {
 277                         opp-hz = /bits/ 64 <1530000000>;
 278                         opp-microvolt = <912500>;
 279                         required-opps = <&cci_opp_8>;
 280                 };
 281
 282                 opp-1670000000 {
 283                         opp-hz = /bits/ 64 <1670000000>;
 284                         opp-microvolt = <956250>;
 285                         required-opps = <&cci_opp_9>;
 286                 };
 287
 288                 opp-1733000000 {
 289                         opp-hz = /bits/ 64 <1733000000>;
 290                         opp-microvolt = <981250>;
 291                         required-opps = <&cci_opp_10>;
 292                 };
 293
 294                 opp-1796000000 {
 295                         opp-hz = /bits/ 64 <1796000000>;
 296                         opp-microvolt = <1012500>;
 297                         required-opps = <&cci_opp_11>;
 298                 };
 299
 300                 opp-1860000000 {
 301                         opp-hz = /bits/ 64 <1860000000>;
 302                         opp-microvolt = <1037500>;
 303                         required-opps = <&cci_opp_12>;
 304                 };
 305
 306                 opp-1923000000 {
 307                         opp-hz = /bits/ 64 <1923000000>;
 308                         opp-microvolt = <1062500>;
 309                         required-opps = <&cci_opp_13>;
 310                 };
 311
 312                 cluster1_opp_14: opp-1986000000 {
 313                         opp-hz = /bits/ 64 <1986000000>;
 314                         opp-microvolt = <1093750>;
 315                         required-opps = <&cci_opp_14>;
 316                 };
 317
 318                 cluster1_opp_15: opp-2050000000 {
 319                         opp-hz = /bits/ 64 <2050000000>;
 320                         opp-microvolt = <1118750>;
 321                         required-opps = <&cci_opp_15>;
 322                 };
 323         };
 324
 325         cpus {
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328
 329                 cpu-map {
 330                         cluster0 {
 331                                 core0 {
 332                                         cpu = <&cpu0>;
 333                                 };
 334
 335                                 core1 {
 336                                         cpu = <&cpu1>;
 337                                 };
 338
 339                                 core2 {
 340                                         cpu = <&cpu2>;
 341                                 };
 342
 343                                 core3 {
 344                                         cpu = <&cpu3>;
 345                                 };
 346
 347                                 core4 {
 348                                         cpu = <&cpu4>;
 349                                 };
 350
 351                                 core5 {
 352                                         cpu = <&cpu5>;
 353                                 };
 354
 355                                 core6 {
 356                                         cpu = <&cpu6>;
 357                                 };
 358
 359                                 core7 {
 360                                         cpu = <&cpu7>;
 361                                 };
 362                         };
 363                 };
 364
 365                 cpu0: cpu@0 {
 366                         device_type = "cpu";
 367                         compatible = "arm,cortex-a55";
 368                         reg = <0x000>;
 369                         enable-method = "psci";
 370                         clock-frequency = <2000000000>;
 371                         clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
 372                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 373                         clock-names = "cpu", "intermediate";
 374                         operating-points-v2 = <&cluster0_opp>;
 375                         dynamic-power-coefficient = <84>;
 376                         capacity-dmips-mhz = <382>;
 377                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 378                         i-cache-size = <32768>;
 379                         i-cache-line-size = <64>;
 380                         i-cache-sets = <128>;
 381                         d-cache-size = <32768>;
 382                         d-cache-line-size = <64>;
 383                         d-cache-sets = <128>;
 384                         next-level-cache = <&l2_0>;
 385                         #cooling-cells = <2>;
 386                         mediatek,cci = <&cci>;
 387                 };
 388
 389                 cpu1: cpu@100 {
 390                         device_type = "cpu";
 391                         compatible = "arm,cortex-a55";
 392                         reg = <0x100>;
 393                         enable-method = "psci";
 394                         clock-frequency = <2000000000>;
 395                         clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
 396                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 397                         clock-names = "cpu", "intermediate";
 398                         operating-points-v2 = <&cluster0_opp>;
 399                         dynamic-power-coefficient = <84>;
 400                         capacity-dmips-mhz = <382>;
 401                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 402                         i-cache-size = <32768>;
 403                         i-cache-line-size = <64>;
 404                         i-cache-sets = <128>;
 405                         d-cache-size = <32768>;
 406                         d-cache-line-size = <64>;
 407                         d-cache-sets = <128>;
 408                         next-level-cache = <&l2_0>;
 409                         #cooling-cells = <2>;
 410                         mediatek,cci = <&cci>;
 411                 };
 412
 413                 cpu2: cpu@200 {
 414                         device_type = "cpu";
 415                         compatible = "arm,cortex-a55";
 416                         reg = <0x200>;
 417                         enable-method = "psci";
 418                         clock-frequency = <2000000000>;
 419                         clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
 420                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 421                         clock-names = "cpu", "intermediate";
 422                         operating-points-v2 = <&cluster0_opp>;
 423                         dynamic-power-coefficient = <84>;
 424                         capacity-dmips-mhz = <382>;
 425                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 426                         i-cache-size = <32768>;
 427                         i-cache-line-size = <64>;
 428                         i-cache-sets = <128>;
 429                         d-cache-size = <32768>;
 430                         d-cache-line-size = <64>;
 431                         d-cache-sets = <128>;
 432                         next-level-cache = <&l2_0>;
 433                         #cooling-cells = <2>;
 434                         mediatek,cci = <&cci>;
 435                 };
 436
 437                 cpu3: cpu@300 {
 438                         device_type = "cpu";
 439                         compatible = "arm,cortex-a55";
 440                         reg = <0x300>;
 441                         enable-method = "psci";
 442                         clock-frequency = <2000000000>;
 443                         clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
 444                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 445                         clock-names = "cpu", "intermediate";
 446                         operating-points-v2 = <&cluster0_opp>;
 447                         dynamic-power-coefficient = <84>;
 448                         capacity-dmips-mhz = <382>;
 449                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 450                         i-cache-size = <32768>;
 451                         i-cache-line-size = <64>;
 452                         i-cache-sets = <128>;
 453                         d-cache-size = <32768>;
 454                         d-cache-line-size = <64>;
 455                         d-cache-sets = <128>;
 456                         next-level-cache = <&l2_0>;
 457                         #cooling-cells = <2>;
 458                         mediatek,cci = <&cci>;
 459                 };
 460
 461                 cpu4: cpu@400 {
 462                         device_type = "cpu";
 463                         compatible = "arm,cortex-a55";
 464                         reg = <0x400>;
 465                         enable-method = "psci";
 466                         clock-frequency = <2000000000>;
 467                         clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
 468                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 469                         clock-names = "cpu", "intermediate";
 470                         operating-points-v2 = <&cluster0_opp>;
 471                         dynamic-power-coefficient = <84>;
 472                         capacity-dmips-mhz = <382>;
 473                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 474                         i-cache-size = <32768>;
 475                         i-cache-line-size = <64>;
 476                         i-cache-sets = <128>;
 477                         d-cache-size = <32768>;
 478                         d-cache-line-size = <64>;
 479                         d-cache-sets = <128>;
 480                         next-level-cache = <&l2_0>;
 481                         #cooling-cells = <2>;
 482                         mediatek,cci = <&cci>;
 483                 };
 484
 485                 cpu5: cpu@500 {
 486                         device_type = "cpu";
 487                         compatible = "arm,cortex-a55";
 488                         reg = <0x500>;
 489                         enable-method = "psci";
 490                         clock-frequency = <2000000000>;
 491                         clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
 492                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 493                         clock-names = "cpu", "intermediate";
 494                         operating-points-v2 = <&cluster0_opp>;
 495                         dynamic-power-coefficient = <84>;
 496                         capacity-dmips-mhz = <382>;
 497                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 498                         i-cache-size = <32768>;
 499                         i-cache-line-size = <64>;
 500                         i-cache-sets = <128>;
 501                         d-cache-size = <32768>;
 502                         d-cache-line-size = <64>;
 503                         d-cache-sets = <128>;
 504                         next-level-cache = <&l2_0>;
 505                         #cooling-cells = <2>;
 506                         mediatek,cci = <&cci>;
 507                 };
 508
 509                 cpu6: cpu@600 {
 510                         device_type = "cpu";
 511                         compatible = "arm,cortex-a76";
 512                         reg = <0x600>;
 513                         enable-method = "psci";
 514                         clock-frequency = <2050000000>;
 515                         clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
 516                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 517                         clock-names = "cpu", "intermediate";
 518                         operating-points-v2 = <&cluster1_opp>;
 519                         dynamic-power-coefficient = <335>;
 520                         capacity-dmips-mhz = <1024>;
 521                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 522                         i-cache-size = <65536>;
 523                         i-cache-line-size = <64>;
 524                         i-cache-sets = <256>;
 525                         d-cache-size = <65536>;
 526                         d-cache-line-size = <64>;
 527                         d-cache-sets = <256>;
 528                         next-level-cache = <&l2_1>;
 529                         #cooling-cells = <2>;
 530                         mediatek,cci = <&cci>;
 531                 };
 532
 533                 cpu7: cpu@700 {
 534                         device_type = "cpu";
 535                         compatible = "arm,cortex-a76";
 536                         reg = <0x700>;
 537                         enable-method = "psci";
 538                         clock-frequency = <2050000000>;
 539                         clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
 540                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 541                         clock-names = "cpu", "intermediate";
 542                         operating-points-v2 = <&cluster1_opp>;
 543                         dynamic-power-coefficient = <335>;
 544                         capacity-dmips-mhz = <1024>;
 545                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 546                         i-cache-size = <65536>;
 547                         i-cache-line-size = <64>;
 548                         i-cache-sets = <256>;
 549                         d-cache-size = <65536>;
 550                         d-cache-line-size = <64>;
 551                         d-cache-sets = <256>;
 552                         next-level-cache = <&l2_1>;
 553                         #cooling-cells = <2>;
 554                         mediatek,cci = <&cci>;
 555                 };
 556
 557                 idle-states {
 558                         entry-method = "psci";
 559
 560                         cpu_ret_l: cpu-retention-l {
 561                                 compatible = "arm,idle-state";
 562                                 arm,psci-suspend-param = <0x00010001>;
 563                                 local-timer-stop;
 564                                 entry-latency-us = <50>;
 565                                 exit-latency-us = <100>;
 566                                 min-residency-us = <1600>;
 567                         };
 568
 569                         cpu_ret_b: cpu-retention-b {
 570                                 compatible = "arm,idle-state";
 571                                 arm,psci-suspend-param = <0x00010001>;
 572                                 local-timer-stop;
 573                                 entry-latency-us = <50>;
 574                                 exit-latency-us = <100>;
 575                                 min-residency-us = <1400>;
 576                         };
 577
 578                         cpu_off_l: cpu-off-l {
 579                                 compatible = "arm,idle-state";
 580                                 arm,psci-suspend-param = <0x01010001>;
 581                                 local-timer-stop;
 582                                 entry-latency-us = <100>;
 583                                 exit-latency-us = <250>;
 584                                 min-residency-us = <2100>;
 585                         };
 586
 587                         cpu_off_b: cpu-off-b {
 588                                 compatible = "arm,idle-state";
 589                                 arm,psci-suspend-param = <0x01010001>;
 590                                 local-timer-stop;
 591                                 entry-latency-us = <100>;
 592                                 exit-latency-us = <250>;
 593                                 min-residency-us = <1900>;
 594                         };
 595                 };
 596
 597                 l2_0: l2-cache0 {
 598                         compatible = "cache";
 599                         cache-level = <2>;
 600                         cache-size = <131072>;
 601                         cache-line-size = <64>;
 602                         cache-sets = <512>;
 603                         next-level-cache = <&l3_0>;
 604                         cache-unified;
 605                 };
 606
 607                 l2_1: l2-cache1 {
 608                         compatible = "cache";
 609                         cache-level = <2>;
 610                         cache-size = <262144>;
 611                         cache-line-size = <64>;
 612                         cache-sets = <512>;
 613                         next-level-cache = <&l3_0>;
 614                         cache-unified;
 615                 };
 616
 617                 l3_0: l3-cache {
 618                         compatible = "cache";
 619                         cache-level = <3>;
 620                         cache-size = <1048576>;
 621                         cache-line-size = <64>;
 622                         cache-sets = <1024>;
 623                         cache-unified;
 624                 };
 625         };
 626
 627         clk13m: fixed-factor-clock-13m {
 628                 compatible = "fixed-factor-clock";
 629                 #clock-cells = <0>;
 630                 clocks = <&clk26m>;
 631                 clock-div = <2>;
 632                 clock-mult = <1>;
 633                 clock-output-names = "clk13m";
 634         };
 635
 636         clk26m: oscillator-26m {
 637                 compatible = "fixed-clock";
 638                 #clock-cells = <0>;
 639                 clock-frequency = <26000000>;
 640                 clock-output-names = "clk26m";
 641         };
 642
 643         clk32k: oscillator-32k {
 644                 compatible = "fixed-clock";
 645                 #clock-cells = <0>;
 646                 clock-frequency = <32768>;
 647                 clock-output-names = "clk32k";
 648         };
 649
 650         gpu_opp_table: opp-table-gpu {
 651                 compatible = "operating-points-v2";
 652
 653                 opp-299000000 {
 654                         opp-hz = /bits/ 64 <299000000>;
 655                         opp-microvolt = <612500>;
 656                         opp-supported-hw = <0xff>;
 657                 };
 658
 659                 opp-332000000 {
 660                         opp-hz = /bits/ 64 <332000000>;
 661                         opp-microvolt = <625000>;
 662                         opp-supported-hw = <0xff>;
 663                 };
 664
 665                 opp-366000000 {
 666                         opp-hz = /bits/ 64 <366000000>;
 667                         opp-microvolt = <637500>;
 668                         opp-supported-hw = <0xff>;
 669                 };
 670
 671                 opp-400000000 {
 672                         opp-hz = /bits/ 64 <400000000>;
 673                         opp-microvolt = <643750>;
 674                         opp-supported-hw = <0xff>;
 675                 };
 676
 677                 opp-434000000 {
 678                         opp-hz = /bits/ 64 <434000000>;
 679                         opp-microvolt = <656250>;
 680                         opp-supported-hw = <0xff>;
 681                 };
 682
 683                 opp-484000000 {
 684                         opp-hz = /bits/ 64 <484000000>;
 685                         opp-microvolt = <668750>;
 686                         opp-supported-hw = <0xff>;
 687                 };
 688
 689                 opp-535000000 {
 690                         opp-hz = /bits/ 64 <535000000>;
 691                         opp-microvolt = <687500>;
 692                         opp-supported-hw = <0xff>;
 693                 };
 694
 695                 opp-586000000 {
 696                         opp-hz = /bits/ 64 <586000000>;
 697                         opp-microvolt = <700000>;
 698                         opp-supported-hw = <0xff>;
 699                 };
 700
 701                 opp-637000000 {
 702                         opp-hz = /bits/ 64 <637000000>;
 703                         opp-microvolt = <712500>;
 704                         opp-supported-hw = <0xff>;
 705                 };
 706
 707                 opp-690000000 {
 708                         opp-hz = /bits/ 64 <690000000>;
 709                         opp-microvolt = <737500>;
 710                         opp-supported-hw = <0xff>;
 711                 };
 712
 713                 opp-743000000 {
 714                         opp-hz = /bits/ 64 <743000000>;
 715                         opp-microvolt = <756250>;
 716                         opp-supported-hw = <0xff>;
 717                 };
 718
 719                 opp-796000000 {
 720                         opp-hz = /bits/ 64 <796000000>;
 721                         opp-microvolt = <781250>;
 722                         opp-supported-hw = <0xff>;
 723                 };
 724
 725                 opp-850000000 {
 726                         opp-hz = /bits/ 64 <850000000>;
 727                         opp-microvolt = <800000>;
 728                         opp-supported-hw = <0xff>;
 729                 };
 730
 731                 opp-900000000-3 {
 732                         opp-hz = /bits/ 64 <900000000>;
 733                         opp-microvolt = <850000>;
 734                         opp-supported-hw = <0x8>;
 735                 };
 736
 737                 opp-900000000-4 {
 738                         opp-hz = /bits/ 64 <900000000>;
 739                         opp-microvolt = <837500>;
 740                         opp-supported-hw = <0x10>;
 741                 };
 742
 743                 opp-900000000-5 {
 744                         opp-hz = /bits/ 64 <900000000>;
 745                         opp-microvolt = <825000>;
 746                         opp-supported-hw = <0x30>;
 747                 };
 748
 749                 opp-950000000-3 {
 750                         opp-hz = /bits/ 64 <950000000>;
 751                         opp-microvolt = <900000>;
 752                         opp-supported-hw = <0x8>;
 753                 };
 754
 755                 opp-950000000-4 {
 756                         opp-hz = /bits/ 64 <950000000>;
 757                         opp-microvolt = <875000>;
 758                         opp-supported-hw = <0x10>;
 759                 };
 760
 761                 opp-950000000-5 {
 762                         opp-hz = /bits/ 64 <950000000>;
 763                         opp-microvolt = <850000>;
 764                         opp-supported-hw = <0x30>;
 765                 };
 766
 767                 opp-1000000000-3 {
 768                         opp-hz = /bits/ 64 <1000000000>;
 769                         opp-microvolt = <950000>;
 770                         opp-supported-hw = <0x8>;
 771                 };
 772
 773                 opp-1000000000-4 {
 774                         opp-hz = /bits/ 64 <1000000000>;
 775                         opp-microvolt = <912500>;
 776                         opp-supported-hw = <0x10>;
 777                 };
 778
 779                 opp-1000000000-5 {
 780                         opp-hz = /bits/ 64 <1000000000>;
 781                         opp-microvolt = <875000>;
 782                         opp-supported-hw = <0x30>;
 783                 };
 784         };
 785
 786         pmu-a55 {
 787                 compatible = "arm,cortex-a55-pmu";
 788                 interrupt-parent = <&gic>;
 789                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 790         };
 791
 792         pmu-a76 {
 793                 compatible = "arm,cortex-a76-pmu";
 794                 interrupt-parent = <&gic>;
 795                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 796         };
 797
 798         psci {
 799                 compatible = "arm,psci-1.0";
 800                 method = "smc";
 801         };
 802
 803         timer {
 804                 compatible = "arm,armv8-timer";
 805                 interrupt-parent = <&gic>;
 806                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 807                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 808                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 809                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 810         };
 811
 812         soc {
 813                 #address-cells = <2>;
 814                 #size-cells = <2>;
 815                 compatible = "simple-bus";
 816                 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 817                 ranges;
 818
 819                 gic: interrupt-controller@c000000 {
 820                         compatible = "arm,gic-v3";
 821                         #interrupt-cells = <4>;
 822                         #redistributor-regions = <1>;
 823                         interrupt-parent = <&gic>;
 824                         interrupt-controller;
 825                         reg = <0 0x0c000000 0 0x40000>,
 826                               <0 0x0c040000 0 0x200000>;
 827                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 828
 829                         ppi-partitions {
 830                                 ppi_cluster0: interrupt-partition-0 {
 831                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
 832                                 };
 833
 834                                 ppi_cluster1: interrupt-partition-1 {
 835                                         affinity = <&cpu6 &cpu7>;
 836                                 };
 837                         };
 838                 };
 839
 840                 mcusys: syscon@c53a000 {
 841                         compatible = "mediatek,mt8186-mcusys", "syscon";
 842                         reg = <0 0xc53a000 0 0x1000>;
 843                         #clock-cells = <1>;
 844                 };
 845
 846                 topckgen: syscon@10000000 {
 847                         compatible = "mediatek,mt8186-topckgen", "syscon";
 848                         reg = <0 0x10000000 0 0x1000>;
 849                         #clock-cells = <1>;
 850                 };
 851
 852                 infracfg_ao: syscon@10001000 {
 853                         compatible = "mediatek,mt8186-infracfg_ao", "syscon";
 854                         reg = <0 0x10001000 0 0x1000>;
 855                         #clock-cells = <1>;
 856                         #reset-cells = <1>;
 857                 };
 858
 859                 pericfg: syscon@10003000 {
 860                         compatible = "mediatek,mt8186-pericfg", "syscon";
 861                         reg = <0 0x10003000 0 0x1000>;
 862                 };
 863
 864                 pio: pinctrl@10005000 {
 865                         compatible = "mediatek,mt8186-pinctrl";
 866                         reg = <0 0x10005000 0 0x1000>,
 867                               <0 0x10002000 0 0x0200>,
 868                               <0 0x10002200 0 0x0200>,
 869                               <0 0x10002400 0 0x0200>,
 870                               <0 0x10002600 0 0x0200>,
 871                               <0 0x10002a00 0 0x0200>,
 872                               <0 0x10002c00 0 0x0200>,
 873                               <0 0x1000b000 0 0x1000>;
 874                         reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
 875                                     "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
 876                         gpio-controller;
 877                         #gpio-cells = <2>;
 878                         gpio-ranges = <&pio 0 0 185>;
 879                         interrupt-controller;
 880                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
 881                         #interrupt-cells = <2>;
 882                 };
 883
 884                 scpsys: syscon@10006000 {
 885                         compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
 886                         reg = <0 0x10006000 0 0x1000>;
 887
 888                         /* System Power Manager */
 889                         spm: power-controller {
 890                                 compatible = "mediatek,mt8186-power-controller";
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 #power-domain-cells = <1>;
 894
 895                                 /* power domain of the SoC */
 896                                 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
 897                                         reg = <MT8186_POWER_DOMAIN_MFG0>;
 898                                         clocks = <&topckgen CLK_TOP_MFG>;
 899                                         clock-names = "mfg00";
 900                                         #address-cells = <1>;
 901                                         #size-cells = <0>;
 902                                         #power-domain-cells = <1>;
 903
 904                                         mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
 905                                                 reg = <MT8186_POWER_DOMAIN_MFG1>;
 906                                                 mediatek,infracfg = <&infracfg_ao>;
 907                                                 #address-cells = <1>;
 908                                                 #size-cells = <0>;
 909                                                 #power-domain-cells = <1>;
 910
 911                                                 power-domain@MT8186_POWER_DOMAIN_MFG2 {
 912                                                         reg = <MT8186_POWER_DOMAIN_MFG2>;
 913                                                         #power-domain-cells = <0>;
 914                                                 };
 915
 916                                                 power-domain@MT8186_POWER_DOMAIN_MFG3 {
 917                                                         reg = <MT8186_POWER_DOMAIN_MFG3>;
 918                                                         #power-domain-cells = <0>;
 919                                                 };
 920                                         };
 921                                 };
 922
 923                                 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
 924                                         reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
 925                                         clocks = <&topckgen CLK_TOP_SENINF>,
 926                                                  <&topckgen CLK_TOP_SENINF1>;
 927                                         clock-names = "subsys-csirx-top0",
 928                                                       "subsys-csirx-top1";
 929                                         #power-domain-cells = <0>;
 930                                 };
 931
 932                                 power-domain@MT8186_POWER_DOMAIN_SSUSB {
 933                                         reg = <MT8186_POWER_DOMAIN_SSUSB>;
 934                                         #power-domain-cells = <0>;
 935                                 };
 936
 937                                 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
 938                                         reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
 939                                         #power-domain-cells = <0>;
 940                                 };
 941
 942                                 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
 943                                         reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
 944                                         clocks = <&topckgen CLK_TOP_AUDIODSP>,
 945                                                  <&topckgen CLK_TOP_ADSP_BUS>;
 946                                         clock-names = "audioadsp",
 947                                                       "subsys-adsp-bus";
 948                                         #address-cells = <1>;
 949                                         #size-cells = <0>;
 950                                         #power-domain-cells = <1>;
 951
 952                                         power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
 953                                                 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
 954                                                 #address-cells = <1>;
 955                                                 #size-cells = <0>;
 956                                                 #power-domain-cells = <1>;
 957
 958                                                 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
 959                                                         reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
 960                                                         mediatek,infracfg = <&infracfg_ao>;
 961                                                         #power-domain-cells = <0>;
 962                                                 };
 963                                         };
 964                                 };
 965
 966                                 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
 967                                         reg = <MT8186_POWER_DOMAIN_CONN_ON>;
 968                                         mediatek,infracfg = <&infracfg_ao>;
 969                                         #power-domain-cells = <0>;
 970                                 };
 971
 972                                 power-domain@MT8186_POWER_DOMAIN_DIS {
 973                                         reg = <MT8186_POWER_DOMAIN_DIS>;
 974                                         clocks = <&topckgen CLK_TOP_DISP>,
 975                                                  <&topckgen CLK_TOP_MDP>,
 976                                                  <&mmsys CLK_MM_SMI_INFRA>,
 977                                                  <&mmsys CLK_MM_SMI_COMMON>,
 978                                                  <&mmsys CLK_MM_SMI_GALS>,
 979                                                  <&mmsys CLK_MM_SMI_IOMMU>;
 980                                         clock-names = "disp", "mdp",
 981                                                       "subsys-smi-infra",
 982                                                       "subsys-smi-common",
 983                                                       "subsys-smi-gals",
 984                                                       "subsys-smi-iommu";
 985                                         mediatek,infracfg = <&infracfg_ao>;
 986                                         #address-cells = <1>;
 987                                         #size-cells = <0>;
 988                                         #power-domain-cells = <1>;
 989
 990                                         power-domain@MT8186_POWER_DOMAIN_VDEC {
 991                                                 reg = <MT8186_POWER_DOMAIN_VDEC>;
 992                                                 clocks = <&topckgen CLK_TOP_VDEC>,
 993                                                          <&vdecsys CLK_VDEC_LARB1_CKEN>;
 994                                                 clock-names = "vdec0", "larb";
 995                                                 mediatek,infracfg = <&infracfg_ao>;
 996                                                 #power-domain-cells = <0>;
 997                                         };
 998
 999                                         power-domain@MT8186_POWER_DOMAIN_CAM {
1000                                                 reg = <MT8186_POWER_DOMAIN_CAM>;
1001                                                 clocks = <&topckgen CLK_TOP_SENINF>,
1002                                                          <&topckgen CLK_TOP_SENINF1>,
1003                                                          <&topckgen CLK_TOP_SENINF2>,
1004                                                          <&topckgen CLK_TOP_SENINF3>,
1005                                                          <&camsys CLK_CAM2MM_GALS>,
1006                                                          <&topckgen CLK_TOP_CAMTM>,
1007                                                          <&topckgen CLK_TOP_CAM>;
1008                                                 clock-names = "cam0", "cam1", "cam2",
1009                                                               "cam3", "gals",
1010                                                               "subsys-cam-tm",
1011                                                               "subsys-cam-top";
1012                                                 mediatek,infracfg = <&infracfg_ao>;
1013                                                 #address-cells = <1>;
1014                                                 #size-cells = <0>;
1015                                                 #power-domain-cells = <1>;
1016
1017                                                 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1018                                                         reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
1019                                                         #power-domain-cells = <0>;
1020                                                 };
1021
1022                                                 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1023                                                         reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
1024                                                         #power-domain-cells = <0>;
1025                                                 };
1026                                         };
1027
1028                                         power-domain@MT8186_POWER_DOMAIN_IMG {
1029                                                 reg = <MT8186_POWER_DOMAIN_IMG>;
1030                                                 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1031                                                          <&topckgen CLK_TOP_IMG1>;
1032                                                 clock-names = "gals", "subsys-img-top";
1033                                                 mediatek,infracfg = <&infracfg_ao>;
1034                                                 #address-cells = <1>;
1035                                                 #size-cells = <0>;
1036                                                 #power-domain-cells = <1>;
1037
1038                                                 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1039                                                         reg = <MT8186_POWER_DOMAIN_IMG2>;
1040                                                         #power-domain-cells = <0>;
1041                                                 };
1042                                         };
1043
1044                                         power-domain@MT8186_POWER_DOMAIN_IPE {
1045                                                 reg = <MT8186_POWER_DOMAIN_IPE>;
1046                                                 clocks = <&topckgen CLK_TOP_IPE>,
1047                                                          <&ipesys CLK_IPE_LARB19>,
1048                                                          <&ipesys CLK_IPE_LARB20>,
1049                                                          <&ipesys CLK_IPE_SMI_SUBCOM>,
1050                                                          <&ipesys CLK_IPE_GALS_IPE>;
1051                                                 clock-names = "subsys-ipe-top",
1052                                                               "subsys-ipe-larb0",
1053                                                               "subsys-ipe-larb1",
1054                                                               "subsys-ipe-smi",
1055                                                               "subsys-ipe-gals";
1056                                                 mediatek,infracfg = <&infracfg_ao>;
1057                                                 #power-domain-cells = <0>;
1058                                         };
1059
1060                                         power-domain@MT8186_POWER_DOMAIN_VENC {
1061                                                 reg = <MT8186_POWER_DOMAIN_VENC>;
1062                                                 clocks = <&topckgen CLK_TOP_VENC>,
1063                                                          <&vencsys CLK_VENC_CKE1_VENC>;
1064                                                 clock-names = "venc0", "larb";
1065                                                 mediatek,infracfg = <&infracfg_ao>;
1066                                                 #power-domain-cells = <0>;
1067                                         };
1068
1069                                         power-domain@MT8186_POWER_DOMAIN_WPE {
1070                                                 reg = <MT8186_POWER_DOMAIN_WPE>;
1071                                                 clocks = <&topckgen CLK_TOP_WPE>,
1072                                                          <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1073                                                          <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
1074                                                 clock-names = "wpe0",
1075                                                               "subsys-larb-ck",
1076                                                               "subsys-larb-pclk";
1077                                                 mediatek,infracfg = <&infracfg_ao>;
1078                                                 #power-domain-cells = <0>;
1079                                         };
1080                                 };
1081                         };
1082                 };
1083
1084                 watchdog: watchdog@10007000 {
1085                         compatible = "mediatek,mt8186-wdt";
1086                         mediatek,disable-extrst;
1087                         reg = <0 0x10007000 0 0x1000>;
1088                         #reset-cells = <1>;
1089                 };
1090
1091                 apmixedsys: syscon@1000c000 {
1092                         compatible = "mediatek,mt8186-apmixedsys", "syscon";
1093                         reg = <0 0x1000c000 0 0x1000>;
1094                         #clock-cells = <1>;
1095                 };
1096
1097                 pwrap: pwrap@1000d000 {
1098                         compatible = "mediatek,mt8186-pwrap", "syscon";
1099                         reg = <0 0x1000d000 0 0x1000>;
1100                         reg-names = "pwrap";
1101                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1102                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1103                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
1104                         clock-names = "spi", "wrap";
1105                 };
1106
1107                 spmi: spmi@10015000 {
1108                         compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1109                         reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
1110                         reg-names = "pmif", "spmimst";
1111                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1112                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
1113                                  <&topckgen CLK_TOP_SPMI_MST>;
1114                         clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1115                         assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1116                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1117                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
1118                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
1119                         status = "disabled";
1120                 };
1121
1122                 systimer: timer@10017000 {
1123                         compatible = "mediatek,mt8186-timer",
1124                                      "mediatek,mt6765-timer";
1125                         reg = <0 0x10017000 0 0x1000>;
1126                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
1127                         clocks = <&clk13m>;
1128                 };
1129
1130                 gce: mailbox@1022c000 {
1131                         compatible = "mediatek,mt8186-gce";
1132                         reg = <0 0X1022c000 0 0x4000>;
1133                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
1134                         clock-names = "gce";
1135                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1136                         #mbox-cells = <2>;
1137                 };
1138
1139                 scp: scp@10500000 {
1140                         compatible = "mediatek,mt8186-scp";
1141                         reg = <0 0x10500000 0 0x40000>,
1142                               <0 0x105c0000 0 0x19080>;
1143                         reg-names = "sram", "cfg";
1144                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1145                 };
1146
1147                 adsp: adsp@10680000 {
1148                         compatible = "mediatek,mt8186-dsp";
1149                         reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
1150                               <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
1151                         reg-names = "cfg", "sram", "sec", "bus";
1152                         clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
1153                         clock-names = "audiodsp", "adsp_bus";
1154                         assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1155                                           <&topckgen CLK_TOP_ADSP_BUS>;
1156                         assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1157                         mbox-names = "rx", "tx";
1158                         mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
1159                         power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1160                         status = "disabled";
1161                 };
1162
1163                 adsp_mailbox0: mailbox@10686000 {
1164                         compatible = "mediatek,mt8186-adsp-mbox";
1165                         #mbox-cells = <0>;
1166                         reg = <0 0x10686100 0 0x1000>;
1167                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
1168                 };
1169
1170                 adsp_mailbox1: mailbox@10687000 {
1171                         compatible = "mediatek,mt8186-adsp-mbox";
1172                         #mbox-cells = <0>;
1173                         reg = <0 0x10687100 0 0x1000>;
1174                         interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
1175                 };
1176
1177                 nor_flash: spi@11000000 {
1178                         compatible = "mediatek,mt8186-nor";
1179                         reg = <0 0x11000000 0 0x1000>;
1180                         clocks = <&topckgen CLK_TOP_SPINOR>,
1181                                  <&infracfg_ao CLK_INFRA_AO_SPINOR>,
1182                                  <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
1183                                  <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
1184                         clock-names = "spi", "sf", "axi", "axi_s";
1185                         assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1186                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1187                         interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
1188                         status = "disabled";
1189                 };
1190
1191                 auxadc: adc@11001000 {
1192                         compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1193                         reg = <0 0x11001000 0 0x1000>;
1194                         #io-channel-cells = <1>;
1195                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1196                         clock-names = "main";
1197                 };
1198
1199                 uart0: serial@11002000 {
1200                         compatible = "mediatek,mt8186-uart",
1201                                      "mediatek,mt6577-uart";
1202                         reg = <0 0x11002000 0 0x1000>;
1203                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1204                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1205                         clock-names = "baud", "bus";
1206                         status = "disabled";
1207                 };
1208
1209                 uart1: serial@11003000 {
1210                         compatible = "mediatek,mt8186-uart",
1211                                      "mediatek,mt6577-uart";
1212                         reg = <0 0x11003000 0 0x1000>;
1213                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1214                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1215                         clock-names = "baud", "bus";
1216                         status = "disabled";
1217                 };
1218
1219                 i2c0: i2c@11007000 {
1220                         compatible = "mediatek,mt8186-i2c";
1221                         reg = <0 0x11007000 0 0x1000>,
1222                               <0 0x10200100 0 0x100>;
1223                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
1224                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
1225                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1226                         clock-names = "main", "dma";
1227                         clock-div = <1>;
1228                         #address-cells = <1>;
1229                         #size-cells = <0>;
1230                         status = "disabled";
1231                 };
1232
1233                 i2c1: i2c@11008000 {
1234                         compatible = "mediatek,mt8186-i2c";
1235                         reg = <0 0x11008000 0 0x1000>,
1236                               <0 0x10200200 0 0x100>;
1237                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1238                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
1239                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1240                         clock-names = "main", "dma";
1241                         clock-div = <1>;
1242                         #address-cells = <1>;
1243                         #size-cells = <0>;
1244                         status = "disabled";
1245                 };
1246
1247                 i2c2: i2c@11009000 {
1248                         compatible = "mediatek,mt8186-i2c";
1249                         reg = <0 0x11009000 0 0x1000>,
1250                               <0 0x10200300 0 0x180>;
1251                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
1252                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
1253                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1254                         clock-names = "main", "dma";
1255                         clock-div = <1>;
1256                         #address-cells = <1>;
1257                         #size-cells = <0>;
1258                         status = "disabled";
1259                 };
1260
1261                 i2c3: i2c@1100f000 {
1262                         compatible = "mediatek,mt8186-i2c";
1263                         reg = <0 0x1100f000 0 0x1000>,
1264                               <0 0x10200480 0 0x100>;
1265                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1266                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
1267                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1268                         clock-names = "main", "dma";
1269                         clock-div = <1>;
1270                         #address-cells = <1>;
1271                         #size-cells = <0>;
1272                         status = "disabled";
1273                 };
1274
1275                 i2c4: i2c@11011000 {
1276                         compatible = "mediatek,mt8186-i2c";
1277                         reg = <0 0x11011000 0 0x1000>,
1278                               <0 0x10200580 0 0x180>;
1279                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
1280                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
1281                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1282                         clock-names = "main", "dma";
1283                         clock-div = <1>;
1284                         #address-cells = <1>;
1285                         #size-cells = <0>;
1286                         status = "disabled";
1287                 };
1288
1289                 i2c5: i2c@11016000 {
1290                         compatible = "mediatek,mt8186-i2c";
1291                         reg = <0 0x11016000 0 0x1000>,
1292                               <0 0x10200700 0 0x100>;
1293                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1294                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
1295                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1296                         clock-names = "main", "dma";
1297                         clock-div = <1>;
1298                         #address-cells = <1>;
1299                         #size-cells = <0>;
1300                         status = "disabled";
1301                 };
1302
1303                 i2c6: i2c@1100d000 {
1304                         compatible = "mediatek,mt8186-i2c";
1305                         reg = <0 0x1100d000 0 0x1000>,
1306                               <0 0x10200800 0 0x100>;
1307                         interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1308                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
1309                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1310                         clock-names = "main", "dma";
1311                         clock-div = <1>;
1312                         #address-cells = <1>;
1313                         #size-cells = <0>;
1314                         status = "disabled";
1315                 };
1316
1317                 i2c7: i2c@11004000 {
1318                         compatible = "mediatek,mt8186-i2c";
1319                         reg = <0 0x11004000 0 0x1000>,
1320                               <0 0x10200900 0 0x180>;
1321                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
1322                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
1323                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1324                         clock-names = "main", "dma";
1325                         clock-div = <1>;
1326                         #address-cells = <1>;
1327                         #size-cells = <0>;
1328                         status = "disabled";
1329                 };
1330
1331                 i2c8: i2c@11005000 {
1332                         compatible = "mediatek,mt8186-i2c";
1333                         reg = <0 0x11005000 0 0x1000>,
1334                               <0 0x10200A80 0 0x180>;
1335                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1336                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
1337                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1338                         clock-names = "main", "dma";
1339                         clock-div = <1>;
1340                         #address-cells = <1>;
1341                         #size-cells = <0>;
1342                         status = "disabled";
1343                 };
1344
1345                 spi0: spi@1100a000 {
1346                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1347                         #address-cells = <1>;
1348                         #size-cells = <0>;
1349                         reg = <0 0x1100a000 0 0x1000>;
1350                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
1351                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1352                                  <&topckgen CLK_TOP_SPI>,
1353                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
1354                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1355                         status = "disabled";
1356                 };
1357
1358                 pwm0: pwm@1100e000 {
1359                         compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1360                         reg = <0 0x1100e000 0 0x1000>;
1361                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1362                         #pwm-cells = <2>;
1363                         clocks = <&topckgen CLK_TOP_DISP_PWM>,
1364                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1365                         clock-names = "main", "mm";
1366                         status = "disabled";
1367                 };
1368
1369                 spi1: spi@11010000 {
1370                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1371                         #address-cells = <1>;
1372                         #size-cells = <0>;
1373                         reg = <0 0x11010000 0 0x1000>;
1374                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
1375                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1376                                  <&topckgen CLK_TOP_SPI>,
1377                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
1378                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1379                         status = "disabled";
1380                 };
1381
1382                 spi2: spi@11012000 {
1383                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1384                         #address-cells = <1>;
1385                         #size-cells = <0>;
1386                         reg = <0 0x11012000 0 0x1000>;
1387                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
1388                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1389                                  <&topckgen CLK_TOP_SPI>,
1390                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
1391                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1392                         status = "disabled";
1393                 };
1394
1395                 spi3: spi@11013000 {
1396                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1397                         #address-cells = <1>;
1398                         #size-cells = <0>;
1399                         reg = <0 0x11013000 0 0x1000>;
1400                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1401                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1402                                  <&topckgen CLK_TOP_SPI>,
1403                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
1404                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1405                         status = "disabled";
1406                 };
1407
1408                 spi4: spi@11014000 {
1409                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1410                         #address-cells = <1>;
1411                         #size-cells = <0>;
1412                         reg = <0 0x11014000 0 0x1000>;
1413                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1414                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1415                                  <&topckgen CLK_TOP_SPI>,
1416                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
1417                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1418                         status = "disabled";
1419                 };
1420
1421                 spi5: spi@11015000 {
1422                         compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1423                         #address-cells = <1>;
1424                         #size-cells = <0>;
1425                         reg = <0 0x11015000 0 0x1000>;
1426                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1427                         clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1428                                  <&topckgen CLK_TOP_SPI>,
1429                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
1430                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1431                         status = "disabled";
1432                 };
1433
1434                 imp_iic_wrap: clock-controller@11017000 {
1435                         compatible = "mediatek,mt8186-imp_iic_wrap";
1436                         reg = <0 0x11017000 0 0x1000>;
1437                         #clock-cells = <1>;
1438                 };
1439
1440                 uart2: serial@11018000 {
1441                         compatible = "mediatek,mt8186-uart",
1442                                      "mediatek,mt6577-uart";
1443                         reg = <0 0x11018000 0 0x1000>;
1444                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
1445                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1446                         clock-names = "baud", "bus";
1447                         status = "disabled";
1448                 };
1449
1450                 i2c9: i2c@11019000 {
1451                         compatible = "mediatek,mt8186-i2c";
1452                         reg = <0 0x11019000 0 0x1000>,
1453                               <0 0x10200c00 0 0x180>;
1454                         interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
1455                         clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
1456                                  <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1457                         clock-names = "main", "dma";
1458                         clock-div = <1>;
1459                         #address-cells = <1>;
1460                         #size-cells = <0>;
1461                         status = "disabled";
1462                 };
1463
1464                 afe: audio-controller@11210000 {
1465                         compatible = "mediatek,mt8186-sound";
1466                         reg = <0 0x11210000 0 0x2000>;
1467                         clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
1468                                  <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
1469                                  <&topckgen CLK_TOP_AUDIO>,
1470                                  <&topckgen CLK_TOP_AUD_INTBUS>,
1471                                  <&topckgen CLK_TOP_MAINPLL_D2_D4>,
1472                                  <&topckgen CLK_TOP_AUD_1>,
1473                                  <&apmixedsys CLK_APMIXED_APLL1>,
1474                                  <&topckgen CLK_TOP_AUD_2>,
1475                                  <&apmixedsys CLK_APMIXED_APLL2>,
1476                                  <&topckgen CLK_TOP_AUD_ENGEN1>,
1477                                  <&topckgen CLK_TOP_APLL1_D8>,
1478                                  <&topckgen CLK_TOP_AUD_ENGEN2>,
1479                                  <&topckgen CLK_TOP_APLL2_D8>,
1480                                  <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
1481                                  <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
1482                                  <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
1483                                  <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
1484                                  <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
1485                                  <&topckgen CLK_TOP_APLL12_CK_DIV0>,
1486                                  <&topckgen CLK_TOP_APLL12_CK_DIV1>,
1487                                  <&topckgen CLK_TOP_APLL12_CK_DIV2>,
1488                                  <&topckgen CLK_TOP_APLL12_CK_DIV4>,
1489                                  <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
1490                                  <&topckgen CLK_TOP_AUDIO_H>,
1491                                  <&clk26m>;
1492                         clock-names = "aud_infra_clk",
1493                                       "mtkaif_26m_clk",
1494                                       "top_mux_audio",
1495                                       "top_mux_audio_int",
1496                                       "top_mainpll_d2_d4",
1497                                       "top_mux_aud_1",
1498                                       "top_apll1_ck",
1499                                       "top_mux_aud_2",
1500                                       "top_apll2_ck",
1501                                       "top_mux_aud_eng1",
1502                                       "top_apll1_d8",
1503                                       "top_mux_aud_eng2",
1504                                       "top_apll2_d8",
1505                                       "top_i2s0_m_sel",
1506                                       "top_i2s1_m_sel",
1507                                       "top_i2s2_m_sel",
1508                                       "top_i2s4_m_sel",
1509                                       "top_tdm_m_sel",
1510                                       "top_apll12_div0",
1511                                       "top_apll12_div1",
1512                                       "top_apll12_div2",
1513                                       "top_apll12_div4",
1514                                       "top_apll12_div_tdm",
1515                                       "top_mux_audio_h",
1516                                       "top_clk26m_clk";
1517                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1518                         mediatek,apmixedsys = <&apmixedsys>;
1519                         mediatek,infracfg = <&infracfg_ao>;
1520                         mediatek,topckgen = <&topckgen>;
1521                         resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
1522                         reset-names = "audiosys";
1523                         status = "disabled";
1524                 };
1525
1526                 ssusb0: usb@11201000 {
1527                         compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1528                         reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1529                         reg-names = "mac", "ippc";
1530                         clocks = <&topckgen CLK_TOP_USB_TOP>,
1531                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
1532                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
1533                                  <&infracfg_ao CLK_INFRA_AO_ICUSB>;
1534                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
1535                         interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
1536                         phys = <&u2port0 PHY_TYPE_USB2>;
1537                         power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1538                         #address-cells = <2>;
1539                         #size-cells = <2>;
1540                         ranges;
1541                         status = "disabled";
1542
1543                         usb_host0: usb@11200000 {
1544                                 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1545                                 reg = <0 0x11200000 0 0x1000>;
1546                                 reg-names = "mac";
1547                                 clocks = <&topckgen CLK_TOP_USB_TOP>,
1548                                          <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
1549                                          <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
1550                                          <&infracfg_ao CLK_INFRA_AO_ICUSB>,
1551                                          <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
1552                                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1553                                 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
1554                                 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1555                                 wakeup-source;
1556                                 status = "disabled";
1557                         };
1558                 };
1559
1560                 mmc0: mmc@11230000 {
1561                         compatible = "mediatek,mt8186-mmc",
1562                                      "mediatek,mt8183-mmc";
1563                         reg = <0 0x11230000 0 0x10000>,
1564                               <0 0x11cd0000 0 0x1000>;
1565                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
1566                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1567                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
1568                                  <&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
1569                         clock-names = "source", "hclk", "source_cg", "crypto";
1570                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
1571                         assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1572                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1573                         status = "disabled";
1574                 };
1575
1576                 mmc1: mmc@11240000 {
1577                         compatible = "mediatek,mt8186-mmc",
1578                                      "mediatek,mt8183-mmc";
1579                         reg = <0 0x11240000 0 0x1000>,
1580                               <0 0x11c90000 0 0x1000>;
1581                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
1582                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1583                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1584                         clock-names = "source", "hclk", "source_cg";
1585                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1586                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1587                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1588                         status = "disabled";
1589                 };
1590
1591                 ssusb1: usb@11281000 {
1592                         compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1593                         reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
1594                         reg-names = "mac", "ippc";
1595                         clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
1596                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
1597                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
1598                                  <&clk26m>;
1599                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
1600                         interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
1601                         phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
1602                         power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1603                         #address-cells = <2>;
1604                         #size-cells = <2>;
1605                         ranges;
1606                         status = "disabled";
1607
1608                         usb_host1: usb@11280000 {
1609                                 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1610                                 reg = <0 0x11280000 0 0x1000>;
1611                                 reg-names = "mac";
1612                                 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
1613                                          <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
1614                                          <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
1615                                          <&clk26m>,
1616                                          <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
1617                                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1618                                 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1619                                 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1620                                 wakeup-source;
1621                                 status = "disabled";
1622                         };
1623                 };
1624
1625                 u3phy0: t-phy@11c80000 {
1626                         compatible = "mediatek,mt8186-tphy",
1627                                      "mediatek,generic-tphy-v2";
1628                         #address-cells = <1>;
1629                         #size-cells = <1>;
1630                         ranges = <0x0 0x0 0x11c80000 0x1000>;
1631                         status = "disabled";
1632
1633                         u2port1: usb-phy@0 {
1634                                 reg = <0x0 0x700>;
1635                                 clocks = <&clk26m>;
1636                                 clock-names = "ref";
1637                                 #phy-cells = <1>;
1638                         };
1639
1640                         u3port1: usb-phy@700 {
1641                                 reg = <0x700 0x900>;
1642                                 clocks = <&clk26m>;
1643                                 clock-names = "ref";
1644                                 #phy-cells = <1>;
1645                         };
1646                 };
1647
1648                 u3phy1: t-phy@11ca0000 {
1649                         compatible = "mediatek,mt8186-tphy",
1650                                      "mediatek,generic-tphy-v2";
1651                         #address-cells = <1>;
1652                         #size-cells = <1>;
1653                         ranges = <0x0 0x0 0x11ca0000 0x1000>;
1654                         status = "disabled";
1655
1656                         u2port0: usb-phy@0 {
1657                                 reg = <0x0 0x700>;
1658                                 clocks = <&clk26m>;
1659                                 clock-names = "ref";
1660                                 #phy-cells = <1>;
1661                                 mediatek,discth = <0x8>;
1662                         };
1663                 };
1664
1665                 efuse: efuse@11cb0000 {
1666                         compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1667                         reg = <0 0x11cb0000 0 0x1000>;
1668                         #address-cells = <1>;
1669                         #size-cells = <1>;
1670
1671                         gpu_speedbin: gpu-speedbin@59c {
1672                                 reg = <0x59c 0x4>;
1673                                 bits = <0 3>;
1674                         };
1675                 };
1676
1677                 mipi_tx0: dsi-phy@11cc0000 {
1678                         compatible = "mediatek,mt8183-mipi-tx";
1679                         reg = <0 0x11cc0000 0 0x1000>;
1680                         clocks = <&clk26m>;
1681                         #clock-cells = <0>;
1682                         #phy-cells = <0>;
1683                         clock-output-names = "mipi_tx0_pll";
1684                         status = "disabled";
1685                 };
1686
1687                 mfgsys: clock-controller@13000000 {
1688                         compatible = "mediatek,mt8186-mfgsys";
1689                         reg = <0 0x13000000 0 0x1000>;
1690                         #clock-cells = <1>;
1691                 };
1692
1693                 gpu: gpu@13040000 {
1694                         compatible = "mediatek,mt8186-mali",
1695                                      "arm,mali-bifrost";
1696                         reg = <0 0x13040000 0 0x4000>;
1697
1698                         clocks = <&mfgsys CLK_MFG_BG3D>;
1699                         interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1700                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1701                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1702                         interrupt-names = "job", "mmu", "gpu";
1703                         power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1704                                         <&spm MT8186_POWER_DOMAIN_MFG3>;
1705                         power-domain-names = "core0", "core1";
1706                         #cooling-cells = <2>;
1707                         nvmem-cells = <&gpu_speedbin>;
1708                         nvmem-cell-names = "speed-bin";
1709                         operating-points-v2 = <&gpu_opp_table>;
1710                         dynamic-power-coefficient = <4687>;
1711                         status = "disabled";
1712                 };
1713
1714                 mmsys: syscon@14000000 {
1715                         compatible = "mediatek,mt8186-mmsys", "syscon";
1716                         reg = <0 0x14000000 0 0x1000>;
1717                         #clock-cells = <1>;
1718                         #reset-cells = <1>;
1719                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1720                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1721                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1722                 };
1723
1724                 mutex: mutex@14001000 {
1725                         compatible = "mediatek,mt8186-disp-mutex";
1726                         reg = <0 0x14001000 0 0x1000>;
1727                         clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1728                         interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
1729                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1730                         mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1731                                               <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1732                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1733                 };
1734
1735                 smi_common: smi@14002000 {
1736                         compatible = "mediatek,mt8186-smi-common";
1737                         reg = <0 0x14002000 0 0x1000>;
1738                         clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1739                                  <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1740                         clock-names = "apb", "smi", "gals0", "gals1";
1741                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1742                 };
1743
1744                 larb0: smi@14003000 {
1745                         compatible = "mediatek,mt8186-smi-larb";
1746                         reg = <0 0x14003000 0 0x1000>;
1747                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1748                                  <&mmsys CLK_MM_SMI_COMMON>;
1749                         clock-names = "apb", "smi";
1750                         mediatek,larb-id = <0>;
1751                         mediatek,smi = <&smi_common>;
1752                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1753                 };
1754
1755                 larb1: smi@14004000 {
1756                         compatible = "mediatek,mt8186-smi-larb";
1757                         reg = <0 0x14004000 0 0x1000>;
1758                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1759                                  <&mmsys CLK_MM_SMI_COMMON>;
1760                         clock-names = "apb", "smi";
1761                         mediatek,larb-id = <1>;
1762                         mediatek,smi = <&smi_common>;
1763                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1764                 };
1765
1766                 ovl0: ovl@14005000 {
1767                         compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1768                         reg = <0 0x14005000 0 0x1000>;
1769                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1770                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
1771                         iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
1772                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1773                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1774                 };
1775
1776                 ovl_2l0: ovl@14006000 {
1777                         compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1778                         reg = <0 0x14006000 0 0x1000>;
1779                         clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1780                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
1781                         iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
1782                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1783                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1784                 };
1785
1786                 rdma0: rdma@14007000 {
1787                         compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1788                         reg = <0 0x14007000 0 0x1000>;
1789                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1790                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
1791                         iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
1792                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1793                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1794                 };
1795
1796                 color: color@14009000 {
1797                         compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1798                         reg = <0 0x14009000 0 0x1000>;
1799                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1800                         interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
1801                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1802                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1803                 };
1804
1805                 dpi: dpi@1400a000 {
1806                         compatible = "mediatek,mt8186-dpi";
1807                         reg = <0 0x1400a000 0 0x1000>;
1808                         clocks = <&topckgen CLK_TOP_DPI>,
1809                                  <&mmsys CLK_MM_DISP_DPI>,
1810                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1811                         clock-names = "pixel", "engine", "pll";
1812                         assigned-clocks = <&topckgen CLK_TOP_DPI>;
1813                         assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1814                         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1815                         status = "disabled";
1816
1817                         port {
1818                                 dpi_out: endpoint { };
1819                         };
1820                 };
1821
1822                 ccorr: ccorr@1400b000 {
1823                         compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1824                         reg = <0 0x1400b000 0 0x1000>;
1825                         clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1826                         interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
1827                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1828                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1829                 };
1830
1831                 aal: aal@1400c000 {
1832                         compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1833                         reg = <0 0x1400c000 0 0x1000>;
1834                         clocks = <&mmsys CLK_MM_DISP_AAL0>;
1835                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
1836                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1837                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1838                 };
1839
1840                 gamma: gamma@1400d000 {
1841                         compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1842                         reg = <0 0x1400d000 0 0x1000>;
1843                         clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1844                         interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
1845                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1846                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1847                 };
1848
1849                 postmask: postmask@1400e000 {
1850                         compatible = "mediatek,mt8186-disp-postmask",
1851                                      "mediatek,mt8192-disp-postmask";
1852                         reg = <0 0x1400e000 0 0x1000>;
1853                         clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1854                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
1855                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1856                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1857                 };
1858
1859                 dither: dither@1400f000 {
1860                         compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1861                         reg = <0 0x1400f000 0 0x1000>;
1862                         clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1863                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
1864                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1865                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1866                 };
1867
1868                 dsi0: dsi@14013000 {
1869                         compatible = "mediatek,mt8186-dsi";
1870                         reg = <0 0x14013000 0 0x1000>;
1871                         clocks = <&mmsys CLK_MM_DSI0>,
1872                                  <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1873                                  <&mipi_tx0>;
1874                         clock-names = "engine", "digital", "hs";
1875                         interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1876                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1877                         resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1878                         phys = <&mipi_tx0>;
1879                         phy-names = "dphy";
1880                         status = "disabled";
1881
1882                         port {
1883                                 dsi_out: endpoint { };
1884                         };
1885                 };
1886
1887                 iommu_mm: iommu@14016000 {
1888                         compatible = "mediatek,mt8186-iommu-mm";
1889                         reg = <0 0x14016000 0 0x1000>;
1890                         clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1891                         clock-names = "bclk";
1892                         interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1893                         mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
1894                                           &larb7 &larb8 &larb9 &larb11
1895                                           &larb13 &larb14 &larb16 &larb17
1896                                           &larb19 &larb20>;
1897                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1898                         #iommu-cells = <1>;
1899                 };
1900
1901                 rdma1: rdma@1401f000 {
1902                         compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1903                         reg = <0 0x1401f000 0 0x1000>;
1904                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1905                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
1906                         iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
1907                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1908                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1909                 };
1910
1911                 wpesys: clock-controller@14020000 {
1912                         compatible = "mediatek,mt8186-wpesys";
1913                         reg = <0 0x14020000 0 0x1000>;
1914                         #clock-cells = <1>;
1915                 };
1916
1917                 larb8: smi@14023000 {
1918                         compatible = "mediatek,mt8186-smi-larb";
1919                         reg = <0 0x14023000 0 0x1000>;
1920                         clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1921                                  <&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
1922                         clock-names = "apb", "smi";
1923                         mediatek,larb-id = <8>;
1924                         mediatek,smi = <&smi_common>;
1925                         power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1926                 };
1927
1928                 imgsys1: clock-controller@15020000 {
1929                         compatible = "mediatek,mt8186-imgsys1";
1930                         reg = <0 0x15020000 0 0x1000>;
1931                         #clock-cells = <1>;
1932                 };
1933
1934                 larb9: smi@1502e000 {
1935                         compatible = "mediatek,mt8186-smi-larb";
1936                         reg = <0 0x1502e000 0 0x1000>;
1937                         clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1938                                  <&imgsys1 CLK_IMG1_LARB9_IMG1>;
1939                         clock-names = "apb", "smi";
1940                         mediatek,larb-id = <9>;
1941                         mediatek,smi = <&smi_common>;
1942                         power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1943                 };
1944
1945                 imgsys2: clock-controller@15820000 {
1946                         compatible = "mediatek,mt8186-imgsys2";
1947                         reg = <0 0x15820000 0 0x1000>;
1948                         #clock-cells = <1>;
1949                 };
1950
1951                 larb11: smi@1582e000 {
1952                         compatible = "mediatek,mt8186-smi-larb";
1953                         reg = <0 0x1582e000 0 0x1000>;
1954                         clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
1955                                  <&imgsys2 CLK_IMG2_LARB9_IMG2>;
1956                         clock-names = "apb", "smi";
1957                         mediatek,larb-id = <11>;
1958                         mediatek,smi = <&smi_common>;
1959                         power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
1960                 };
1961
1962                 larb4: smi@1602e000 {
1963                         compatible = "mediatek,mt8186-smi-larb";
1964                         reg = <0 0x1602e000 0 0x1000>;
1965                         clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
1966                                  <&vdecsys CLK_VDEC_LARB1_CKEN>;
1967                         clock-names = "apb", "smi";
1968                         mediatek,larb-id = <4>;
1969                         mediatek,smi = <&smi_common>;
1970                         power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
1971                 };
1972
1973                 vdecsys: clock-controller@1602f000 {
1974                         compatible = "mediatek,mt8186-vdecsys";
1975                         reg = <0 0x1602f000 0 0x1000>;
1976                         #clock-cells = <1>;
1977                 };
1978
1979                 vencsys: clock-controller@17000000 {
1980                         compatible = "mediatek,mt8186-vencsys";
1981                         reg = <0 0x17000000 0 0x1000>;
1982                         #clock-cells = <1>;
1983                 };
1984
1985                 larb7: smi@17010000 {
1986                         compatible = "mediatek,mt8186-smi-larb";
1987                         reg = <0 0x17010000 0 0x1000>;
1988                         clocks = <&vencsys CLK_VENC_CKE1_VENC>,
1989                                  <&vencsys CLK_VENC_CKE1_VENC>;
1990                         clock-names = "apb", "smi";
1991                         mediatek,larb-id = <7>;
1992                         mediatek,smi = <&smi_common>;
1993                         power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
1994                 };
1995
1996                 camsys: clock-controller@1a000000 {
1997                         compatible = "mediatek,mt8186-camsys";
1998                         reg = <0 0x1a000000 0 0x1000>;
1999                         #clock-cells = <1>;
2000                 };
2001
2002                 larb13: smi@1a001000 {
2003                         compatible = "mediatek,mt8186-smi-larb";
2004                         reg = <0 0x1a001000 0 0x1000>;
2005                         clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
2006                         clock-names = "apb", "smi";
2007                         mediatek,larb-id = <13>;
2008                         mediatek,smi = <&smi_common>;
2009                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2010                 };
2011
2012                 larb14: smi@1a002000 {
2013                         compatible = "mediatek,mt8186-smi-larb";
2014                         reg = <0 0x1a002000 0 0x1000>;
2015                         clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
2016                         clock-names = "apb", "smi";
2017                         mediatek,larb-id = <14>;
2018                         mediatek,smi = <&smi_common>;
2019                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2020                 };
2021
2022                 larb16: smi@1a00f000 {
2023                         compatible = "mediatek,mt8186-smi-larb";
2024                         reg = <0 0x1a00f000 0 0x1000>;
2025                         clocks = <&camsys CLK_CAM_LARB14>,
2026                                  <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
2027                         clock-names = "apb", "smi";
2028                         mediatek,larb-id = <16>;
2029                         mediatek,smi = <&smi_common>;
2030                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2031                 };
2032
2033                 larb17: smi@1a010000 {
2034                         compatible = "mediatek,mt8186-smi-larb";
2035                         reg = <0 0x1a010000 0 0x1000>;
2036                         clocks = <&camsys CLK_CAM_LARB13>,
2037                                  <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
2038                         clock-names = "apb", "smi";
2039                         mediatek,larb-id = <17>;
2040                         mediatek,smi = <&smi_common>;
2041                         power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2042                 };
2043
2044                 camsys_rawa: clock-controller@1a04f000 {
2045                         compatible = "mediatek,mt8186-camsys_rawa";
2046                         reg = <0 0x1a04f000 0 0x1000>;
2047                         #clock-cells = <1>;
2048                 };
2049
2050                 camsys_rawb: clock-controller@1a06f000 {
2051                         compatible = "mediatek,mt8186-camsys_rawb";
2052                         reg = <0 0x1a06f000 0 0x1000>;
2053                         #clock-cells = <1>;
2054                 };
2055
2056                 mdpsys: clock-controller@1b000000 {
2057                         compatible = "mediatek,mt8186-mdpsys";
2058                         reg = <0 0x1b000000 0 0x1000>;
2059                         #clock-cells = <1>;
2060                 };
2061
2062                 larb2: smi@1b002000 {
2063                         compatible = "mediatek,mt8186-smi-larb";
2064                         reg = <0 0x1b002000 0 0x1000>;
2065                         clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
2066                         clock-names = "apb", "smi";
2067                         mediatek,larb-id = <2>;
2068                         mediatek,smi = <&smi_common>;
2069                         power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2070                 };
2071
2072                 ipesys: clock-controller@1c000000 {
2073                         compatible = "mediatek,mt8186-ipesys";
2074                         reg = <0 0x1c000000 0 0x1000>;
2075                         #clock-cells = <1>;
2076                 };
2077
2078                 larb20: smi@1c00f000 {
2079                         compatible = "mediatek,mt8186-smi-larb";
2080                         reg = <0 0x1c00f000 0 0x1000>;
2081                         clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
2082                         clock-names = "apb", "smi";
2083                         mediatek,larb-id = <20>;
2084                         mediatek,smi = <&smi_common>;
2085                         power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2086                 };
2087
2088                 larb19: smi@1c10f000 {
2089                         compatible = "mediatek,mt8186-smi-larb";
2090                         reg = <0 0x1c10f000 0 0x1000>;
2091                         clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
2092                         clock-names = "apb", "smi";
2093                         mediatek,larb-id = <19>;
2094                         mediatek,smi = <&smi_common>;
2095                         power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2096                 };
2097         };
2098 };