arch/arm64/boot/dts/mediatek/mt8183.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Ben Ho <ben.ho@mediatek.com>
   5  *         Erin Lo <erin.lo@mediatek.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt8183-clk.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "mt8183-pinfunc.h"
  12
  13 / {
  14         compatible = "mediatek,mt8183";
  15         interrupt-parent = <&sysirq>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 i2c4 = &i2c4;
  25                 i2c5 = &i2c5;
  26                 i2c6 = &i2c6;
  27                 i2c7 = &i2c7;
  28                 i2c8 = &i2c8;
  29                 i2c9 = &i2c9;
  30                 i2c10 = &i2c10;
  31                 i2c11 = &i2c11;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu-map {
  39                         cluster0 {
  40                                 core0 {
  41                                         cpu = <&cpu0>;
  42                                 };
  43                                 core1 {
  44                                         cpu = <&cpu1>;
  45                                 };
  46                                 core2 {
  47                                         cpu = <&cpu2>;
  48                                 };
  49                                 core3 {
  50                                         cpu = <&cpu3>;
  51                                 };
  52                         };
  53
  54                         cluster1 {
  55                                 core0 {
  56                                         cpu = <&cpu4>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu5>;
  60                                 };
  61                                 core2 {
  62                                         cpu = <&cpu6>;
  63                                 };
  64                                 core3 {
  65                                         cpu = <&cpu7>;
  66                                 };
  67                         };
  68                 };
  69
  70                 cpu0: cpu@0 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x000>;
  74                         enable-method = "psci";
  75                         capacity-dmips-mhz = <741>;
  76                 };
  77
  78                 cpu1: cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53";
  81                         reg = <0x001>;
  82                         enable-method = "psci";
  83                         capacity-dmips-mhz = <741>;
  84                 };
  85
  86                 cpu2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x002>;
  90                         enable-method = "psci";
  91                         capacity-dmips-mhz = <741>;
  92                 };
  93
  94                 cpu3: cpu@3 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x003>;
  98                         enable-method = "psci";
  99                         capacity-dmips-mhz = <741>;
 100                 };
 101
 102                 cpu4: cpu@100 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a73";
 105                         reg = <0x100>;
 106                         enable-method = "psci";
 107                         capacity-dmips-mhz = <1024>;
 108                 };
 109
 110                 cpu5: cpu@101 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a73";
 113                         reg = <0x101>;
 114                         enable-method = "psci";
 115                         capacity-dmips-mhz = <1024>;
 116                 };
 117
 118                 cpu6: cpu@102 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a73";
 121                         reg = <0x102>;
 122                         enable-method = "psci";
 123                         capacity-dmips-mhz = <1024>;
 124                 };
 125
 126                 cpu7: cpu@103 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a73";
 129                         reg = <0x103>;
 130                         enable-method = "psci";
 131                         capacity-dmips-mhz = <1024>;
 132                 };
 133         };
 134
 135         pmu-a53 {
 136                 compatible = "arm,cortex-a53-pmu";
 137                 interrupt-parent = <&gic>;
 138                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 139         };
 140
 141         pmu-a73 {
 142                 compatible = "arm,cortex-a73-pmu";
 143                 interrupt-parent = <&gic>;
 144                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 145         };
 146
 147         psci {
 148                 compatible      = "arm,psci-1.0";
 149                 method          = "smc";
 150         };
 151
 152         clk26m: oscillator {
 153                 compatible = "fixed-clock";
 154                 #clock-cells = <0>;
 155                 clock-frequency = <26000000>;
 156                 clock-output-names = "clk26m";
 157         };
 158
 159         timer {
 160                 compatible = "arm,armv8-timer";
 161                 interrupt-parent = <&gic>;
 162                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 163                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 164                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 165                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 166         };
 167
 168         soc {
 169                 #address-cells = <2>;
 170                 #size-cells = <2>;
 171                 compatible = "simple-bus";
 172                 ranges;
 173
 174                 soc_data: soc_data@8000000 {
 175                         compatible = "mediatek,mt8183-efuse",
 176                                      "mediatek,efuse";
 177                         reg = <0 0x08000000 0 0x0010>;
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180                         status = "disabled";
 181                 };
 182
 183                 gic: interrupt-controller@c000000 {
 184                         compatible = "arm,gic-v3";
 185                         #interrupt-cells = <4>;
 186                         interrupt-parent = <&gic>;
 187                         interrupt-controller;
 188                         reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 189                               <0 0x0c100000 0 0x200000>, /* GICR */
 190                               <0 0x0c400000 0 0x2000>,   /* GICC */
 191                               <0 0x0c410000 0 0x1000>,   /* GICH */
 192                               <0 0x0c420000 0 0x2000>;   /* GICV */
 193
 194                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 195                         ppi-partitions {
 196                                 ppi_cluster0: interrupt-partition-0 {
 197                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 198                                 };
 199                                 ppi_cluster1: interrupt-partition-1 {
 200                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 201                                 };
 202                         };
 203                 };
 204
 205                 mcucfg: syscon@c530000 {
 206                         compatible = "mediatek,mt8183-mcucfg", "syscon";
 207                         reg = <0 0x0c530000 0 0x1000>;
 208                         #clock-cells = <1>;
 209                 };
 210
 211                 sysirq: interrupt-controller@c530a80 {
 212                         compatible = "mediatek,mt8183-sysirq",
 213                                      "mediatek,mt6577-sysirq";
 214                         interrupt-controller;
 215                         #interrupt-cells = <3>;
 216                         interrupt-parent = <&gic>;
 217                         reg = <0 0x0c530a80 0 0x50>;
 218                 };
 219
 220                 topckgen: syscon@10000000 {
 221                         compatible = "mediatek,mt8183-topckgen", "syscon";
 222                         reg = <0 0x10000000 0 0x1000>;
 223                         #clock-cells = <1>;
 224                 };
 225
 226                 infracfg: syscon@10001000 {
 227                         compatible = "mediatek,mt8183-infracfg", "syscon";
 228                         reg = <0 0x10001000 0 0x1000>;
 229                         #clock-cells = <1>;
 230                 };
 231
 232                 pio: pinctrl@10005000 {
 233                         compatible = "mediatek,mt8183-pinctrl";
 234                         reg = <0 0x10005000 0 0x1000>,
 235                               <0 0x11f20000 0 0x1000>,
 236                               <0 0x11e80000 0 0x1000>,
 237                               <0 0x11e70000 0 0x1000>,
 238                               <0 0x11e90000 0 0x1000>,
 239                               <0 0x11d30000 0 0x1000>,
 240                               <0 0x11d20000 0 0x1000>,
 241                               <0 0x11c50000 0 0x1000>,
 242                               <0 0x11f30000 0 0x1000>,
 243                               <0 0x1000b000 0 0x1000>;
 244                         reg-names = "iocfg0", "iocfg1", "iocfg2",
 245                                     "iocfg3", "iocfg4", "iocfg5",
 246                                     "iocfg6", "iocfg7", "iocfg8",
 247                                     "eint";
 248                         gpio-controller;
 249                         #gpio-cells = <2>;
 250                         gpio-ranges = <&pio 0 0 192>;
 251                         interrupt-controller;
 252                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 253                         #interrupt-cells = <2>;
 254                 };
 255
 256                 apmixedsys: syscon@1000c000 {
 257                         compatible = "mediatek,mt8183-apmixedsys", "syscon";
 258                         reg = <0 0x1000c000 0 0x1000>;
 259                         #clock-cells = <1>;
 260                 };
 261
 262                 pwrap: pwrap@1000d000 {
 263                         compatible = "mediatek,mt8183-pwrap";
 264                         reg = <0 0x1000d000 0 0x1000>;
 265                         reg-names = "pwrap";
 266                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 267                         clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
 268                                  <&infracfg CLK_INFRA_PMIC_AP>;
 269                         clock-names = "spi", "wrap";
 270                 };
 271
 272                 auxadc: auxadc@11001000 {
 273                         compatible = "mediatek,mt8183-auxadc",
 274                                      "mediatek,mt8173-auxadc";
 275                         reg = <0 0x11001000 0 0x1000>;
 276                         clocks = <&infracfg CLK_INFRA_AUXADC>;
 277                         clock-names = "main";
 278                         #io-channel-cells = <1>;
 279                         status = "disabled";
 280                 };
 281
 282                 uart0: serial@11002000 {
 283                         compatible = "mediatek,mt8183-uart",
 284                                      "mediatek,mt6577-uart";
 285                         reg = <0 0x11002000 0 0x1000>;
 286                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 287                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 288                         clock-names = "baud", "bus";
 289                         status = "disabled";
 290                 };
 291
 292                 uart1: serial@11003000 {
 293                         compatible = "mediatek,mt8183-uart",
 294                                      "mediatek,mt6577-uart";
 295                         reg = <0 0x11003000 0 0x1000>;
 296                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 297                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 298                         clock-names = "baud", "bus";
 299                         status = "disabled";
 300                 };
 301
 302                 uart2: serial@11004000 {
 303                         compatible = "mediatek,mt8183-uart",
 304                                      "mediatek,mt6577-uart";
 305                         reg = <0 0x11004000 0 0x1000>;
 306                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 307                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
 308                         clock-names = "baud", "bus";
 309                         status = "disabled";
 310                 };
 311
 312                 i2c6: i2c@11005000 {
 313                         compatible = "mediatek,mt8183-i2c";
 314                         reg = <0 0x11005000 0 0x1000>,
 315                               <0 0x11000600 0 0x80>;
 316                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 317                         clocks = <&infracfg CLK_INFRA_I2C6>,
 318                                  <&infracfg CLK_INFRA_AP_DMA>;
 319                         clock-names = "main", "dma";
 320                         clock-div = <1>;
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         status = "disabled";
 324                 };
 325
 326                 i2c0: i2c@11007000 {
 327                         compatible = "mediatek,mt8183-i2c";
 328                         reg = <0 0x11007000 0 0x1000>,
 329                               <0 0x11000080 0 0x80>;
 330                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 331                         clocks = <&infracfg CLK_INFRA_I2C0>,
 332                                  <&infracfg CLK_INFRA_AP_DMA>;
 333                         clock-names = "main", "dma";
 334                         clock-div = <1>;
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         status = "disabled";
 338                 };
 339
 340                 i2c4: i2c@11008000 {
 341                         compatible = "mediatek,mt8183-i2c";
 342                         reg = <0 0x11008000 0 0x1000>,
 343                               <0 0x11000100 0 0x80>;
 344                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 345                         clocks = <&infracfg CLK_INFRA_I2C1>,
 346                                  <&infracfg CLK_INFRA_AP_DMA>,
 347                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
 348                         clock-names = "main", "dma","arb";
 349                         clock-div = <1>;
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         status = "disabled";
 353                 };
 354
 355                 i2c2: i2c@11009000 {
 356                         compatible = "mediatek,mt8183-i2c";
 357                         reg = <0 0x11009000 0 0x1000>,
 358                               <0 0x11000280 0 0x80>;
 359                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 360                         clocks = <&infracfg CLK_INFRA_I2C2>,
 361                                  <&infracfg CLK_INFRA_AP_DMA>,
 362                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
 363                         clock-names = "main", "dma", "arb";
 364                         clock-div = <1>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         status = "disabled";
 368                 };
 369
 370                 spi0: spi@1100a000 {
 371                         compatible = "mediatek,mt8183-spi";
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         reg = <0 0x1100a000 0 0x1000>;
 375                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
 376                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 377                                  <&topckgen CLK_TOP_MUX_SPI>,
 378                                  <&infracfg CLK_INFRA_SPI0>;
 379                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 380                         status = "disabled";
 381                 };
 382
 383                 i2c3: i2c@1100f000 {
 384                         compatible = "mediatek,mt8183-i2c";
 385                         reg = <0 0x1100f000 0 0x1000>,
 386                               <0 0x11000400 0 0x80>;
 387                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 388                         clocks = <&infracfg CLK_INFRA_I2C3>,
 389                                  <&infracfg CLK_INFRA_AP_DMA>;
 390                         clock-names = "main", "dma";
 391                         clock-div = <1>;
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         status = "disabled";
 395                 };
 396
 397                 spi1: spi@11010000 {
 398                         compatible = "mediatek,mt8183-spi";
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         reg = <0 0x11010000 0 0x1000>;
 402                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
 403                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 404                                  <&topckgen CLK_TOP_MUX_SPI>,
 405                                  <&infracfg CLK_INFRA_SPI1>;
 406                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 407                         status = "disabled";
 408                 };
 409
 410                 i2c1: i2c@11011000 {
 411                         compatible = "mediatek,mt8183-i2c";
 412                         reg = <0 0x11011000 0 0x1000>,
 413                               <0 0x11000480 0 0x80>;
 414                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 415                         clocks = <&infracfg CLK_INFRA_I2C4>,
 416                                  <&infracfg CLK_INFRA_AP_DMA>;
 417                         clock-names = "main", "dma";
 418                         clock-div = <1>;
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         status = "disabled";
 422                 };
 423
 424                 spi2: spi@11012000 {
 425                         compatible = "mediatek,mt8183-spi";
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         reg = <0 0x11012000 0 0x1000>;
 429                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 430                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 431                                  <&topckgen CLK_TOP_MUX_SPI>,
 432                                  <&infracfg CLK_INFRA_SPI2>;
 433                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 434                         status = "disabled";
 435                 };
 436
 437                 spi3: spi@11013000 {
 438                         compatible = "mediatek,mt8183-spi";
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         reg = <0 0x11013000 0 0x1000>;
 442                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
 443                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 444                                  <&topckgen CLK_TOP_MUX_SPI>,
 445                                  <&infracfg CLK_INFRA_SPI3>;
 446                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 447                         status = "disabled";
 448                 };
 449
 450                 i2c9: i2c@11014000 {
 451                         compatible = "mediatek,mt8183-i2c";
 452                         reg = <0 0x11014000 0 0x1000>,
 453                               <0 0x11000180 0 0x80>;
 454                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
 455                         clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
 456                                  <&infracfg CLK_INFRA_AP_DMA>,
 457                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
 458                         clock-names = "main", "dma", "arb";
 459                         clock-div = <1>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         status = "disabled";
 463                 };
 464
 465                 i2c10: i2c@11015000 {
 466                         compatible = "mediatek,mt8183-i2c";
 467                         reg = <0 0x11015000 0 0x1000>,
 468                               <0 0x11000300 0 0x80>;
 469                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 470                         clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
 471                                  <&infracfg CLK_INFRA_AP_DMA>,
 472                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
 473                         clock-names = "main", "dma", "arb";
 474                         clock-div = <1>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         status = "disabled";
 478                 };
 479
 480                 i2c5: i2c@11016000 {
 481                         compatible = "mediatek,mt8183-i2c";
 482                         reg = <0 0x11016000 0 0x1000>,
 483                               <0 0x11000500 0 0x80>;
 484                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 485                         clocks = <&infracfg CLK_INFRA_I2C5>,
 486                                  <&infracfg CLK_INFRA_AP_DMA>,
 487                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
 488                         clock-names = "main", "dma", "arb";
 489                         clock-div = <1>;
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                         status = "disabled";
 493                 };
 494
 495                 i2c11: i2c@11017000 {
 496                         compatible = "mediatek,mt8183-i2c";
 497                         reg = <0 0x11017000 0 0x1000>,
 498                               <0 0x11000580 0 0x80>;
 499                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
 500                         clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
 501                                  <&infracfg CLK_INFRA_AP_DMA>,
 502                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
 503                         clock-names = "main", "dma", "arb";
 504                         clock-div = <1>;
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         status = "disabled";
 508                 };
 509
 510                 spi4: spi@11018000 {
 511                         compatible = "mediatek,mt8183-spi";
 512                         #address-cells = <1>;
 513                         #size-cells = <0>;
 514                         reg = <0 0x11018000 0 0x1000>;
 515                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
 516                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 517                                  <&topckgen CLK_TOP_MUX_SPI>,
 518                                  <&infracfg CLK_INFRA_SPI4>;
 519                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 520                         status = "disabled";
 521                 };
 522
 523                 spi5: spi@11019000 {
 524                         compatible = "mediatek,mt8183-spi";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         reg = <0 0x11019000 0 0x1000>;
 528                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 529                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 530                                  <&topckgen CLK_TOP_MUX_SPI>,
 531                                  <&infracfg CLK_INFRA_SPI5>;
 532                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 533                         status = "disabled";
 534                 };
 535
 536                 i2c7: i2c@1101a000 {
 537                         compatible = "mediatek,mt8183-i2c";
 538                         reg = <0 0x1101a000 0 0x1000>,
 539                               <0 0x11000680 0 0x80>;
 540                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
 541                         clocks = <&infracfg CLK_INFRA_I2C7>,
 542                                  <&infracfg CLK_INFRA_AP_DMA>;
 543                         clock-names = "main", "dma";
 544                         clock-div = <1>;
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         status = "disabled";
 548                 };
 549
 550                 i2c8: i2c@1101b000 {
 551                         compatible = "mediatek,mt8183-i2c";
 552                         reg = <0 0x1101b000 0 0x1000>,
 553                               <0 0x11000700 0 0x80>;
 554                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 555                         clocks = <&infracfg CLK_INFRA_I2C8>,
 556                                  <&infracfg CLK_INFRA_AP_DMA>;
 557                         clock-names = "main", "dma";
 558                         clock-div = <1>;
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         status = "disabled";
 562                 };
 563
 564                 audiosys: syscon@11220000 {
 565                         compatible = "mediatek,mt8183-audiosys", "syscon";
 566                         reg = <0 0x11220000 0 0x1000>;
 567                         #clock-cells = <1>;
 568                 };
 569
 570                 efuse: efuse@11f10000 {
 571                         compatible = "mediatek,mt8183-efuse",
 572                                      "mediatek,efuse";
 573                         reg = <0 0x11f10000 0 0x1000>;
 574                 };
 575
 576                 mfgcfg: syscon@13000000 {
 577                         compatible = "mediatek,mt8183-mfgcfg", "syscon";
 578                         reg = <0 0x13000000 0 0x1000>;
 579                         #clock-cells = <1>;
 580                 };
 581
 582                 mmsys: syscon@14000000 {
 583                         compatible = "mediatek,mt8183-mmsys", "syscon";
 584                         reg = <0 0x14000000 0 0x1000>;
 585                         #clock-cells = <1>;
 586                 };
 587
 588                 imgsys: syscon@15020000 {
 589                         compatible = "mediatek,mt8183-imgsys", "syscon";
 590                         reg = <0 0x15020000 0 0x1000>;
 591                         #clock-cells = <1>;
 592                 };
 593
 594                 vdecsys: syscon@16000000 {
 595                         compatible = "mediatek,mt8183-vdecsys", "syscon";
 596                         reg = <0 0x16000000 0 0x1000>;
 597                         #clock-cells = <1>;
 598                 };
 599
 600                 vencsys: syscon@17000000 {
 601                         compatible = "mediatek,mt8183-vencsys", "syscon";
 602                         reg = <0 0x17000000 0 0x1000>;
 603                         #clock-cells = <1>;
 604                 };
 605
 606                 ipu_conn: syscon@19000000 {
 607                         compatible = "mediatek,mt8183-ipu_conn", "syscon";
 608                         reg = <0 0x19000000 0 0x1000>;
 609                         #clock-cells = <1>;
 610                 };
 611
 612                 ipu_adl: syscon@19010000 {
 613                         compatible = "mediatek,mt8183-ipu_adl", "syscon";
 614                         reg = <0 0x19010000 0 0x1000>;
 615                         #clock-cells = <1>;
 616                 };
 617
 618                 ipu_core0: syscon@19180000 {
 619                         compatible = "mediatek,mt8183-ipu_core0", "syscon";
 620                         reg = <0 0x19180000 0 0x1000>;
 621                         #clock-cells = <1>;
 622                 };
 623
 624                 ipu_core1: syscon@19280000 {
 625                         compatible = "mediatek,mt8183-ipu_core1", "syscon";
 626                         reg = <0 0x19280000 0 0x1000>;
 627                         #clock-cells = <1>;
 628                 };
 629
 630                 camsys: syscon@1a000000 {
 631                         compatible = "mediatek,mt8183-camsys", "syscon";
 632                         reg = <0 0x1a000000 0 0x1000>;
 633                         #clock-cells = <1>;
 634                 };
 635         };
 636 };