1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
10 #include "mt6358.dtsi"
13 model = "MediaTek MT8183 evaluation board";
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
22 device_type = "memory";
23 reg = <0 0x40000000 0 0x80000000>;
27 stdout-path = "serial0:921600n8";
34 scp_mem_reserved: memory@50000000 {
35 compatible = "shared-dma-pool";
36 reg = <0 0x50000000 0 0x2900000>;
42 compatible = "murata,ncp03wf104";
43 pullup-uv = <1800000>;
44 pullup-ohm = <390000>;
46 io-channels = <&auxadc 0>;
55 mali-supply = <&mt6358_vgpu_reg>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins_0>;
62 clock-frequency = <100000>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&i2c_pins_1>;
69 clock-frequency = <100000>;
73 pinctrl-names = "default";
74 pinctrl-0 = <&i2c_pins_2>;
76 clock-frequency = <100000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&i2c_pins_3>;
83 clock-frequency = <100000>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c_pins_4>;
90 clock-frequency = <1000000>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c_pins_5>;
97 clock-frequency = <1000000>;
102 pinctrl-names = "default", "state_uhs";
103 pinctrl-0 = <&mmc0_pins_default>;
104 pinctrl-1 = <&mmc0_pins_uhs>;
106 max-frequency = <200000000>;
113 hs400-ds-delay = <0x12814>;
114 vmmc-supply = <&mt6358_vemc_reg>;
115 vqmmc-supply = <&mt6358_vio18_reg>;
116 assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
117 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
123 pinctrl-names = "default", "state_uhs";
124 pinctrl-0 = <&mmc1_pins_default>;
125 pinctrl-1 = <&mmc1_pins_uhs>;
127 max-frequency = <200000000>;
134 vmmc-supply = <&mt6358_vmch_reg>;
135 vqmmc-supply = <&mt6358_vmc_reg>;
136 keep-power-in-suspend;
142 regulator-min-microvolt = <625000>;
143 regulator-max-microvolt = <900000>;
145 regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
146 regulator-coupled-max-spread = <100000>;
149 &mt6358_vsram_gpu_reg {
150 regulator-min-microvolt = <850000>;
151 regulator-max-microvolt = <1000000>;
153 regulator-coupled-with = <&mt6358_vgpu_reg>;
154 regulator-coupled-max-spread = <100000>;
160 pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
161 <PINMUX_GPIO83__FUNC_SCL0>;
162 mediatek,pull-up-adv = <3>;
163 mediatek,drive-strength-adv = <00>;
169 pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
170 <PINMUX_GPIO84__FUNC_SCL1>;
171 mediatek,pull-up-adv = <3>;
172 mediatek,drive-strength-adv = <00>;
178 pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
179 <PINMUX_GPIO104__FUNC_SDA2>;
180 mediatek,pull-up-adv = <3>;
181 mediatek,drive-strength-adv = <00>;
187 pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
188 <PINMUX_GPIO51__FUNC_SDA3>;
189 mediatek,pull-up-adv = <3>;
190 mediatek,drive-strength-adv = <00>;
196 pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
197 <PINMUX_GPIO106__FUNC_SDA4>;
198 mediatek,pull-up-adv = <3>;
199 mediatek,drive-strength-adv = <00>;
205 pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
206 <PINMUX_GPIO49__FUNC_SDA5>;
207 mediatek,pull-up-adv = <3>;
208 mediatek,drive-strength-adv = <00>;
214 pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
215 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
216 <PINMUX_GPIO87__FUNC_SPI0_MO>,
217 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
222 mmc0_pins_default: mmc0default {
224 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
225 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
226 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
227 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
228 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
229 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
230 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
231 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
232 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
238 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
243 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
248 mmc0_pins_uhs: mmc0 {
250 pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
251 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
252 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
253 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
254 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
255 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
256 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
257 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
258 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
260 drive-strength = <MTK_DRIVE_10mA>;
261 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
265 pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
266 drive-strength = <MTK_DRIVE_10mA>;
267 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
271 pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
272 drive-strength = <MTK_DRIVE_10mA>;
273 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
277 pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
278 drive-strength = <MTK_DRIVE_10mA>;
283 mmc1_pins_default: mmc1default {
285 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
286 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
287 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
288 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
289 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
295 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
301 pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
302 <PINMUX_GPIO166__FUNC_GPIO166>;
307 mmc1_pins_uhs: mmc1 {
309 pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
310 <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
311 <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
312 <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
313 <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
314 drive-strength = <MTK_DRIVE_6mA>;
316 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
320 pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
321 drive-strength = <MTK_DRIVE_6mA>;
322 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
329 pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
330 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
331 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
332 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
339 pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
340 <PINMUX_GPIO1__FUNC_SPI2_MO>,
341 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
342 <PINMUX_GPIO94__FUNC_SPI2_MI>;
349 pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
350 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
351 <PINMUX_GPIO23__FUNC_SPI3_MO>,
352 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
359 pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
360 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
361 <PINMUX_GPIO19__FUNC_SPI4_MO>,
362 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
369 pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
370 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
371 <PINMUX_GPIO15__FUNC_SPI5_MO>,
372 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
379 pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
385 domain-supply = <&mt6358_vgpu_reg>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&spi_pins_0>;
391 mediatek,pad-select = <0>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&spi_pins_1>;
398 mediatek,pad-select = <0>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&spi_pins_2>;
405 mediatek,pad-select = <0>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&spi_pins_3>;
412 mediatek,pad-select = <0>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&spi_pins_4>;
419 mediatek,pad-select = <0>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&spi_pins_5>;
426 mediatek,pad-select = <0>;
432 proc-supply = <&mt6358_vproc12_reg>;
436 proc-supply = <&mt6358_vproc12_reg>;
440 proc-supply = <&mt6358_vproc12_reg>;
444 proc-supply = <&mt6358_vproc12_reg>;
448 proc-supply = <&mt6358_vproc12_reg>;
452 proc-supply = <&mt6358_vproc11_reg>;
456 proc-supply = <&mt6358_vproc11_reg>;
460 proc-supply = <&mt6358_vproc11_reg>;
464 proc-supply = <&mt6358_vproc11_reg>;
473 pinctrl-0 = <&pwm_pins_1>;
474 pinctrl-names = "default";