2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/power/mt8173-power.h>
18 #include <dt-bindings/reset-controller/mt8173-resets.h>
19 #include "mt8173-pinfunc.h"
22 compatible = "mediatek,mt8173";
23 interrupt-parent = <&sysirq>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
62 compatible = "arm,cortex-a53";
64 enable-method = "psci";
65 cpu-idle-states = <&CPU_SLEEP_0>;
70 compatible = "arm,cortex-a57";
72 enable-method = "psci";
73 cpu-idle-states = <&CPU_SLEEP_0>;
79 compatible = "arm,cortex-a57";
81 enable-method = "psci";
82 cpu-idle-states = <&CPU_SLEEP_0>;
86 entry-method = "psci";
88 CPU_SLEEP_0: cpu-sleep-0 {
89 compatible = "arm,idle-state";
91 entry-latency-us = <639>;
92 exit-latency-us = <680>;
93 min-residency-us = <1088>;
94 arm,psci-suspend-param = <0x0010000>;
100 compatible = "arm,psci";
102 cpu_suspend = <0x84000001>;
103 cpu_off = <0x84000002>;
104 cpu_on = <0x84000003>;
107 clk26m: oscillator@0 {
108 compatible = "fixed-clock";
110 clock-frequency = <26000000>;
111 clock-output-names = "clk26m";
114 clk32k: oscillator@1 {
115 compatible = "fixed-clock";
117 clock-frequency = <32000>;
118 clock-output-names = "clk32k";
121 cpum_ck: oscillator@2 {
122 compatible = "fixed-clock";
124 clock-frequency = <0>;
125 clock-output-names = "cpum_ck";
129 compatible = "arm,armv8-timer";
130 interrupt-parent = <&gic>;
131 interrupts = <GIC_PPI 13
132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
142 #address-cells = <2>;
144 compatible = "simple-bus";
147 topckgen: clock-controller@10000000 {
148 compatible = "mediatek,mt8173-topckgen";
149 reg = <0 0x10000000 0 0x1000>;
153 infracfg: power-controller@10001000 {
154 compatible = "mediatek,mt8173-infracfg", "syscon";
155 reg = <0 0x10001000 0 0x1000>;
160 pericfg: power-controller@10003000 {
161 compatible = "mediatek,mt8173-pericfg", "syscon";
162 reg = <0 0x10003000 0 0x1000>;
167 syscfg_pctl_a: syscfg_pctl_a@10005000 {
168 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
169 reg = <0 0x10005000 0 0x1000>;
172 pio: pinctrl@0x10005000 {
173 compatible = "mediatek,mt8173-pinctrl";
174 reg = <0 0x1000b000 0 0x1000>;
175 mediatek,pctl-regmap = <&syscfg_pctl_a>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
187 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
188 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
195 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
196 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
203 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
204 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
211 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
212 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
219 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
220 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
227 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
228 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
234 scpsys: scpsys@10006000 {
235 compatible = "mediatek,mt8173-scpsys";
236 #power-domain-cells = <1>;
237 reg = <0 0x10006000 0 0x1000>;
239 <&topckgen CLK_TOP_MM_SEL>,
240 <&topckgen CLK_TOP_VENC_SEL>,
241 <&topckgen CLK_TOP_VENC_LT_SEL>;
242 clock-names = "mfg", "mm", "venc", "venc_lt";
243 infracfg = <&infracfg>;
246 watchdog: watchdog@10007000 {
247 compatible = "mediatek,mt8173-wdt",
248 "mediatek,mt6589-wdt";
249 reg = <0 0x10007000 0 0x100>;
252 pwrap: pwrap@1000d000 {
253 compatible = "mediatek,mt8173-pwrap";
254 reg = <0 0x1000d000 0 0x1000>;
256 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
257 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
258 reset-names = "pwrap";
259 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
260 clock-names = "spi", "wrap";
263 sysirq: intpol-controller@10200620 {
264 compatible = "mediatek,mt8173-sysirq",
265 "mediatek,mt6577-sysirq";
266 interrupt-controller;
267 #interrupt-cells = <3>;
268 interrupt-parent = <&gic>;
269 reg = <0 0x10200620 0 0x20>;
272 apmixedsys: clock-controller@10209000 {
273 compatible = "mediatek,mt8173-apmixedsys";
274 reg = <0 0x10209000 0 0x1000>;
278 gic: interrupt-controller@10220000 {
279 compatible = "arm,gic-400";
280 #interrupt-cells = <3>;
281 interrupt-parent = <&gic>;
282 interrupt-controller;
283 reg = <0 0x10221000 0 0x1000>,
284 <0 0x10222000 0 0x2000>,
285 <0 0x10224000 0 0x2000>,
286 <0 0x10226000 0 0x2000>;
287 interrupts = <GIC_PPI 9
288 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
291 uart0: serial@11002000 {
292 compatible = "mediatek,mt8173-uart",
293 "mediatek,mt6577-uart";
294 reg = <0 0x11002000 0 0x400>;
295 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
296 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
297 clock-names = "baud", "bus";
301 uart1: serial@11003000 {
302 compatible = "mediatek,mt8173-uart",
303 "mediatek,mt6577-uart";
304 reg = <0 0x11003000 0 0x400>;
305 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
306 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
307 clock-names = "baud", "bus";
311 uart2: serial@11004000 {
312 compatible = "mediatek,mt8173-uart",
313 "mediatek,mt6577-uart";
314 reg = <0 0x11004000 0 0x400>;
315 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
316 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
317 clock-names = "baud", "bus";
321 uart3: serial@11005000 {
322 compatible = "mediatek,mt8173-uart",
323 "mediatek,mt6577-uart";
324 reg = <0 0x11005000 0 0x400>;
325 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
326 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
327 clock-names = "baud", "bus";
332 compatible = "mediatek,mt8173-i2c";
333 reg = <0 0x11007000 0 0x70>,
334 <0 0x11000100 0 0x80>;
335 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
337 clocks = <&pericfg CLK_PERI_I2C0>,
338 <&pericfg CLK_PERI_AP_DMA>;
339 clock-names = "main", "dma";
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c0_pins_a>;
342 #address-cells = <1>;
348 compatible = "mediatek,mt8173-i2c";
349 reg = <0 0x11008000 0 0x70>,
350 <0 0x11000180 0 0x80>;
351 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
353 clocks = <&pericfg CLK_PERI_I2C1>,
354 <&pericfg CLK_PERI_AP_DMA>;
355 clock-names = "main", "dma";
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c1_pins_a>;
358 #address-cells = <1>;
364 compatible = "mediatek,mt8173-i2c";
365 reg = <0 0x11009000 0 0x70>,
366 <0 0x11000200 0 0x80>;
367 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
369 clocks = <&pericfg CLK_PERI_I2C2>,
370 <&pericfg CLK_PERI_AP_DMA>;
371 clock-names = "main", "dma";
372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c2_pins_a>;
374 #address-cells = <1>;
380 compatible = "mediatek,mt8173-spi";
381 #address-cells = <1>;
383 reg = <0 0x1100a000 0 0x1000>;
384 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
385 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
386 <&topckgen CLK_TOP_SPI_SEL>,
387 <&pericfg CLK_PERI_SPI0>;
388 clock-names = "parent-clk", "sel-clk", "spi-clk";
393 compatible = "mediatek,mt8173-i2c";
394 reg = <0 0x11010000 0 0x70>,
395 <0 0x11000280 0 0x80>;
396 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
398 clocks = <&pericfg CLK_PERI_I2C3>,
399 <&pericfg CLK_PERI_AP_DMA>;
400 clock-names = "main", "dma";
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c3_pins_a>;
403 #address-cells = <1>;
409 compatible = "mediatek,mt8173-i2c";
410 reg = <0 0x11011000 0 0x70>,
411 <0 0x11000300 0 0x80>;
412 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
414 clocks = <&pericfg CLK_PERI_I2C4>,
415 <&pericfg CLK_PERI_AP_DMA>;
416 clock-names = "main", "dma";
417 pinctrl-names = "default";
418 pinctrl-0 = <&i2c4_pins_a>;
419 #address-cells = <1>;
425 compatible = "mediatek,mt8173-i2c";
426 reg = <0 0x11013000 0 0x70>,
427 <0 0x11000080 0 0x80>;
428 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
430 clocks = <&pericfg CLK_PERI_I2C6>,
431 <&pericfg CLK_PERI_AP_DMA>;
432 clock-names = "main", "dma";
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2c6_pins_a>;
435 #address-cells = <1>;
440 afe: audio-controller@11220000 {
441 compatible = "mediatek,mt8173-afe-pcm";
442 reg = <0 0x11220000 0 0x1000>;
443 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
444 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
445 clocks = <&infracfg CLK_INFRA_AUDIO>,
446 <&topckgen CLK_TOP_AUDIO_SEL>,
447 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
448 <&topckgen CLK_TOP_APLL1_DIV0>,
449 <&topckgen CLK_TOP_APLL2_DIV0>,
450 <&topckgen CLK_TOP_I2S0_M_SEL>,
451 <&topckgen CLK_TOP_I2S1_M_SEL>,
452 <&topckgen CLK_TOP_I2S2_M_SEL>,
453 <&topckgen CLK_TOP_I2S3_M_SEL>,
454 <&topckgen CLK_TOP_I2S3_B_SEL>;
455 clock-names = "infra_sys_audio_clk",
457 "top_pdn_aud_intbus",
465 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
466 <&topckgen CLK_TOP_AUD_2_SEL>;
467 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
468 <&topckgen CLK_TOP_APLL2>;
472 compatible = "mediatek,mt8173-mmc",
473 "mediatek,mt8135-mmc";
474 reg = <0 0x11230000 0 0x1000>;
475 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
476 clocks = <&pericfg CLK_PERI_MSDC30_0>,
477 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
478 clock-names = "source", "hclk";
483 compatible = "mediatek,mt8173-mmc",
484 "mediatek,mt8135-mmc";
485 reg = <0 0x11240000 0 0x1000>;
486 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
487 clocks = <&pericfg CLK_PERI_MSDC30_1>,
488 <&topckgen CLK_TOP_AXI_SEL>;
489 clock-names = "source", "hclk";
494 compatible = "mediatek,mt8173-mmc",
495 "mediatek,mt8135-mmc";
496 reg = <0 0x11250000 0 0x1000>;
497 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
498 clocks = <&pericfg CLK_PERI_MSDC30_2>,
499 <&topckgen CLK_TOP_AXI_SEL>;
500 clock-names = "source", "hclk";
505 compatible = "mediatek,mt8173-mmc",
506 "mediatek,mt8135-mmc";
507 reg = <0 0x11260000 0 0x1000>;
508 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
509 clocks = <&pericfg CLK_PERI_MSDC30_3>,
510 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
511 clock-names = "source", "hclk";
515 mmsys: clock-controller@14000000 {
516 compatible = "mediatek,mt8173-mmsys", "syscon";
517 reg = <0 0x14000000 0 0x1000>;
521 imgsys: clock-controller@15000000 {
522 compatible = "mediatek,mt8173-imgsys", "syscon";
523 reg = <0 0x15000000 0 0x1000>;
527 vdecsys: clock-controller@16000000 {
528 compatible = "mediatek,mt8173-vdecsys", "syscon";
529 reg = <0 0x16000000 0 0x1000>;
533 vencsys: clock-controller@18000000 {
534 compatible = "mediatek,mt8173-vencsys", "syscon";
535 reg = <0 0x18000000 0 0x1000>;
539 vencltsys: clock-controller@19000000 {
540 compatible = "mediatek,mt8173-vencltsys", "syscon";
541 reg = <0 0x19000000 0 0x1000>;