arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include "mt8173-pinfunc.h"
  22
  23 / {
  24         compatible = "mediatek,mt8173";
  25         interrupt-parent = <&sysirq>;
  26         #address-cells = <2>;
  27         #size-cells = <2>;
  28
  29         aliases {
  30                 ovl0 = &ovl0;
  31                 ovl1 = &ovl1;
  32                 rdma0 = &rdma0;
  33                 rdma1 = &rdma1;
  34                 rdma2 = &rdma2;
  35                 wdma0 = &wdma0;
  36                 wdma1 = &wdma1;
  37                 color0 = &color0;
  38                 color1 = &color1;
  39                 split0 = &split0;
  40                 split1 = &split1;
  41                 dpi0 = &dpi0;
  42                 dsi0 = &dsi0;
  43                 dsi1 = &dsi1;
  44                 mdp_rdma0 = &mdp_rdma0;
  45                 mdp_rdma1 = &mdp_rdma1;
  46                 mdp_rsz0 = &mdp_rsz0;
  47                 mdp_rsz1 = &mdp_rsz1;
  48                 mdp_rsz2 = &mdp_rsz2;
  49                 mdp_wdma0 = &mdp_wdma0;
  50                 mdp_wrot0 = &mdp_wrot0;
  51                 mdp_wrot1 = &mdp_wrot1;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu-map {
  59                         cluster0 {
  60                                 core0 {
  61                                         cpu = <&cpu0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu1>;
  65                                 };
  66                         };
  67
  68                         cluster1 {
  69                                 core0 {
  70                                         cpu = <&cpu2>;
  71                                 };
  72                                 core1 {
  73                                         cpu = <&cpu3>;
  74                                 };
  75                         };
  76                 };
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53";
  81                         reg = <0x000>;
  82                         enable-method = "psci";
  83                         cpu-idle-states = <&CPU_SLEEP_0>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 cpu1: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53";
  90                         reg = <0x001>;
  91                         enable-method = "psci";
  92                         cpu-idle-states = <&CPU_SLEEP_0>;
  93                 };
  94
  95                 cpu2: cpu@100 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a57";
  98                         reg = <0x100>;
  99                         enable-method = "psci";
 100                         cpu-idle-states = <&CPU_SLEEP_0>;
 101                         #cooling-cells = <2>;
 102                 };
 103
 104                 cpu3: cpu@101 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a57";
 107                         reg = <0x101>;
 108                         enable-method = "psci";
 109                         cpu-idle-states = <&CPU_SLEEP_0>;
 110                 };
 111
 112                 idle-states {
 113                         entry-method = "psci";
 114
 115                         CPU_SLEEP_0: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 local-timer-stop;
 118                                 entry-latency-us = <639>;
 119                                 exit-latency-us = <680>;
 120                                 min-residency-us = <1088>;
 121                                 arm,psci-suspend-param = <0x0010000>;
 122                         };
 123                 };
 124         };
 125
 126         psci {
 127                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 128                 method = "smc";
 129                 cpu_suspend   = <0x84000001>;
 130                 cpu_off       = <0x84000002>;
 131                 cpu_on        = <0x84000003>;
 132         };
 133
 134         clk26m: oscillator@0 {
 135                 compatible = "fixed-clock";
 136                 #clock-cells = <0>;
 137                 clock-frequency = <26000000>;
 138                 clock-output-names = "clk26m";
 139         };
 140
 141         clk32k: oscillator@1 {
 142                 compatible = "fixed-clock";
 143                 #clock-cells = <0>;
 144                 clock-frequency = <32000>;
 145                 clock-output-names = "clk32k";
 146         };
 147
 148         cpum_ck: oscillator@2 {
 149                 compatible = "fixed-clock";
 150                 #clock-cells = <0>;
 151                 clock-frequency = <0>;
 152                 clock-output-names = "cpum_ck";
 153         };
 154
 155         thermal-zones {
 156                 cpu_thermal: cpu_thermal {
 157                         polling-delay-passive = <1000>; /* milliseconds */
 158                         polling-delay = <1000>; /* milliseconds */
 159
 160                         thermal-sensors = <&thermal>;
 161                         sustainable-power = <1500>; /* milliwatts */
 162
 163                         trips {
 164                                 threshold: trip-point@0 {
 165                                         temperature = <68000>;
 166                                         hysteresis = <2000>;
 167                                         type = "passive";
 168                                 };
 169
 170                                 target: trip-point@1 {
 171                                         temperature = <85000>;
 172                                         hysteresis = <2000>;
 173                                         type = "passive";
 174                                 };
 175
 176                                 cpu_crit: cpu_crit@0 {
 177                                         temperature = <115000>;
 178                                         hysteresis = <2000>;
 179                                         type = "critical";
 180                                 };
 181                         };
 182
 183                         cooling-maps {
 184                                 map@0 {
 185                                         trip = <&target>;
 186                                         cooling-device = <&cpu0 0 0>;
 187                                         contribution = <3072>;
 188                                 };
 189                                 map@1 {
 190                                         trip = <&target>;
 191                                         cooling-device = <&cpu2 0 0>;
 192                                         contribution = <1024>;
 193                                 };
 194                         };
 195                 };
 196         };
 197
 198         reserved-memory {
 199                 #address-cells = <2>;
 200                 #size-cells = <2>;
 201                 ranges;
 202                 vpu_dma_reserved: vpu_dma_mem_region {
 203                         compatible = "shared-dma-pool";
 204                         reg = <0 0xb7000000 0 0x500000>;
 205                         alignment = <0x1000>;
 206                         no-map;
 207                 };
 208         };
 209
 210         timer {
 211                 compatible = "arm,armv8-timer";
 212                 interrupt-parent = <&gic>;
 213                 interrupts = <GIC_PPI 13
 214                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 215                              <GIC_PPI 14
 216                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 217                              <GIC_PPI 11
 218                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 219                              <GIC_PPI 10
 220                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 221         };
 222
 223         soc {
 224                 #address-cells = <2>;
 225                 #size-cells = <2>;
 226                 compatible = "simple-bus";
 227                 ranges;
 228
 229                 topckgen: clock-controller@10000000 {
 230                         compatible = "mediatek,mt8173-topckgen";
 231                         reg = <0 0x10000000 0 0x1000>;
 232                         #clock-cells = <1>;
 233                 };
 234
 235                 infracfg: power-controller@10001000 {
 236                         compatible = "mediatek,mt8173-infracfg", "syscon";
 237                         reg = <0 0x10001000 0 0x1000>;
 238                         #clock-cells = <1>;
 239                         #reset-cells = <1>;
 240                 };
 241
 242                 pericfg: power-controller@10003000 {
 243                         compatible = "mediatek,mt8173-pericfg", "syscon";
 244                         reg = <0 0x10003000 0 0x1000>;
 245                         #clock-cells = <1>;
 246                         #reset-cells = <1>;
 247                 };
 248
 249                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 250                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 251                         reg = <0 0x10005000 0 0x1000>;
 252                 };
 253
 254                 pio: pinctrl@0x10005000 {
 255                         compatible = "mediatek,mt8173-pinctrl";
 256                         reg = <0 0x1000b000 0 0x1000>;
 257                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 258                         pins-are-numbered;
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261                         interrupt-controller;
 262                         #interrupt-cells = <2>;
 263                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 264                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 265                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 266
 267                         hdmi_pin: xxx {
 268
 269                                 /*hdmi htplg pin*/
 270                                 pins1 {
 271                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 272                                         input-enable;
 273                                         bias-pull-down;
 274                                 };
 275                         };
 276
 277                         i2c0_pins_a: i2c0 {
 278                                 pins1 {
 279                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 280                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 281                                         bias-disable;
 282                                 };
 283                         };
 284
 285                         i2c1_pins_a: i2c1 {
 286                                 pins1 {
 287                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 288                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 289                                         bias-disable;
 290                                 };
 291                         };
 292
 293                         i2c2_pins_a: i2c2 {
 294                                 pins1 {
 295                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 296                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 297                                         bias-disable;
 298                                 };
 299                         };
 300
 301                         i2c3_pins_a: i2c3 {
 302                                 pins1 {
 303                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 304                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 305                                         bias-disable;
 306                                 };
 307                         };
 308
 309                         i2c4_pins_a: i2c4 {
 310                                 pins1 {
 311                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 312                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 313                                         bias-disable;
 314                                 };
 315                         };
 316
 317                         i2c6_pins_a: i2c6 {
 318                                 pins1 {
 319                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 320                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 321                                         bias-disable;
 322                                 };
 323                         };
 324                 };
 325
 326                 scpsys: scpsys@10006000 {
 327                         compatible = "mediatek,mt8173-scpsys";
 328                         #power-domain-cells = <1>;
 329                         reg = <0 0x10006000 0 0x1000>;
 330                         clocks = <&clk26m>,
 331                                  <&topckgen CLK_TOP_MM_SEL>,
 332                                  <&topckgen CLK_TOP_VENC_SEL>,
 333                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 334                         clock-names = "mfg", "mm", "venc", "venc_lt";
 335                         infracfg = <&infracfg>;
 336                 };
 337
 338                 watchdog: watchdog@10007000 {
 339                         compatible = "mediatek,mt8173-wdt",
 340                                      "mediatek,mt6589-wdt";
 341                         reg = <0 0x10007000 0 0x100>;
 342                 };
 343
 344                 timer: timer@10008000 {
 345                         compatible = "mediatek,mt8173-timer",
 346                                      "mediatek,mt6577-timer";
 347                         reg = <0 0x10008000 0 0x1000>;
 348                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 349                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 350                                  <&topckgen CLK_TOP_RTC_SEL>;
 351                 };
 352
 353                 pwrap: pwrap@1000d000 {
 354                         compatible = "mediatek,mt8173-pwrap";
 355                         reg = <0 0x1000d000 0 0x1000>;
 356                         reg-names = "pwrap";
 357                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 358                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 359                         reset-names = "pwrap";
 360                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 361                         clock-names = "spi", "wrap";
 362                 };
 363
 364                 cec: cec@10013000 {
 365                         compatible = "mediatek,mt8173-cec";
 366                         reg = <0 0x10013000 0 0xbc>;
 367                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 368                         clocks = <&infracfg CLK_INFRA_CEC>;
 369                         status = "disabled";
 370                 };
 371
 372                 vpu: vpu@10020000 {
 373                         compatible = "mediatek,mt8173-vpu";
 374                         reg = <0 0x10020000 0 0x30000>,
 375                               <0 0x10050000 0 0x100>;
 376                         reg-names = "tcm", "cfg_reg";
 377                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 379                         clock-names = "main";
 380                         memory-region = <&vpu_dma_reserved>;
 381                 };
 382
 383                 sysirq: intpol-controller@10200620 {
 384                         compatible = "mediatek,mt8173-sysirq",
 385                                      "mediatek,mt6577-sysirq";
 386                         interrupt-controller;
 387                         #interrupt-cells = <3>;
 388                         interrupt-parent = <&gic>;
 389                         reg = <0 0x10200620 0 0x20>;
 390                 };
 391
 392                 iommu: iommu@10205000 {
 393                         compatible = "mediatek,mt8173-m4u";
 394                         reg = <0 0x10205000 0 0x1000>;
 395                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 396                         clocks = <&infracfg CLK_INFRA_M4U>;
 397                         clock-names = "bclk";
 398                         mediatek,larbs = <&larb0 &larb1 &larb2
 399                                           &larb3 &larb4 &larb5>;
 400                         #iommu-cells = <1>;
 401                 };
 402
 403                 efuse: efuse@10206000 {
 404                         compatible = "mediatek,mt8173-efuse";
 405                         reg = <0 0x10206000 0 0x1000>;
 406                         #address-cells = <1>;
 407                         #size-cells = <1>;
 408                         thermal_calibration: calib@528 {
 409                                 reg = <0x528 0xc>;
 410                         };
 411                 };
 412
 413                 apmixedsys: clock-controller@10209000 {
 414                         compatible = "mediatek,mt8173-apmixedsys";
 415                         reg = <0 0x10209000 0 0x1000>;
 416                         #clock-cells = <1>;
 417                 };
 418
 419                 hdmi_phy: hdmi-phy@10209100 {
 420                         compatible = "mediatek,mt8173-hdmi-phy";
 421                         reg = <0 0x10209100 0 0x24>;
 422                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 423                         clock-names = "pll_ref";
 424                         clock-output-names = "hdmitx_dig_cts";
 425                         mediatek,ibias = <0xa>;
 426                         mediatek,ibias_up = <0x1c>;
 427                         #clock-cells = <0>;
 428                         #phy-cells = <0>;
 429                         status = "disabled";
 430                 };
 431
 432                 mipi_tx0: mipi-dphy@10215000 {
 433                         compatible = "mediatek,mt8173-mipi-tx";
 434                         reg = <0 0x10215000 0 0x1000>;
 435                         clocks = <&clk26m>;
 436                         clock-output-names = "mipi_tx0_pll";
 437                         #clock-cells = <0>;
 438                         #phy-cells = <0>;
 439                         status = "disabled";
 440                 };
 441
 442                 mipi_tx1: mipi-dphy@10216000 {
 443                         compatible = "mediatek,mt8173-mipi-tx";
 444                         reg = <0 0x10216000 0 0x1000>;
 445                         clocks = <&clk26m>;
 446                         clock-output-names = "mipi_tx1_pll";
 447                         #clock-cells = <0>;
 448                         #phy-cells = <0>;
 449                         status = "disabled";
 450                 };
 451
 452                 gic: interrupt-controller@10220000 {
 453                         compatible = "arm,gic-400";
 454                         #interrupt-cells = <3>;
 455                         interrupt-parent = <&gic>;
 456                         interrupt-controller;
 457                         reg = <0 0x10221000 0 0x1000>,
 458                               <0 0x10222000 0 0x2000>,
 459                               <0 0x10224000 0 0x2000>,
 460                               <0 0x10226000 0 0x2000>;
 461                         interrupts = <GIC_PPI 9
 462                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 463                 };
 464
 465                 auxadc: auxadc@11001000 {
 466                         compatible = "mediatek,mt8173-auxadc";
 467                         reg = <0 0x11001000 0 0x1000>;
 468                         clocks = <&pericfg CLK_PERI_AUXADC>;
 469                         clock-names = "main";
 470                         #io-channel-cells = <1>;
 471                 };
 472
 473                 uart0: serial@11002000 {
 474                         compatible = "mediatek,mt8173-uart",
 475                                      "mediatek,mt6577-uart";
 476                         reg = <0 0x11002000 0 0x400>;
 477                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 478                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 479                         clock-names = "baud", "bus";
 480                         status = "disabled";
 481                 };
 482
 483                 uart1: serial@11003000 {
 484                         compatible = "mediatek,mt8173-uart",
 485                                      "mediatek,mt6577-uart";
 486                         reg = <0 0x11003000 0 0x400>;
 487                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 488                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 489                         clock-names = "baud", "bus";
 490                         status = "disabled";
 491                 };
 492
 493                 uart2: serial@11004000 {
 494                         compatible = "mediatek,mt8173-uart",
 495                                      "mediatek,mt6577-uart";
 496                         reg = <0 0x11004000 0 0x400>;
 497                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 498                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 499                         clock-names = "baud", "bus";
 500                         status = "disabled";
 501                 };
 502
 503                 uart3: serial@11005000 {
 504                         compatible = "mediatek,mt8173-uart",
 505                                      "mediatek,mt6577-uart";
 506                         reg = <0 0x11005000 0 0x400>;
 507                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 508                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 509                         clock-names = "baud", "bus";
 510                         status = "disabled";
 511                 };
 512
 513                 i2c0: i2c@11007000 {
 514                         compatible = "mediatek,mt8173-i2c";
 515                         reg = <0 0x11007000 0 0x70>,
 516                               <0 0x11000100 0 0x80>;
 517                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 518                         clock-div = <16>;
 519                         clocks = <&pericfg CLK_PERI_I2C0>,
 520                                  <&pericfg CLK_PERI_AP_DMA>;
 521                         clock-names = "main", "dma";
 522                         pinctrl-names = "default";
 523                         pinctrl-0 = <&i2c0_pins_a>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         status = "disabled";
 527                 };
 528
 529                 i2c1: i2c@11008000 {
 530                         compatible = "mediatek,mt8173-i2c";
 531                         reg = <0 0x11008000 0 0x70>,
 532                               <0 0x11000180 0 0x80>;
 533                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 534                         clock-div = <16>;
 535                         clocks = <&pericfg CLK_PERI_I2C1>,
 536                                  <&pericfg CLK_PERI_AP_DMA>;
 537                         clock-names = "main", "dma";
 538                         pinctrl-names = "default";
 539                         pinctrl-0 = <&i2c1_pins_a>;
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         status = "disabled";
 543                 };
 544
 545                 i2c2: i2c@11009000 {
 546                         compatible = "mediatek,mt8173-i2c";
 547                         reg = <0 0x11009000 0 0x70>,
 548                               <0 0x11000200 0 0x80>;
 549                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 550                         clock-div = <16>;
 551                         clocks = <&pericfg CLK_PERI_I2C2>,
 552                                  <&pericfg CLK_PERI_AP_DMA>;
 553                         clock-names = "main", "dma";
 554                         pinctrl-names = "default";
 555                         pinctrl-0 = <&i2c2_pins_a>;
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         status = "disabled";
 559                 };
 560
 561                 spi: spi@1100a000 {
 562                         compatible = "mediatek,mt8173-spi";
 563                         #address-cells = <1>;
 564                         #size-cells = <0>;
 565                         reg = <0 0x1100a000 0 0x1000>;
 566                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 567                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 568                                  <&topckgen CLK_TOP_SPI_SEL>,
 569                                  <&pericfg CLK_PERI_SPI0>;
 570                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 571                         status = "disabled";
 572                 };
 573
 574                 thermal: thermal@1100b000 {
 575                         #thermal-sensor-cells = <0>;
 576                         compatible = "mediatek,mt8173-thermal";
 577                         reg = <0 0x1100b000 0 0x1000>;
 578                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 579                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 580                         clock-names = "therm", "auxadc";
 581                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 582                         mediatek,auxadc = <&auxadc>;
 583                         mediatek,apmixedsys = <&apmixedsys>;
 584                         nvmem-cells = <&thermal_calibration>;
 585                         nvmem-cell-names = "calibration-data";
 586                 };
 587
 588                 nor_flash: spi@1100d000 {
 589                         compatible = "mediatek,mt8173-nor";
 590                         reg = <0 0x1100d000 0 0xe0>;
 591                         clocks = <&pericfg CLK_PERI_SPI>,
 592                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 593                         clock-names = "spi", "sf";
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         status = "disabled";
 597                 };
 598
 599                 i2c3: i2c@11010000 {
 600                         compatible = "mediatek,mt8173-i2c";
 601                         reg = <0 0x11010000 0 0x70>,
 602                               <0 0x11000280 0 0x80>;
 603                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 604                         clock-div = <16>;
 605                         clocks = <&pericfg CLK_PERI_I2C3>,
 606                                  <&pericfg CLK_PERI_AP_DMA>;
 607                         clock-names = "main", "dma";
 608                         pinctrl-names = "default";
 609                         pinctrl-0 = <&i2c3_pins_a>;
 610                         #address-cells = <1>;
 611                         #size-cells = <0>;
 612                         status = "disabled";
 613                 };
 614
 615                 i2c4: i2c@11011000 {
 616                         compatible = "mediatek,mt8173-i2c";
 617                         reg = <0 0x11011000 0 0x70>,
 618                               <0 0x11000300 0 0x80>;
 619                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 620                         clock-div = <16>;
 621                         clocks = <&pericfg CLK_PERI_I2C4>,
 622                                  <&pericfg CLK_PERI_AP_DMA>;
 623                         clock-names = "main", "dma";
 624                         pinctrl-names = "default";
 625                         pinctrl-0 = <&i2c4_pins_a>;
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                         status = "disabled";
 629                 };
 630
 631                 hdmiddc0: i2c@11012000 {
 632                         compatible = "mediatek,mt8173-hdmi-ddc";
 633                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 634                         reg = <0 0x11012000 0 0x1C>;
 635                         clocks = <&pericfg CLK_PERI_I2C5>;
 636                         clock-names = "ddc-i2c";
 637                 };
 638
 639                 i2c6: i2c@11013000 {
 640                         compatible = "mediatek,mt8173-i2c";
 641                         reg = <0 0x11013000 0 0x70>,
 642                               <0 0x11000080 0 0x80>;
 643                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 644                         clock-div = <16>;
 645                         clocks = <&pericfg CLK_PERI_I2C6>,
 646                                  <&pericfg CLK_PERI_AP_DMA>;
 647                         clock-names = "main", "dma";
 648                         pinctrl-names = "default";
 649                         pinctrl-0 = <&i2c6_pins_a>;
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         status = "disabled";
 653                 };
 654
 655                 afe: audio-controller@11220000  {
 656                         compatible = "mediatek,mt8173-afe-pcm";
 657                         reg = <0 0x11220000 0 0x1000>;
 658                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 659                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 660                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 661                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 662                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 663                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 664                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 665                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 666                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 667                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 668                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 669                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 670                         clock-names = "infra_sys_audio_clk",
 671                                       "top_pdn_audio",
 672                                       "top_pdn_aud_intbus",
 673                                       "bck0",
 674                                       "bck1",
 675                                       "i2s0_m",
 676                                       "i2s1_m",
 677                                       "i2s2_m",
 678                                       "i2s3_m",
 679                                       "i2s3_b";
 680                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 681                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 682                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 683                                                  <&topckgen CLK_TOP_APLL2>;
 684                 };
 685
 686                 mmc0: mmc@11230000 {
 687                         compatible = "mediatek,mt8173-mmc",
 688                                      "mediatek,mt8135-mmc";
 689                         reg = <0 0x11230000 0 0x1000>;
 690                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 691                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 692                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 693                         clock-names = "source", "hclk";
 694                         status = "disabled";
 695                 };
 696
 697                 mmc1: mmc@11240000 {
 698                         compatible = "mediatek,mt8173-mmc",
 699                                      "mediatek,mt8135-mmc";
 700                         reg = <0 0x11240000 0 0x1000>;
 701                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 702                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 703                                  <&topckgen CLK_TOP_AXI_SEL>;
 704                         clock-names = "source", "hclk";
 705                         status = "disabled";
 706                 };
 707
 708                 mmc2: mmc@11250000 {
 709                         compatible = "mediatek,mt8173-mmc",
 710                                      "mediatek,mt8135-mmc";
 711                         reg = <0 0x11250000 0 0x1000>;
 712                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 713                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 714                                  <&topckgen CLK_TOP_AXI_SEL>;
 715                         clock-names = "source", "hclk";
 716                         status = "disabled";
 717                 };
 718
 719                 mmc3: mmc@11260000 {
 720                         compatible = "mediatek,mt8173-mmc",
 721                                      "mediatek,mt8135-mmc";
 722                         reg = <0 0x11260000 0 0x1000>;
 723                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 724                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 725                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 726                         clock-names = "source", "hclk";
 727                         status = "disabled";
 728                 };
 729
 730                 ssusb: usb@11271000 {
 731                         compatible = "mediatek,mt8173-mtu3";
 732                         reg = <0 0x11271000 0 0x3000>,
 733                               <0 0x11280700 0 0x0100>;
 734                         reg-names = "mac", "ippc";
 735                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 736                         phys = <&u2port0 PHY_TYPE_USB2>,
 737                                <&u3port0 PHY_TYPE_USB3>,
 738                                <&u2port1 PHY_TYPE_USB2>;
 739                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 740                         clocks = <&topckgen CLK_TOP_USB30_SEL>,
 741                                  <&clk26m>,
 742                                  <&pericfg CLK_PERI_USB0>,
 743                                  <&pericfg CLK_PERI_USB1>;
 744                         clock-names = "sys_ck",
 745                                       "ref_ck",
 746                                       "wakeup_deb_p0",
 747                                       "wakeup_deb_p1";
 748                         mediatek,syscon-wakeup = <&pericfg>;
 749                         #address-cells = <2>;
 750                         #size-cells = <2>;
 751                         ranges;
 752                         status = "disabled";
 753
 754                         usb_host: xhci@11270000 {
 755                                 compatible = "mediatek,mt8173-xhci";
 756                                 reg = <0 0x11270000 0 0x1000>;
 757                                 reg-names = "mac";
 758                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 759                                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 760                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 761                                 clock-names = "sys_ck", "ref_ck";
 762                                 status = "disabled";
 763                         };
 764                 };
 765
 766                 u3phy: usb-phy@11290000 {
 767                         compatible = "mediatek,mt8173-u3phy";
 768                         reg = <0 0x11290000 0 0x800>;
 769                         #address-cells = <2>;
 770                         #size-cells = <2>;
 771                         ranges;
 772                         status = "okay";
 773
 774                         u2port0: usb-phy@11290800 {
 775                                 reg = <0 0x11290800 0 0x100>;
 776                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 777                                 clock-names = "ref";
 778                                 #phy-cells = <1>;
 779                                 status = "okay";
 780                         };
 781
 782                         u3port0: usb-phy@11290900 {
 783                                 reg = <0 0x11290900 0 0x700>;
 784                                 clocks = <&clk26m>;
 785                                 clock-names = "ref";
 786                                 #phy-cells = <1>;
 787                                 status = "okay";
 788                         };
 789
 790                         u2port1: usb-phy@11291000 {
 791                                 reg = <0 0x11291000 0 0x100>;
 792                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 793                                 clock-names = "ref";
 794                                 #phy-cells = <1>;
 795                                 status = "okay";
 796                         };
 797                 };
 798
 799                 mmsys: clock-controller@14000000 {
 800                         compatible = "mediatek,mt8173-mmsys", "syscon";
 801                         reg = <0 0x14000000 0 0x1000>;
 802                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 803                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
 804                         assigned-clock-rates = <400000000>;
 805                         #clock-cells = <1>;
 806                 };
 807
 808                 mdp_rdma0: rdma@14001000 {
 809                         compatible = "mediatek,mt8173-mdp-rdma",
 810                                      "mediatek,mt8173-mdp";
 811                         reg = <0 0x14001000 0 0x1000>;
 812                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
 813                                  <&mmsys CLK_MM_MUTEX_32K>;
 814                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 815                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
 816                         mediatek,larb = <&larb0>;
 817                         mediatek,vpu = <&vpu>;
 818                 };
 819
 820                 mdp_rdma1: rdma@14002000 {
 821                         compatible = "mediatek,mt8173-mdp-rdma";
 822                         reg = <0 0x14002000 0 0x1000>;
 823                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
 824                                  <&mmsys CLK_MM_MUTEX_32K>;
 825                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 826                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
 827                         mediatek,larb = <&larb4>;
 828                 };
 829
 830                 mdp_rsz0: rsz@14003000 {
 831                         compatible = "mediatek,mt8173-mdp-rsz";
 832                         reg = <0 0x14003000 0 0x1000>;
 833                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
 834                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 835                 };
 836
 837                 mdp_rsz1: rsz@14004000 {
 838                         compatible = "mediatek,mt8173-mdp-rsz";
 839                         reg = <0 0x14004000 0 0x1000>;
 840                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
 841                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 842                 };
 843
 844                 mdp_rsz2: rsz@14005000 {
 845                         compatible = "mediatek,mt8173-mdp-rsz";
 846                         reg = <0 0x14005000 0 0x1000>;
 847                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
 848                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 849                 };
 850
 851                 mdp_wdma0: wdma@14006000 {
 852                         compatible = "mediatek,mt8173-mdp-wdma";
 853                         reg = <0 0x14006000 0 0x1000>;
 854                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
 855                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 856                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
 857                         mediatek,larb = <&larb0>;
 858                 };
 859
 860                 mdp_wrot0: wrot@14007000 {
 861                         compatible = "mediatek,mt8173-mdp-wrot";
 862                         reg = <0 0x14007000 0 0x1000>;
 863                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
 864                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 865                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
 866                         mediatek,larb = <&larb0>;
 867                 };
 868
 869                 mdp_wrot1: wrot@14008000 {
 870                         compatible = "mediatek,mt8173-mdp-wrot";
 871                         reg = <0 0x14008000 0 0x1000>;
 872                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
 873                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 874                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
 875                         mediatek,larb = <&larb4>;
 876                 };
 877
 878                 ovl0: ovl@1400c000 {
 879                         compatible = "mediatek,mt8173-disp-ovl";
 880                         reg = <0 0x1400c000 0 0x1000>;
 881                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
 882                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 883                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
 884                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
 885                         mediatek,larb = <&larb0>;
 886                 };
 887
 888                 ovl1: ovl@1400d000 {
 889                         compatible = "mediatek,mt8173-disp-ovl";
 890                         reg = <0 0x1400d000 0 0x1000>;
 891                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
 892                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 893                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
 894                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
 895                         mediatek,larb = <&larb4>;
 896                 };
 897
 898                 rdma0: rdma@1400e000 {
 899                         compatible = "mediatek,mt8173-disp-rdma";
 900                         reg = <0 0x1400e000 0 0x1000>;
 901                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
 902                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 903                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 904                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
 905                         mediatek,larb = <&larb0>;
 906                 };
 907
 908                 rdma1: rdma@1400f000 {
 909                         compatible = "mediatek,mt8173-disp-rdma";
 910                         reg = <0 0x1400f000 0 0x1000>;
 911                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
 912                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 913                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 914                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
 915                         mediatek,larb = <&larb4>;
 916                 };
 917
 918                 rdma2: rdma@14010000 {
 919                         compatible = "mediatek,mt8173-disp-rdma";
 920                         reg = <0 0x14010000 0 0x1000>;
 921                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
 922                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 923                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
 924                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
 925                         mediatek,larb = <&larb4>;
 926                 };
 927
 928                 wdma0: wdma@14011000 {
 929                         compatible = "mediatek,mt8173-disp-wdma";
 930                         reg = <0 0x14011000 0 0x1000>;
 931                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
 932                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 933                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
 934                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
 935                         mediatek,larb = <&larb0>;
 936                 };
 937
 938                 wdma1: wdma@14012000 {
 939                         compatible = "mediatek,mt8173-disp-wdma";
 940                         reg = <0 0x14012000 0 0x1000>;
 941                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
 942                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 943                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
 944                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
 945                         mediatek,larb = <&larb4>;
 946                 };
 947
 948                 color0: color@14013000 {
 949                         compatible = "mediatek,mt8173-disp-color";
 950                         reg = <0 0x14013000 0 0x1000>;
 951                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
 952                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 953                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
 954                 };
 955
 956                 color1: color@14014000 {
 957                         compatible = "mediatek,mt8173-disp-color";
 958                         reg = <0 0x14014000 0 0x1000>;
 959                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
 960                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 961                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
 962                 };
 963
 964                 aal@14015000 {
 965                         compatible = "mediatek,mt8173-disp-aal";
 966                         reg = <0 0x14015000 0 0x1000>;
 967                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
 968                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 969                         clocks = <&mmsys CLK_MM_DISP_AAL>;
 970                 };
 971
 972                 gamma@14016000 {
 973                         compatible = "mediatek,mt8173-disp-gamma";
 974                         reg = <0 0x14016000 0 0x1000>;
 975                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
 976                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 977                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
 978                 };
 979
 980                 merge@14017000 {
 981                         compatible = "mediatek,mt8173-disp-merge";
 982                         reg = <0 0x14017000 0 0x1000>;
 983                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 984                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
 985                 };
 986
 987                 split0: split@14018000 {
 988                         compatible = "mediatek,mt8173-disp-split";
 989                         reg = <0 0x14018000 0 0x1000>;
 990                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 991                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
 992                 };
 993
 994                 split1: split@14019000 {
 995                         compatible = "mediatek,mt8173-disp-split";
 996                         reg = <0 0x14019000 0 0x1000>;
 997                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 998                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
 999                 };
1000
1001                 ufoe@1401a000 {
1002                         compatible = "mediatek,mt8173-disp-ufoe";
1003                         reg = <0 0x1401a000 0 0x1000>;
1004                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1005                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1006                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1007                 };
1008
1009                 dsi0: dsi@1401b000 {
1010                         compatible = "mediatek,mt8173-dsi";
1011                         reg = <0 0x1401b000 0 0x1000>;
1012                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1013                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1014                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1015                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1016                                  <&mipi_tx0>;
1017                         clock-names = "engine", "digital", "hs";
1018                         phys = <&mipi_tx0>;
1019                         phy-names = "dphy";
1020                         status = "disabled";
1021                 };
1022
1023                 dsi1: dsi@1401c000 {
1024                         compatible = "mediatek,mt8173-dsi";
1025                         reg = <0 0x1401c000 0 0x1000>;
1026                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1027                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1028                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1029                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1030                                  <&mipi_tx1>;
1031                         clock-names = "engine", "digital", "hs";
1032                         phys = <&mipi_tx1>;
1033                         phy-names = "dphy";
1034                         status = "disabled";
1035                 };
1036
1037                 dpi0: dpi@1401d000 {
1038                         compatible = "mediatek,mt8173-dpi";
1039                         reg = <0 0x1401d000 0 0x1000>;
1040                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1041                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1042                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1043                                  <&mmsys CLK_MM_DPI_ENGINE>,
1044                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1045                         clock-names = "pixel", "engine", "pll";
1046                         status = "disabled";
1047
1048                         port {
1049                                 dpi0_out: endpoint {
1050                                         remote-endpoint = <&hdmi0_in>;
1051                                 };
1052                         };
1053                 };
1054
1055                 pwm0: pwm@1401e000 {
1056                         compatible = "mediatek,mt8173-disp-pwm",
1057                                      "mediatek,mt6595-disp-pwm";
1058                         reg = <0 0x1401e000 0 0x1000>;
1059                         #pwm-cells = <2>;
1060                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1061                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1062                         clock-names = "main", "mm";
1063                         status = "disabled";
1064                 };
1065
1066                 pwm1: pwm@1401f000 {
1067                         compatible = "mediatek,mt8173-disp-pwm",
1068                                      "mediatek,mt6595-disp-pwm";
1069                         reg = <0 0x1401f000 0 0x1000>;
1070                         #pwm-cells = <2>;
1071                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1072                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1073                         clock-names = "main", "mm";
1074                         status = "disabled";
1075                 };
1076
1077                 mutex: mutex@14020000 {
1078                         compatible = "mediatek,mt8173-disp-mutex";
1079                         reg = <0 0x14020000 0 0x1000>;
1080                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1081                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1082                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1083                 };
1084
1085                 larb0: larb@14021000 {
1086                         compatible = "mediatek,mt8173-smi-larb";
1087                         reg = <0 0x14021000 0 0x1000>;
1088                         mediatek,smi = <&smi_common>;
1089                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1090                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1091                                  <&mmsys CLK_MM_SMI_LARB0>;
1092                         clock-names = "apb", "smi";
1093                 };
1094
1095                 smi_common: smi@14022000 {
1096                         compatible = "mediatek,mt8173-smi-common";
1097                         reg = <0 0x14022000 0 0x1000>;
1098                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1099                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1100                                  <&mmsys CLK_MM_SMI_COMMON>;
1101                         clock-names = "apb", "smi";
1102                 };
1103
1104                 od@14023000 {
1105                         compatible = "mediatek,mt8173-disp-od";
1106                         reg = <0 0x14023000 0 0x1000>;
1107                         clocks = <&mmsys CLK_MM_DISP_OD>;
1108                 };
1109
1110                 hdmi0: hdmi@14025000 {
1111                         compatible = "mediatek,mt8173-hdmi";
1112                         reg = <0 0x14025000 0 0x400>;
1113                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1114                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1115                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1116                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1117                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1118                         clock-names = "pixel", "pll", "bclk", "spdif";
1119                         pinctrl-names = "default";
1120                         pinctrl-0 = <&hdmi_pin>;
1121                         phys = <&hdmi_phy>;
1122                         phy-names = "hdmi";
1123                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1124                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1125                         assigned-clock-parents = <&hdmi_phy>;
1126                         status = "disabled";
1127
1128                         ports {
1129                                 #address-cells = <1>;
1130                                 #size-cells = <0>;
1131
1132                                 port@0 {
1133                                         reg = <0>;
1134
1135                                         hdmi0_in: endpoint {
1136                                                 remote-endpoint = <&dpi0_out>;
1137                                         };
1138                                 };
1139                         };
1140                 };
1141
1142                 larb4: larb@14027000 {
1143                         compatible = "mediatek,mt8173-smi-larb";
1144                         reg = <0 0x14027000 0 0x1000>;
1145                         mediatek,smi = <&smi_common>;
1146                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1147                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1148                                  <&mmsys CLK_MM_SMI_LARB4>;
1149                         clock-names = "apb", "smi";
1150                 };
1151
1152                 imgsys: clock-controller@15000000 {
1153                         compatible = "mediatek,mt8173-imgsys", "syscon";
1154                         reg = <0 0x15000000 0 0x1000>;
1155                         #clock-cells = <1>;
1156                 };
1157
1158                 larb2: larb@15001000 {
1159                         compatible = "mediatek,mt8173-smi-larb";
1160                         reg = <0 0x15001000 0 0x1000>;
1161                         mediatek,smi = <&smi_common>;
1162                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1163                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1164                                  <&imgsys CLK_IMG_LARB2_SMI>;
1165                         clock-names = "apb", "smi";
1166                 };
1167
1168                 vdecsys: clock-controller@16000000 {
1169                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1170                         reg = <0 0x16000000 0 0x1000>;
1171                         #clock-cells = <1>;
1172                 };
1173
1174                 vcodec_dec: vcodec@16000000 {
1175                         compatible = "mediatek,mt8173-vcodec-dec";
1176                         reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
1177                               <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1178                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1179                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1180                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1181                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1182                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1183                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1184                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1185                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1186                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1187                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1188                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1189                         mediatek,larb = <&larb1>;
1190                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1191                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1192                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1193                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1194                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1195                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1196                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1197                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1198                         mediatek,vpu = <&vpu>;
1199                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1200                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1201                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1202                                  <&topckgen CLK_TOP_CCI400_SEL>,
1203                                  <&topckgen CLK_TOP_VDEC_SEL>,
1204                                  <&topckgen CLK_TOP_VCODECPLL>,
1205                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1206                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1207                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1208                         clock-names = "vcodecpll",
1209                                       "univpll_d2",
1210                                       "clk_cci400_sel",
1211                                       "vdec_sel",
1212                                       "vdecpll",
1213                                       "vencpll",
1214                                       "venc_lt_sel",
1215                                       "vdec_bus_clk_src";
1216                 };
1217
1218                 larb1: larb@16010000 {
1219                         compatible = "mediatek,mt8173-smi-larb";
1220                         reg = <0 0x16010000 0 0x1000>;
1221                         mediatek,smi = <&smi_common>;
1222                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1223                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1224                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1225                         clock-names = "apb", "smi";
1226                 };
1227
1228                 vencsys: clock-controller@18000000 {
1229                         compatible = "mediatek,mt8173-vencsys", "syscon";
1230                         reg = <0 0x18000000 0 0x1000>;
1231                         #clock-cells = <1>;
1232                 };
1233
1234                 larb3: larb@18001000 {
1235                         compatible = "mediatek,mt8173-smi-larb";
1236                         reg = <0 0x18001000 0 0x1000>;
1237                         mediatek,smi = <&smi_common>;
1238                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1239                         clocks = <&vencsys CLK_VENC_CKE1>,
1240                                  <&vencsys CLK_VENC_CKE0>;
1241                         clock-names = "apb", "smi";
1242                 };
1243
1244                 vcodec_enc: vcodec@18002000 {
1245                         compatible = "mediatek,mt8173-vcodec-enc";
1246                         reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
1247                               <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
1248                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1249                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1250                         mediatek,larb = <&larb3>,
1251                                         <&larb5>;
1252                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1253                                  <&iommu M4U_PORT_VENC_REC>,
1254                                  <&iommu M4U_PORT_VENC_BSDMA>,
1255                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1256                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1257                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1258                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1259                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1260                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1261                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1262                                  <&iommu M4U_PORT_VENC_NBM_WDMA>,
1263                                  <&iommu M4U_PORT_VENC_RCPU_SET2>,
1264                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1265                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1266                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1267                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1268                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1269                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1270                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1271                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1272                         mediatek,vpu = <&vpu>;
1273                         clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1274                                  <&topckgen CLK_TOP_VENC_SEL>,
1275                                  <&topckgen CLK_TOP_UNIVPLL1_D2>,
1276                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
1277                         clock-names = "venc_sel_src",
1278                                       "venc_sel",
1279                                       "venc_lt_sel_src",
1280                                       "venc_lt_sel";
1281                 };
1282
1283                 vencltsys: clock-controller@19000000 {
1284                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1285                         reg = <0 0x19000000 0 0x1000>;
1286                         #clock-cells = <1>;
1287                 };
1288
1289                 larb5: larb@19001000 {
1290                         compatible = "mediatek,mt8173-smi-larb";
1291                         reg = <0 0x19001000 0 0x1000>;
1292                         mediatek,smi = <&smi_common>;
1293                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1294                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1295                                  <&vencltsys CLK_VENCLT_CKE0>;
1296                         clock-names = "apb", "smi";
1297                 };
1298         };
1299 };
1300