2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include "mt8173-pinfunc.h"
24 compatible = "mediatek,mt8173";
25 interrupt-parent = <&sysirq>;
44 mdp_rdma0 = &mdp_rdma0;
45 mdp_rdma1 = &mdp_rdma1;
49 mdp_wdma0 = &mdp_wdma0;
50 mdp_wrot0 = &mdp_wrot0;
51 mdp_wrot1 = &mdp_wrot1;
54 cluster0_opp: opp_table0 {
55 compatible = "operating-points-v2";
58 opp-hz = /bits/ 64 <507000000>;
59 opp-microvolt = <859000>;
62 opp-hz = /bits/ 64 <702000000>;
63 opp-microvolt = <908000>;
66 opp-hz = /bits/ 64 <1001000000>;
67 opp-microvolt = <983000>;
70 opp-hz = /bits/ 64 <1105000000>;
71 opp-microvolt = <1009000>;
74 opp-hz = /bits/ 64 <1209000000>;
75 opp-microvolt = <1034000>;
78 opp-hz = /bits/ 64 <1300000000>;
79 opp-microvolt = <1057000>;
82 opp-hz = /bits/ 64 <1508000000>;
83 opp-microvolt = <1109000>;
86 opp-hz = /bits/ 64 <1703000000>;
87 opp-microvolt = <1125000>;
91 cluster1_opp: opp_table1 {
92 compatible = "operating-points-v2";
95 opp-hz = /bits/ 64 <507000000>;
96 opp-microvolt = <828000>;
99 opp-hz = /bits/ 64 <702000000>;
100 opp-microvolt = <867000>;
103 opp-hz = /bits/ 64 <1001000000>;
104 opp-microvolt = <927000>;
107 opp-hz = /bits/ 64 <1209000000>;
108 opp-microvolt = <968000>;
111 opp-hz = /bits/ 64 <1404000000>;
112 opp-microvolt = <1007000>;
115 opp-hz = /bits/ 64 <1612000000>;
116 opp-microvolt = <1049000>;
119 opp-hz = /bits/ 64 <1807000000>;
120 opp-microvolt = <1089000>;
123 opp-hz = /bits/ 64 <2106000000>;
124 opp-microvolt = <1125000>;
129 #address-cells = <1>;
154 compatible = "arm,cortex-a53";
156 enable-method = "psci";
157 cpu-idle-states = <&CPU_SLEEP_0>;
158 #cooling-cells = <2>;
159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
160 <&apmixedsys CLK_APMIXED_MAINPLL>;
161 clock-names = "cpu", "intermediate";
162 operating-points-v2 = <&cluster0_opp>;
167 compatible = "arm,cortex-a53";
169 enable-method = "psci";
170 cpu-idle-states = <&CPU_SLEEP_0>;
171 #cooling-cells = <2>;
172 clocks = <&infracfg CLK_INFRA_CA53SEL>,
173 <&apmixedsys CLK_APMIXED_MAINPLL>;
174 clock-names = "cpu", "intermediate";
175 operating-points-v2 = <&cluster0_opp>;
180 compatible = "arm,cortex-a57";
182 enable-method = "psci";
183 cpu-idle-states = <&CPU_SLEEP_0>;
184 #cooling-cells = <2>;
185 clocks = <&infracfg CLK_INFRA_CA57SEL>,
186 <&apmixedsys CLK_APMIXED_MAINPLL>;
187 clock-names = "cpu", "intermediate";
188 operating-points-v2 = <&cluster1_opp>;
193 compatible = "arm,cortex-a57";
195 enable-method = "psci";
196 cpu-idle-states = <&CPU_SLEEP_0>;
197 #cooling-cells = <2>;
198 clocks = <&infracfg CLK_INFRA_CA57SEL>,
199 <&apmixedsys CLK_APMIXED_MAINPLL>;
200 clock-names = "cpu", "intermediate";
201 operating-points-v2 = <&cluster1_opp>;
205 entry-method = "psci";
207 CPU_SLEEP_0: cpu-sleep-0 {
208 compatible = "arm,idle-state";
210 entry-latency-us = <639>;
211 exit-latency-us = <680>;
212 min-residency-us = <1088>;
213 arm,psci-suspend-param = <0x0010000>;
219 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
221 cpu_suspend = <0x84000001>;
222 cpu_off = <0x84000002>;
223 cpu_on = <0x84000003>;
226 clk26m: oscillator0 {
227 compatible = "fixed-clock";
229 clock-frequency = <26000000>;
230 clock-output-names = "clk26m";
233 clk32k: oscillator1 {
234 compatible = "fixed-clock";
236 clock-frequency = <32000>;
237 clock-output-names = "clk32k";
240 cpum_ck: oscillator2 {
241 compatible = "fixed-clock";
243 clock-frequency = <0>;
244 clock-output-names = "cpum_ck";
248 cpu_thermal: cpu_thermal {
249 polling-delay-passive = <1000>; /* milliseconds */
250 polling-delay = <1000>; /* milliseconds */
252 thermal-sensors = <&thermal>;
253 sustainable-power = <1500>; /* milliwatts */
256 threshold: trip-point0 {
257 temperature = <68000>;
262 target: trip-point1 {
263 temperature = <85000>;
268 cpu_crit: cpu_crit0 {
269 temperature = <115000>;
278 cooling-device = <&cpu0 0 0>;
279 contribution = <3072>;
283 cooling-device = <&cpu2 0 0>;
284 contribution = <1024>;
291 #address-cells = <2>;
294 vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
295 compatible = "shared-dma-pool";
296 reg = <0 0xb7000000 0 0x500000>;
297 alignment = <0x1000>;
303 compatible = "arm,armv8-timer";
304 interrupt-parent = <&gic>;
305 interrupts = <GIC_PPI 13
306 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
308 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
310 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
312 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
316 #address-cells = <2>;
318 compatible = "simple-bus";
321 topckgen: clock-controller@10000000 {
322 compatible = "mediatek,mt8173-topckgen";
323 reg = <0 0x10000000 0 0x1000>;
327 infracfg: power-controller@10001000 {
328 compatible = "mediatek,mt8173-infracfg", "syscon";
329 reg = <0 0x10001000 0 0x1000>;
334 pericfg: power-controller@10003000 {
335 compatible = "mediatek,mt8173-pericfg", "syscon";
336 reg = <0 0x10003000 0 0x1000>;
341 syscfg_pctl_a: syscfg_pctl_a@10005000 {
342 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
343 reg = <0 0x10005000 0 0x1000>;
346 pio: pinctrl@1000b000 {
347 compatible = "mediatek,mt8173-pinctrl";
348 reg = <0 0x1000b000 0 0x1000>;
349 mediatek,pctl-regmap = <&syscfg_pctl_a>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
363 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
371 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
372 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
379 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
380 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
387 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
388 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
395 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
396 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
403 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
404 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
411 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
412 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
418 scpsys: scpsys@10006000 {
419 compatible = "mediatek,mt8173-scpsys";
420 #power-domain-cells = <1>;
421 reg = <0 0x10006000 0 0x1000>;
423 <&topckgen CLK_TOP_MM_SEL>,
424 <&topckgen CLK_TOP_VENC_SEL>,
425 <&topckgen CLK_TOP_VENC_LT_SEL>;
426 clock-names = "mfg", "mm", "venc", "venc_lt";
427 infracfg = <&infracfg>;
430 watchdog: watchdog@10007000 {
431 compatible = "mediatek,mt8173-wdt",
432 "mediatek,mt6589-wdt";
433 reg = <0 0x10007000 0 0x100>;
436 timer: timer@10008000 {
437 compatible = "mediatek,mt8173-timer",
438 "mediatek,mt6577-timer";
439 reg = <0 0x10008000 0 0x1000>;
440 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
441 clocks = <&infracfg CLK_INFRA_CLK_13M>,
442 <&topckgen CLK_TOP_RTC_SEL>;
445 pwrap: pwrap@1000d000 {
446 compatible = "mediatek,mt8173-pwrap";
447 reg = <0 0x1000d000 0 0x1000>;
449 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
450 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
451 reset-names = "pwrap";
452 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
453 clock-names = "spi", "wrap";
457 compatible = "mediatek,mt8173-cec";
458 reg = <0 0x10013000 0 0xbc>;
459 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
460 clocks = <&infracfg CLK_INFRA_CEC>;
465 compatible = "mediatek,mt8173-vpu";
466 reg = <0 0x10020000 0 0x30000>,
467 <0 0x10050000 0 0x100>;
468 reg-names = "tcm", "cfg_reg";
469 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&topckgen CLK_TOP_SCP_SEL>;
471 clock-names = "main";
472 memory-region = <&vpu_dma_reserved>;
475 sysirq: intpol-controller@10200620 {
476 compatible = "mediatek,mt8173-sysirq",
477 "mediatek,mt6577-sysirq";
478 interrupt-controller;
479 #interrupt-cells = <3>;
480 interrupt-parent = <&gic>;
481 reg = <0 0x10200620 0 0x20>;
484 iommu: iommu@10205000 {
485 compatible = "mediatek,mt8173-m4u";
486 reg = <0 0x10205000 0 0x1000>;
487 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
488 clocks = <&infracfg CLK_INFRA_M4U>;
489 clock-names = "bclk";
490 mediatek,larbs = <&larb0 &larb1 &larb2
491 &larb3 &larb4 &larb5>;
495 efuse: efuse@10206000 {
496 compatible = "mediatek,mt8173-efuse";
497 reg = <0 0x10206000 0 0x1000>;
498 #address-cells = <1>;
500 thermal_calibration: calib@528 {
505 apmixedsys: clock-controller@10209000 {
506 compatible = "mediatek,mt8173-apmixedsys";
507 reg = <0 0x10209000 0 0x1000>;
511 hdmi_phy: hdmi-phy@10209100 {
512 compatible = "mediatek,mt8173-hdmi-phy";
513 reg = <0 0x10209100 0 0x24>;
514 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
515 clock-names = "pll_ref";
516 clock-output-names = "hdmitx_dig_cts";
517 mediatek,ibias = <0xa>;
518 mediatek,ibias_up = <0x1c>;
524 mipi_tx0: mipi-dphy@10215000 {
525 compatible = "mediatek,mt8173-mipi-tx";
526 reg = <0 0x10215000 0 0x1000>;
528 clock-output-names = "mipi_tx0_pll";
534 mipi_tx1: mipi-dphy@10216000 {
535 compatible = "mediatek,mt8173-mipi-tx";
536 reg = <0 0x10216000 0 0x1000>;
538 clock-output-names = "mipi_tx1_pll";
544 gic: interrupt-controller@10221000 {
545 compatible = "arm,gic-400";
546 #interrupt-cells = <3>;
547 interrupt-parent = <&gic>;
548 interrupt-controller;
549 reg = <0 0x10221000 0 0x1000>,
550 <0 0x10222000 0 0x2000>,
551 <0 0x10224000 0 0x2000>,
552 <0 0x10226000 0 0x2000>;
553 interrupts = <GIC_PPI 9
554 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
557 auxadc: auxadc@11001000 {
558 compatible = "mediatek,mt8173-auxadc";
559 reg = <0 0x11001000 0 0x1000>;
560 clocks = <&pericfg CLK_PERI_AUXADC>;
561 clock-names = "main";
562 #io-channel-cells = <1>;
565 uart0: serial@11002000 {
566 compatible = "mediatek,mt8173-uart",
567 "mediatek,mt6577-uart";
568 reg = <0 0x11002000 0 0x400>;
569 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
570 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
571 clock-names = "baud", "bus";
575 uart1: serial@11003000 {
576 compatible = "mediatek,mt8173-uart",
577 "mediatek,mt6577-uart";
578 reg = <0 0x11003000 0 0x400>;
579 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
580 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
581 clock-names = "baud", "bus";
585 uart2: serial@11004000 {
586 compatible = "mediatek,mt8173-uart",
587 "mediatek,mt6577-uart";
588 reg = <0 0x11004000 0 0x400>;
589 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
590 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
591 clock-names = "baud", "bus";
595 uart3: serial@11005000 {
596 compatible = "mediatek,mt8173-uart",
597 "mediatek,mt6577-uart";
598 reg = <0 0x11005000 0 0x400>;
599 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
600 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
601 clock-names = "baud", "bus";
606 compatible = "mediatek,mt8173-i2c";
607 reg = <0 0x11007000 0 0x70>,
608 <0 0x11000100 0 0x80>;
609 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
611 clocks = <&pericfg CLK_PERI_I2C0>,
612 <&pericfg CLK_PERI_AP_DMA>;
613 clock-names = "main", "dma";
614 pinctrl-names = "default";
615 pinctrl-0 = <&i2c0_pins_a>;
616 #address-cells = <1>;
622 compatible = "mediatek,mt8173-i2c";
623 reg = <0 0x11008000 0 0x70>,
624 <0 0x11000180 0 0x80>;
625 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
627 clocks = <&pericfg CLK_PERI_I2C1>,
628 <&pericfg CLK_PERI_AP_DMA>;
629 clock-names = "main", "dma";
630 pinctrl-names = "default";
631 pinctrl-0 = <&i2c1_pins_a>;
632 #address-cells = <1>;
638 compatible = "mediatek,mt8173-i2c";
639 reg = <0 0x11009000 0 0x70>,
640 <0 0x11000200 0 0x80>;
641 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
643 clocks = <&pericfg CLK_PERI_I2C2>,
644 <&pericfg CLK_PERI_AP_DMA>;
645 clock-names = "main", "dma";
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2c2_pins_a>;
648 #address-cells = <1>;
654 compatible = "mediatek,mt8173-spi";
655 #address-cells = <1>;
657 reg = <0 0x1100a000 0 0x1000>;
658 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
659 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
660 <&topckgen CLK_TOP_SPI_SEL>,
661 <&pericfg CLK_PERI_SPI0>;
662 clock-names = "parent-clk", "sel-clk", "spi-clk";
666 thermal: thermal@1100b000 {
667 #thermal-sensor-cells = <0>;
668 compatible = "mediatek,mt8173-thermal";
669 reg = <0 0x1100b000 0 0x1000>;
670 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
671 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
672 clock-names = "therm", "auxadc";
673 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
674 mediatek,auxadc = <&auxadc>;
675 mediatek,apmixedsys = <&apmixedsys>;
676 nvmem-cells = <&thermal_calibration>;
677 nvmem-cell-names = "calibration-data";
680 nor_flash: spi@1100d000 {
681 compatible = "mediatek,mt8173-nor";
682 reg = <0 0x1100d000 0 0xe0>;
683 clocks = <&pericfg CLK_PERI_SPI>,
684 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
685 clock-names = "spi", "sf";
686 #address-cells = <1>;
692 compatible = "mediatek,mt8173-i2c";
693 reg = <0 0x11010000 0 0x70>,
694 <0 0x11000280 0 0x80>;
695 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
697 clocks = <&pericfg CLK_PERI_I2C3>,
698 <&pericfg CLK_PERI_AP_DMA>;
699 clock-names = "main", "dma";
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2c3_pins_a>;
702 #address-cells = <1>;
708 compatible = "mediatek,mt8173-i2c";
709 reg = <0 0x11011000 0 0x70>,
710 <0 0x11000300 0 0x80>;
711 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
713 clocks = <&pericfg CLK_PERI_I2C4>,
714 <&pericfg CLK_PERI_AP_DMA>;
715 clock-names = "main", "dma";
716 pinctrl-names = "default";
717 pinctrl-0 = <&i2c4_pins_a>;
718 #address-cells = <1>;
723 hdmiddc0: i2c@11012000 {
724 compatible = "mediatek,mt8173-hdmi-ddc";
725 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
726 reg = <0 0x11012000 0 0x1C>;
727 clocks = <&pericfg CLK_PERI_I2C5>;
728 clock-names = "ddc-i2c";
732 compatible = "mediatek,mt8173-i2c";
733 reg = <0 0x11013000 0 0x70>,
734 <0 0x11000080 0 0x80>;
735 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
737 clocks = <&pericfg CLK_PERI_I2C6>,
738 <&pericfg CLK_PERI_AP_DMA>;
739 clock-names = "main", "dma";
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c6_pins_a>;
742 #address-cells = <1>;
747 afe: audio-controller@11220000 {
748 compatible = "mediatek,mt8173-afe-pcm";
749 reg = <0 0x11220000 0 0x1000>;
750 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
751 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
752 clocks = <&infracfg CLK_INFRA_AUDIO>,
753 <&topckgen CLK_TOP_AUDIO_SEL>,
754 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
755 <&topckgen CLK_TOP_APLL1_DIV0>,
756 <&topckgen CLK_TOP_APLL2_DIV0>,
757 <&topckgen CLK_TOP_I2S0_M_SEL>,
758 <&topckgen CLK_TOP_I2S1_M_SEL>,
759 <&topckgen CLK_TOP_I2S2_M_SEL>,
760 <&topckgen CLK_TOP_I2S3_M_SEL>,
761 <&topckgen CLK_TOP_I2S3_B_SEL>;
762 clock-names = "infra_sys_audio_clk",
764 "top_pdn_aud_intbus",
772 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
773 <&topckgen CLK_TOP_AUD_2_SEL>;
774 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
775 <&topckgen CLK_TOP_APLL2>;
779 compatible = "mediatek,mt8173-mmc";
780 reg = <0 0x11230000 0 0x1000>;
781 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
782 clocks = <&pericfg CLK_PERI_MSDC30_0>,
783 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
784 clock-names = "source", "hclk";
789 compatible = "mediatek,mt8173-mmc";
790 reg = <0 0x11240000 0 0x1000>;
791 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
792 clocks = <&pericfg CLK_PERI_MSDC30_1>,
793 <&topckgen CLK_TOP_AXI_SEL>;
794 clock-names = "source", "hclk";
799 compatible = "mediatek,mt8173-mmc";
800 reg = <0 0x11250000 0 0x1000>;
801 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
802 clocks = <&pericfg CLK_PERI_MSDC30_2>,
803 <&topckgen CLK_TOP_AXI_SEL>;
804 clock-names = "source", "hclk";
809 compatible = "mediatek,mt8173-mmc";
810 reg = <0 0x11260000 0 0x1000>;
811 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
812 clocks = <&pericfg CLK_PERI_MSDC30_3>,
813 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
814 clock-names = "source", "hclk";
818 ssusb: usb@11271000 {
819 compatible = "mediatek,mt8173-mtu3";
820 reg = <0 0x11271000 0 0x3000>,
821 <0 0x11280700 0 0x0100>;
822 reg-names = "mac", "ippc";
823 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
824 phys = <&u2port0 PHY_TYPE_USB2>,
825 <&u3port0 PHY_TYPE_USB3>,
826 <&u2port1 PHY_TYPE_USB2>;
827 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
828 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
829 clock-names = "sys_ck", "ref_ck";
830 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
831 #address-cells = <2>;
836 usb_host: xhci@11270000 {
837 compatible = "mediatek,mt8173-xhci";
838 reg = <0 0x11270000 0 0x1000>;
840 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
841 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
842 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
843 clock-names = "sys_ck", "ref_ck";
848 u3phy: usb-phy@11290000 {
849 compatible = "mediatek,mt8173-u3phy";
850 reg = <0 0x11290000 0 0x800>;
851 #address-cells = <2>;
856 u2port0: usb-phy@11290800 {
857 reg = <0 0x11290800 0 0x100>;
858 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
864 u3port0: usb-phy@11290900 {
865 reg = <0 0x11290900 0 0x700>;
872 u2port1: usb-phy@11291000 {
873 reg = <0 0x11291000 0 0x100>;
874 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
881 mmsys: clock-controller@14000000 {
882 compatible = "mediatek,mt8173-mmsys", "syscon";
883 reg = <0 0x14000000 0 0x1000>;
884 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
885 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
886 assigned-clock-rates = <400000000>;
890 mdp_rdma0: rdma@14001000 {
891 compatible = "mediatek,mt8173-mdp-rdma",
892 "mediatek,mt8173-mdp";
893 reg = <0 0x14001000 0 0x1000>;
894 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
895 <&mmsys CLK_MM_MUTEX_32K>;
896 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
897 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
898 mediatek,larb = <&larb0>;
899 mediatek,vpu = <&vpu>;
902 mdp_rdma1: rdma@14002000 {
903 compatible = "mediatek,mt8173-mdp-rdma";
904 reg = <0 0x14002000 0 0x1000>;
905 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
906 <&mmsys CLK_MM_MUTEX_32K>;
907 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
908 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
909 mediatek,larb = <&larb4>;
912 mdp_rsz0: rsz@14003000 {
913 compatible = "mediatek,mt8173-mdp-rsz";
914 reg = <0 0x14003000 0 0x1000>;
915 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
916 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
919 mdp_rsz1: rsz@14004000 {
920 compatible = "mediatek,mt8173-mdp-rsz";
921 reg = <0 0x14004000 0 0x1000>;
922 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
923 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
926 mdp_rsz2: rsz@14005000 {
927 compatible = "mediatek,mt8173-mdp-rsz";
928 reg = <0 0x14005000 0 0x1000>;
929 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
930 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
933 mdp_wdma0: wdma@14006000 {
934 compatible = "mediatek,mt8173-mdp-wdma";
935 reg = <0 0x14006000 0 0x1000>;
936 clocks = <&mmsys CLK_MM_MDP_WDMA>;
937 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
938 iommus = <&iommu M4U_PORT_MDP_WDMA>;
939 mediatek,larb = <&larb0>;
942 mdp_wrot0: wrot@14007000 {
943 compatible = "mediatek,mt8173-mdp-wrot";
944 reg = <0 0x14007000 0 0x1000>;
945 clocks = <&mmsys CLK_MM_MDP_WROT0>;
946 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
947 iommus = <&iommu M4U_PORT_MDP_WROT0>;
948 mediatek,larb = <&larb0>;
951 mdp_wrot1: wrot@14008000 {
952 compatible = "mediatek,mt8173-mdp-wrot";
953 reg = <0 0x14008000 0 0x1000>;
954 clocks = <&mmsys CLK_MM_MDP_WROT1>;
955 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
956 iommus = <&iommu M4U_PORT_MDP_WROT1>;
957 mediatek,larb = <&larb4>;
961 compatible = "mediatek,mt8173-disp-ovl";
962 reg = <0 0x1400c000 0 0x1000>;
963 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
964 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
965 clocks = <&mmsys CLK_MM_DISP_OVL0>;
966 iommus = <&iommu M4U_PORT_DISP_OVL0>;
967 mediatek,larb = <&larb0>;
971 compatible = "mediatek,mt8173-disp-ovl";
972 reg = <0 0x1400d000 0 0x1000>;
973 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
974 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
975 clocks = <&mmsys CLK_MM_DISP_OVL1>;
976 iommus = <&iommu M4U_PORT_DISP_OVL1>;
977 mediatek,larb = <&larb4>;
980 rdma0: rdma@1400e000 {
981 compatible = "mediatek,mt8173-disp-rdma";
982 reg = <0 0x1400e000 0 0x1000>;
983 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
984 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
985 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
986 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
987 mediatek,larb = <&larb0>;
990 rdma1: rdma@1400f000 {
991 compatible = "mediatek,mt8173-disp-rdma";
992 reg = <0 0x1400f000 0 0x1000>;
993 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
994 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
995 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
996 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
997 mediatek,larb = <&larb4>;
1000 rdma2: rdma@14010000 {
1001 compatible = "mediatek,mt8173-disp-rdma";
1002 reg = <0 0x14010000 0 0x1000>;
1003 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1004 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1005 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1006 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1007 mediatek,larb = <&larb4>;
1010 wdma0: wdma@14011000 {
1011 compatible = "mediatek,mt8173-disp-wdma";
1012 reg = <0 0x14011000 0 0x1000>;
1013 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1014 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1015 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1016 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1017 mediatek,larb = <&larb0>;
1020 wdma1: wdma@14012000 {
1021 compatible = "mediatek,mt8173-disp-wdma";
1022 reg = <0 0x14012000 0 0x1000>;
1023 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1024 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1025 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1026 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1027 mediatek,larb = <&larb4>;
1030 color0: color@14013000 {
1031 compatible = "mediatek,mt8173-disp-color";
1032 reg = <0 0x14013000 0 0x1000>;
1033 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1034 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1035 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1038 color1: color@14014000 {
1039 compatible = "mediatek,mt8173-disp-color";
1040 reg = <0 0x14014000 0 0x1000>;
1041 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1042 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1043 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1047 compatible = "mediatek,mt8173-disp-aal";
1048 reg = <0 0x14015000 0 0x1000>;
1049 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1050 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1051 clocks = <&mmsys CLK_MM_DISP_AAL>;
1055 compatible = "mediatek,mt8173-disp-gamma";
1056 reg = <0 0x14016000 0 0x1000>;
1057 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1058 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1059 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1063 compatible = "mediatek,mt8173-disp-merge";
1064 reg = <0 0x14017000 0 0x1000>;
1065 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1066 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1069 split0: split@14018000 {
1070 compatible = "mediatek,mt8173-disp-split";
1071 reg = <0 0x14018000 0 0x1000>;
1072 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1073 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1076 split1: split@14019000 {
1077 compatible = "mediatek,mt8173-disp-split";
1078 reg = <0 0x14019000 0 0x1000>;
1079 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1080 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1084 compatible = "mediatek,mt8173-disp-ufoe";
1085 reg = <0 0x1401a000 0 0x1000>;
1086 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1087 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1088 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1091 dsi0: dsi@1401b000 {
1092 compatible = "mediatek,mt8173-dsi";
1093 reg = <0 0x1401b000 0 0x1000>;
1094 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1095 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1096 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1097 <&mmsys CLK_MM_DSI0_DIGITAL>,
1099 clock-names = "engine", "digital", "hs";
1102 status = "disabled";
1105 dsi1: dsi@1401c000 {
1106 compatible = "mediatek,mt8173-dsi";
1107 reg = <0 0x1401c000 0 0x1000>;
1108 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1109 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1110 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1111 <&mmsys CLK_MM_DSI1_DIGITAL>,
1113 clock-names = "engine", "digital", "hs";
1116 status = "disabled";
1119 dpi0: dpi@1401d000 {
1120 compatible = "mediatek,mt8173-dpi";
1121 reg = <0 0x1401d000 0 0x1000>;
1122 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1123 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1124 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1125 <&mmsys CLK_MM_DPI_ENGINE>,
1126 <&apmixedsys CLK_APMIXED_TVDPLL>;
1127 clock-names = "pixel", "engine", "pll";
1128 status = "disabled";
1131 dpi0_out: endpoint {
1132 remote-endpoint = <&hdmi0_in>;
1137 pwm0: pwm@1401e000 {
1138 compatible = "mediatek,mt8173-disp-pwm",
1139 "mediatek,mt6595-disp-pwm";
1140 reg = <0 0x1401e000 0 0x1000>;
1142 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1143 <&mmsys CLK_MM_DISP_PWM0MM>;
1144 clock-names = "main", "mm";
1145 status = "disabled";
1148 pwm1: pwm@1401f000 {
1149 compatible = "mediatek,mt8173-disp-pwm",
1150 "mediatek,mt6595-disp-pwm";
1151 reg = <0 0x1401f000 0 0x1000>;
1153 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1154 <&mmsys CLK_MM_DISP_PWM1MM>;
1155 clock-names = "main", "mm";
1156 status = "disabled";
1159 mutex: mutex@14020000 {
1160 compatible = "mediatek,mt8173-disp-mutex";
1161 reg = <0 0x14020000 0 0x1000>;
1162 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1163 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1164 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1167 larb0: larb@14021000 {
1168 compatible = "mediatek,mt8173-smi-larb";
1169 reg = <0 0x14021000 0 0x1000>;
1170 mediatek,smi = <&smi_common>;
1171 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1172 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1173 <&mmsys CLK_MM_SMI_LARB0>;
1174 clock-names = "apb", "smi";
1177 smi_common: smi@14022000 {
1178 compatible = "mediatek,mt8173-smi-common";
1179 reg = <0 0x14022000 0 0x1000>;
1180 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1181 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1182 <&mmsys CLK_MM_SMI_COMMON>;
1183 clock-names = "apb", "smi";
1187 compatible = "mediatek,mt8173-disp-od";
1188 reg = <0 0x14023000 0 0x1000>;
1189 clocks = <&mmsys CLK_MM_DISP_OD>;
1192 hdmi0: hdmi@14025000 {
1193 compatible = "mediatek,mt8173-hdmi";
1194 reg = <0 0x14025000 0 0x400>;
1195 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1196 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1197 <&mmsys CLK_MM_HDMI_PLLCK>,
1198 <&mmsys CLK_MM_HDMI_AUDIO>,
1199 <&mmsys CLK_MM_HDMI_SPDIF>;
1200 clock-names = "pixel", "pll", "bclk", "spdif";
1201 pinctrl-names = "default";
1202 pinctrl-0 = <&hdmi_pin>;
1205 mediatek,syscon-hdmi = <&mmsys 0x900>;
1206 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1207 assigned-clock-parents = <&hdmi_phy>;
1208 status = "disabled";
1211 #address-cells = <1>;
1217 hdmi0_in: endpoint {
1218 remote-endpoint = <&dpi0_out>;
1224 larb4: larb@14027000 {
1225 compatible = "mediatek,mt8173-smi-larb";
1226 reg = <0 0x14027000 0 0x1000>;
1227 mediatek,smi = <&smi_common>;
1228 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1229 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1230 <&mmsys CLK_MM_SMI_LARB4>;
1231 clock-names = "apb", "smi";
1234 imgsys: clock-controller@15000000 {
1235 compatible = "mediatek,mt8173-imgsys", "syscon";
1236 reg = <0 0x15000000 0 0x1000>;
1240 larb2: larb@15001000 {
1241 compatible = "mediatek,mt8173-smi-larb";
1242 reg = <0 0x15001000 0 0x1000>;
1243 mediatek,smi = <&smi_common>;
1244 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1245 clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1246 <&imgsys CLK_IMG_LARB2_SMI>;
1247 clock-names = "apb", "smi";
1250 vdecsys: clock-controller@16000000 {
1251 compatible = "mediatek,mt8173-vdecsys", "syscon";
1252 reg = <0 0x16000000 0 0x1000>;
1256 vcodec_dec: vcodec@16000000 {
1257 compatible = "mediatek,mt8173-vcodec-dec";
1258 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1259 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1260 <0 0x16021000 0 0x800>, /* VDEC_LD */
1261 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1262 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1263 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1264 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1265 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1266 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1267 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1268 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1269 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1270 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1271 mediatek,larb = <&larb1>;
1272 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1273 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1274 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1275 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1276 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1277 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1278 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1279 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1280 mediatek,vpu = <&vpu>;
1281 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1282 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1283 <&topckgen CLK_TOP_UNIVPLL_D2>,
1284 <&topckgen CLK_TOP_CCI400_SEL>,
1285 <&topckgen CLK_TOP_VDEC_SEL>,
1286 <&topckgen CLK_TOP_VCODECPLL>,
1287 <&apmixedsys CLK_APMIXED_VENCPLL>,
1288 <&topckgen CLK_TOP_VENC_LT_SEL>,
1289 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1290 clock-names = "vcodecpll",
1300 larb1: larb@16010000 {
1301 compatible = "mediatek,mt8173-smi-larb";
1302 reg = <0 0x16010000 0 0x1000>;
1303 mediatek,smi = <&smi_common>;
1304 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1305 clocks = <&vdecsys CLK_VDEC_CKEN>,
1306 <&vdecsys CLK_VDEC_LARB_CKEN>;
1307 clock-names = "apb", "smi";
1310 vencsys: clock-controller@18000000 {
1311 compatible = "mediatek,mt8173-vencsys", "syscon";
1312 reg = <0 0x18000000 0 0x1000>;
1316 larb3: larb@18001000 {
1317 compatible = "mediatek,mt8173-smi-larb";
1318 reg = <0 0x18001000 0 0x1000>;
1319 mediatek,smi = <&smi_common>;
1320 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1321 clocks = <&vencsys CLK_VENC_CKE1>,
1322 <&vencsys CLK_VENC_CKE0>;
1323 clock-names = "apb", "smi";
1326 vcodec_enc: vcodec@18002000 {
1327 compatible = "mediatek,mt8173-vcodec-enc";
1328 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
1329 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1330 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1331 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1332 mediatek,larb = <&larb3>,
1334 iommus = <&iommu M4U_PORT_VENC_RCPU>,
1335 <&iommu M4U_PORT_VENC_REC>,
1336 <&iommu M4U_PORT_VENC_BSDMA>,
1337 <&iommu M4U_PORT_VENC_SV_COMV>,
1338 <&iommu M4U_PORT_VENC_RD_COMV>,
1339 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1340 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1341 <&iommu M4U_PORT_VENC_REF_LUMA>,
1342 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1343 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1344 <&iommu M4U_PORT_VENC_NBM_WDMA>,
1345 <&iommu M4U_PORT_VENC_RCPU_SET2>,
1346 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1347 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1348 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1349 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1350 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1351 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1352 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1353 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1354 mediatek,vpu = <&vpu>;
1355 clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1356 <&topckgen CLK_TOP_VENC_SEL>,
1357 <&topckgen CLK_TOP_UNIVPLL1_D2>,
1358 <&topckgen CLK_TOP_VENC_LT_SEL>;
1359 clock-names = "venc_sel_src",
1365 vencltsys: clock-controller@19000000 {
1366 compatible = "mediatek,mt8173-vencltsys", "syscon";
1367 reg = <0 0x19000000 0 0x1000>;
1371 larb5: larb@19001000 {
1372 compatible = "mediatek,mt8173-smi-larb";
1373 reg = <0 0x19001000 0 0x1000>;
1374 mediatek,smi = <&smi_common>;
1375 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1376 clocks = <&vencltsys CLK_VENCLT_CKE1>,
1377 <&vencltsys CLK_VENCLT_CKE0>;
1378 clock-names = "apb", "smi";