1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7986b.dtsi"
11 model = "MediaTek MT7986b RFB";
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
24 device_type = "memory";
25 reg = <0 0x40000000 0 0x40000000>;
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
53 compatible = "mediatek,mt7531";
55 reset-gpios = <&pio 5 0>;
90 phy-mode = "2500base-x";
104 spi_flash_pins: spi-flash-pins {
107 groups = "spi0", "spi0_wp_hold";
111 spic_pins: spic-pins {
118 wf_2g_5g_pins: wf-2g-5g-pins {
121 groups = "wf_2g", "wf_5g";
124 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
125 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
126 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
127 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
128 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
129 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
130 "WF1_TOP_CLK", "WF1_TOP_DATA";
131 drive-strength = <4>;
135 wf_dbdc_pins: wf-dbdc-pins {
141 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
142 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
143 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
144 "WF0_TOP_CLK", "WF0_TOP_DATA";
145 drive-strength = <4>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&spi_flash_pins>;
155 spi_nand: spi_nand@0 {
156 compatible = "spi-nand";
158 spi-max-frequency = <10000000>;
159 spi-tx-buswidth = <4>;
160 spi-rx-buswidth = <4>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&spic_pins>;
185 pinctrl-names = "default", "dbdc";
186 pinctrl-0 = <&wf_2g_5g_pins>;
187 pinctrl-1 = <&wf_dbdc_pins>;