1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7986b.dtsi"
11 model = "MediaTek MT7986b RFB";
12 compatible = "mediatek,mt7986b-rfb";
19 stdout-path = "serial0:115200n8";
23 device_type = "memory";
24 reg = <0 0x40000000 0 0x40000000>;
36 compatible = "mediatek,eth-mac";
38 phy-mode = "2500base-x";
52 compatible = "mediatek,mt7531";
54 reset-gpios = <&pio 5 0>;
89 phy-mode = "2500base-x";
104 pinctrl-names = "default", "dbdc";
105 pinctrl-0 = <&wf_2g_5g_pins>;
106 pinctrl-1 = <&wf_dbdc_pins>;
110 wf_2g_5g_pins: wf-2g-5g-pins {
113 groups = "wf_2g", "wf_5g";
116 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
117 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
118 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
119 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
120 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
121 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
122 "WF1_TOP_CLK", "WF1_TOP_DATA";
123 drive-strength = <4>;
127 wf_dbdc_pins: wf-dbdc-pins {
133 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
134 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
135 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
136 "WF0_TOP_CLK", "WF0_TOP_DATA";
137 drive-strength = <4>;