arch/arm64/boot/dts/mediatek/mt7986a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2021 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7986-clk.h>
  10 #include <dt-bindings/reset/mt7986-resets.h>
  11
  12 / {
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         clk40m: oscillator-40m {
  18                 compatible = "fixed-clock";
  19                 clock-frequency = <40000000>;
  20                 #clock-cells = <0>;
  21                 clock-output-names = "clkxtal";
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 cpu0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53";
  30                         enable-method = "psci";
  31                         reg = <0x0>;
  32                         #cooling-cells = <2>;
  33                 };
  34
  35                 cpu1: cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         enable-method = "psci";
  39                         reg = <0x1>;
  40                         #cooling-cells = <2>;
  41                 };
  42
  43                 cpu2: cpu@2 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53";
  46                         enable-method = "psci";
  47                         reg = <0x2>;
  48                         #cooling-cells = <2>;
  49                 };
  50
  51                 cpu3: cpu@3 {
  52                         device_type = "cpu";
  53                         enable-method = "psci";
  54                         compatible = "arm,cortex-a53";
  55                         reg = <0x3>;
  56                         #cooling-cells = <2>;
  57                 };
  58         };
  59
  60         psci {
  61                 compatible = "arm,psci-0.2";
  62                 method = "smc";
  63         };
  64
  65         reserved-memory {
  66                 #address-cells = <2>;
  67                 #size-cells = <2>;
  68                 ranges;
  69                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
  70                 secmon_reserved: secmon@43000000 {
  71                         reg = <0 0x43000000 0 0x30000>;
  72                         no-map;
  73                 };
  74
  75                 wmcpu_emi: wmcpu-reserved@4fc00000 {
  76                         no-map;
  77                         reg = <0 0x4fc00000 0 0x00100000>;
  78                 };
  79         };
  80
  81         timer {
  82                 compatible = "arm,armv8-timer";
  83                 interrupt-parent = <&gic>;
  84                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  85                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  86                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  87                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  88         };
  89
  90         soc {
  91                 #address-cells = <2>;
  92                 #size-cells = <2>;
  93                 compatible = "simple-bus";
  94                 ranges;
  95
  96                 gic: interrupt-controller@c000000 {
  97                         compatible = "arm,gic-v3";
  98                         #interrupt-cells = <3>;
  99                         interrupt-parent = <&gic>;
 100                         interrupt-controller;
 101                         reg = <0 0x0c000000 0 0x10000>,  /* GICD */
 102                               <0 0x0c080000 0 0x80000>,  /* GICR */
 103                               <0 0x0c400000 0 0x2000>,   /* GICC */
 104                               <0 0x0c410000 0 0x1000>,   /* GICH */
 105                               <0 0x0c420000 0 0x2000>;   /* GICV */
 106                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 107                 };
 108
 109                 infracfg: infracfg@10001000 {
 110                         compatible = "mediatek,mt7986-infracfg", "syscon";
 111                         reg = <0 0x10001000 0 0x1000>;
 112                         #clock-cells = <1>;
 113                         #reset-cells = <1>;
 114                 };
 115
 116                 wed_pcie: wed-pcie@10003000 {
 117                         compatible = "mediatek,mt7986-wed-pcie",
 118                                      "syscon";
 119                         reg = <0 0x10003000 0 0x10>;
 120                 };
 121
 122                 topckgen: topckgen@1001b000 {
 123                         compatible = "mediatek,mt7986-topckgen", "syscon";
 124                         reg = <0 0x1001B000 0 0x1000>;
 125                         #clock-cells = <1>;
 126                 };
 127
 128                 watchdog: watchdog@1001c000 {
 129                         compatible = "mediatek,mt7986-wdt";
 130                         reg = <0 0x1001c000 0 0x1000>;
 131                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 132                         #reset-cells = <1>;
 133                         status = "disabled";
 134                 };
 135
 136                 apmixedsys: apmixedsys@1001e000 {
 137                         compatible = "mediatek,mt7986-apmixedsys";
 138                         reg = <0 0x1001E000 0 0x1000>;
 139                         #clock-cells = <1>;
 140                 };
 141
 142                 pio: pinctrl@1001f000 {
 143                         compatible = "mediatek,mt7986a-pinctrl";
 144                         reg = <0 0x1001f000 0 0x1000>,
 145                               <0 0x11c30000 0 0x1000>,
 146                               <0 0x11c40000 0 0x1000>,
 147                               <0 0x11e20000 0 0x1000>,
 148                               <0 0x11e30000 0 0x1000>,
 149                               <0 0x11f00000 0 0x1000>,
 150                               <0 0x11f10000 0 0x1000>,
 151                               <0 0x1000b000 0 0x1000>;
 152                         reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
 153                                     "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
 154                         gpio-controller;
 155                         #gpio-cells = <2>;
 156                         gpio-ranges = <&pio 0 0 100>;
 157                         interrupt-controller;
 158                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 159                         interrupt-parent = <&gic>;
 160                         #interrupt-cells = <2>;
 161                 };
 162
 163                 sgmiisys0: syscon@10060000 {
 164                         compatible = "mediatek,mt7986-sgmiisys_0",
 165                                      "syscon";
 166                         reg = <0 0x10060000 0 0x1000>;
 167                         #clock-cells = <1>;
 168                 };
 169
 170                 sgmiisys1: syscon@10070000 {
 171                         compatible = "mediatek,mt7986-sgmiisys_1",
 172                                      "syscon";
 173                         reg = <0 0x10070000 0 0x1000>;
 174                         #clock-cells = <1>;
 175                 };
 176
 177                 trng: rng@1020f000 {
 178                         compatible = "mediatek,mt7986-rng",
 179                                      "mediatek,mt7623-rng";
 180                         reg = <0 0x1020f000 0 0x100>;
 181                         clocks = <&infracfg CLK_INFRA_TRNG_CK>;
 182                         clock-names = "rng";
 183                         status = "disabled";
 184                 };
 185
 186                 uart0: serial@11002000 {
 187                         compatible = "mediatek,mt7986-uart",
 188                                      "mediatek,mt6577-uart";
 189                         reg = <0 0x11002000 0 0x400>;
 190                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 192                                  <&infracfg CLK_INFRA_UART0_CK>;
 193                         clock-names = "baud", "bus";
 194                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 195                                           <&infracfg CLK_INFRA_UART0_SEL>;
 196                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 197                                                  <&topckgen CLK_TOP_UART_SEL>;
 198                         status = "disabled";
 199                 };
 200
 201                 uart1: serial@11003000 {
 202                         compatible = "mediatek,mt7986-uart",
 203                                      "mediatek,mt6577-uart";
 204                         reg = <0 0x11003000 0 0x400>;
 205                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 206                         clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 207                                  <&infracfg CLK_INFRA_UART1_CK>;
 208                         clock-names = "baud", "bus";
 209                         assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
 210                         assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 211                         status = "disabled";
 212                 };
 213
 214                 uart2: serial@11004000 {
 215                         compatible = "mediatek,mt7986-uart",
 216                                      "mediatek,mt6577-uart";
 217                         reg = <0 0x11004000 0 0x400>;
 218                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 220                                  <&infracfg CLK_INFRA_UART2_CK>;
 221                         clock-names = "baud", "bus";
 222                         assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
 223                         assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 224                         status = "disabled";
 225                 };
 226
 227                 ethsys: syscon@15000000 {
 228                          #address-cells = <1>;
 229                          #size-cells = <1>;
 230                          compatible = "mediatek,mt7986-ethsys",
 231                                       "syscon";
 232                          reg = <0 0x15000000 0 0x1000>;
 233                          #clock-cells = <1>;
 234                          #reset-cells = <1>;
 235                 };
 236
 237                 wed0: wed@15010000 {
 238                         compatible = "mediatek,mt7986-wed",
 239                                      "syscon";
 240                         reg = <0 0x15010000 0 0x1000>;
 241                         interrupt-parent = <&gic>;
 242                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 243                 };
 244
 245                 wed1: wed@15011000 {
 246                         compatible = "mediatek,mt7986-wed",
 247                                      "syscon";
 248                         reg = <0 0x15011000 0 0x1000>;
 249                         interrupt-parent = <&gic>;
 250                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 251                 };
 252
 253                 eth: ethernet@15100000 {
 254                         compatible = "mediatek,mt7986-eth";
 255                         reg = <0 0x15100000 0 0x80000>;
 256                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 258                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 259                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 260                         clocks = <&ethsys CLK_ETH_FE_EN>,
 261                                  <&ethsys CLK_ETH_GP2_EN>,
 262                                  <&ethsys CLK_ETH_GP1_EN>,
 263                                  <&ethsys CLK_ETH_WOCPU1_EN>,
 264                                  <&ethsys CLK_ETH_WOCPU0_EN>,
 265                                  <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
 266                                  <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
 267                                  <&sgmiisys0 CLK_SGMII0_CDR_REF>,
 268                                  <&sgmiisys0 CLK_SGMII0_CDR_FB>,
 269                                  <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
 270                                  <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
 271                                  <&sgmiisys1 CLK_SGMII1_CDR_REF>,
 272                                  <&sgmiisys1 CLK_SGMII1_CDR_FB>,
 273                                  <&topckgen CLK_TOP_NETSYS_SEL>,
 274                                  <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 275                         clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
 276                                       "sgmii_tx250m", "sgmii_rx250m",
 277                                       "sgmii_cdr_ref", "sgmii_cdr_fb",
 278                                       "sgmii2_tx250m", "sgmii2_rx250m",
 279                                       "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 280                                       "netsys0", "netsys1";
 281                         assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 282                                           <&topckgen CLK_TOP_SGM_325M_SEL>;
 283                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
 284                                                  <&apmixedsys CLK_APMIXED_SGMPLL>;
 285                         mediatek,ethsys = <&ethsys>;
 286                         mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 287                         mediatek,wed-pcie = <&wed_pcie>;
 288                         mediatek,wed = <&wed0>, <&wed1>;
 289                         #reset-cells = <1>;
 290                         #address-cells = <1>;
 291                         #size-cells = <0>;
 292                         status = "disabled";
 293                 };
 294
 295                 wifi: wifi@18000000 {
 296                         compatible = "mediatek,mt7986-wmac";
 297                         resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
 298                         reset-names = "consys";
 299                         clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
 300                                  <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 301                         clock-names = "mcu", "ap2conn";
 302                         reg = <0 0x18000000 0 0x1000000>,
 303                               <0 0x10003000 0 0x1000>,
 304                               <0 0x11d10000 0 0x1000>;
 305                         interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 309                         memory-region = <&wmcpu_emi>;
 310                 };
 311         };
 312
 313 };