1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include <dt-bindings/pinctrl/mt65xx.h>
10 #include "mt7986a.dtsi"
13 model = "MediaTek MT7986a RFB";
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
26 device_type = "memory";
27 reg = <0 0x40000000 0 0x40000000>;
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
39 reg_3p3v: regulator-3p3v {
40 compatible = "regulator-fixed";
41 regulator-name = "fixed-3.3V";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
57 compatible = "mediatek,eth-mac";
59 phy-mode = "2500base-x";
76 compatible = "mediatek,mt7531";
78 reset-gpios = <&pio 5 0>;
83 pinctrl-names = "default", "state_uhs";
84 pinctrl-0 = <&mmc0_pins_default>;
85 pinctrl-1 = <&mmc0_pins_uhs>;
87 max-frequency = <200000000>;
91 hs400-ds-delay = <0x14014>;
92 vmmc-supply = <®_3p3v>;
93 vqmmc-supply = <®_1p8v>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pcie_pins>;
110 mmc0_pins_default: mmc0-pins {
116 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
117 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
118 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
120 drive-strength = <4>;
121 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
125 drive-strength = <6>;
126 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
130 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
134 drive-strength = <4>;
135 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
139 mmc0_pins_uhs: mmc0-uhs-pins {
145 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
146 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
147 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
149 drive-strength = <4>;
150 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
154 drive-strength = <6>;
155 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
159 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
163 drive-strength = <4>;
164 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
168 pcie_pins: pcie-pins {
171 groups = "pcie_clk", "pcie_wake", "pcie_pereset";
175 spi_flash_pins: spi-flash-pins {
178 groups = "spi0", "spi0_wp_hold";
182 spic_pins: spic-pins {
189 uart1_pins: uart1-pins {
196 uart2_pins: uart2-pins {
203 wf_2g_5g_pins: wf-2g-5g-pins {
206 groups = "wf_2g", "wf_5g";
209 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
210 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
211 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
212 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
213 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
214 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
215 "WF1_TOP_CLK", "WF1_TOP_DATA";
216 drive-strength = <4>;
220 wf_dbdc_pins: wf-dbdc-pins {
226 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
227 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
228 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
229 "WF0_TOP_CLK", "WF0_TOP_DATA";
230 drive-strength = <4>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&spi_flash_pins>;
240 spi_nand: spi_nand@0 {
241 compatible = "spi-nand";
243 spi-max-frequency = <10000000>;
244 spi-tx-buswidth = <4>;
245 spi-rx-buswidth = <4>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&spic_pins>;
262 #address-cells = <1>;
294 phy-mode = "2500base-x";
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart1_pins>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&uart2_pins>;
327 pinctrl-names = "default", "dbdc";
328 pinctrl-0 = <&wf_2g_5g_pins>;
329 pinctrl-1 = <&wf_dbdc_pins>;