1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7986a.dtsi"
11 model = "MediaTek MT7986a RFB";
12 compatible = "mediatek,mt7986a-rfb";
19 stdout-path = "serial0:115200n8";
23 device_type = "memory";
24 reg = <0 0x40000000 0 0x40000000>;
32 compatible = "mediatek,eth-mac";
34 phy-mode = "2500base-x";
51 compatible = "mediatek,mt7531";
53 reset-gpios = <&pio 5 0>;
91 phy-mode = "2500base-x";
107 pinctrl-names = "default";
108 pinctrl-0 = <&uart1_pins>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&uart2_pins>;
120 pinctrl-names = "default", "dbdc";
121 pinctrl-0 = <&wf_2g_5g_pins>;
122 pinctrl-1 = <&wf_dbdc_pins>;
126 uart1_pins: uart1-pins {
133 uart2_pins: uart2-pins {
140 wf_2g_5g_pins: wf-2g-5g-pins {
143 groups = "wf_2g", "wf_5g";
146 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
147 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
148 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
149 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
150 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
151 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
152 "WF1_TOP_CLK", "WF1_TOP_DATA";
153 drive-strength = <4>;
157 wf_dbdc_pins: wf-dbdc-pins {
163 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
164 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
165 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
166 "WF0_TOP_CLK", "WF0_TOP_DATA";
167 drive-strength = <4>;