arch/arm64/boot/dts/mediatek/mt7622.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt7622-clk.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt7622-power.h>
  14 #include <dt-bindings/reset/mt7622-reset.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         compatible = "mediatek,mt7622";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpu_opp_table: opp-table {
  24                 compatible = "operating-points-v2";
  25                 opp-shared;
  26                 opp-300000000 {
  27                         opp-hz = /bits/ 64 <30000000>;
  28                         opp-microvolt = <950000>;
  29                 };
  30
  31                 opp-437500000 {
  32                         opp-hz = /bits/ 64 <437500000>;
  33                         opp-microvolt = <1000000>;
  34                 };
  35
  36                 opp-600000000 {
  37                         opp-hz = /bits/ 64 <600000000>;
  38                         opp-microvolt = <1050000>;
  39                 };
  40
  41                 opp-812500000 {
  42                         opp-hz = /bits/ 64 <812500000>;
  43                         opp-microvolt = <1100000>;
  44                 };
  45
  46                 opp-1025000000 {
  47                         opp-hz = /bits/ 64 <1025000000>;
  48                         opp-microvolt = <1150000>;
  49                 };
  50
  51                 opp-1137500000 {
  52                         opp-hz = /bits/ 64 <1137500000>;
  53                         opp-microvolt = <1200000>;
  54                 };
  55
  56                 opp-1262500000 {
  57                         opp-hz = /bits/ 64 <1262500000>;
  58                         opp-microvolt = <1250000>;
  59                 };
  60
  61                 opp-1350000000 {
  62                         opp-hz = /bits/ 64 <1350000000>;
  63                         opp-microvolt = <1310000>;
  64                 };
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x0 0x0>;
  75                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  76                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  77                         clock-names = "cpu", "intermediate";
  78                         operating-points-v2 = <&cpu_opp_table>;
  79                         #cooling-cells = <2>;
  80                         enable-method = "psci";
  81                         clock-frequency = <1300000000>;
  82                         cci-control-port = <&cci_control2>;
  83                         next-level-cache = <&L2>;
  84                 };
  85
  86                 cpu1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x0 0x1>;
  90                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  91                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  92                         clock-names = "cpu", "intermediate";
  93                         operating-points-v2 = <&cpu_opp_table>;
  94                         #cooling-cells = <2>;
  95                         enable-method = "psci";
  96                         clock-frequency = <1300000000>;
  97                         cci-control-port = <&cci_control2>;
  98                         next-level-cache = <&L2>;
  99                 };
 100
 101                 L2: l2-cache {
 102                         compatible = "cache";
 103                         cache-level = <2>;
 104                 };
 105         };
 106
 107         pwrap_clk: dummy40m {
 108                 compatible = "fixed-clock";
 109                 clock-frequency = <40000000>;
 110                 #clock-cells = <0>;
 111         };
 112
 113         clk25m: oscillator {
 114                 compatible = "fixed-clock";
 115                 #clock-cells = <0>;
 116                 clock-frequency = <25000000>;
 117                 clock-output-names = "clkxtal";
 118         };
 119
 120         psci {
 121                 compatible = "arm,psci-0.2";
 122                 method = "smc";
 123         };
 124
 125         pmu {
 126                 compatible = "arm,cortex-a53-pmu";
 127                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 128                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 129                 interrupt-affinity = <&cpu0>, <&cpu1>;
 130         };
 131
 132         reserved-memory {
 133                 #address-cells = <2>;
 134                 #size-cells = <2>;
 135                 ranges;
 136
 137                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 138                 secmon_reserved: secmon@43000000 {
 139                         reg = <0 0x43000000 0 0x30000>;
 140                         no-map;
 141                 };
 142         };
 143
 144         thermal-zones {
 145                 cpu_thermal: cpu-thermal {
 146                         polling-delay-passive = <1000>;
 147                         polling-delay = <1000>;
 148
 149                         thermal-sensors = <&thermal 0>;
 150
 151                         trips {
 152                                 cpu_passive: cpu-passive {
 153                                         temperature = <47000>;
 154                                         hysteresis = <2000>;
 155                                         type = "passive";
 156                                 };
 157
 158                                 cpu_active: cpu-active {
 159                                         temperature = <67000>;
 160                                         hysteresis = <2000>;
 161                                         type = "active";
 162                                 };
 163
 164                                 cpu_hot: cpu-hot {
 165                                         temperature = <87000>;
 166                                         hysteresis = <2000>;
 167                                         type = "hot";
 168                                 };
 169
 170                                 cpu-crit {
 171                                         temperature = <107000>;
 172                                         hysteresis = <2000>;
 173                                         type = "critical";
 174                                 };
 175                         };
 176
 177                         cooling-maps {
 178                                 map0 {
 179                                         trip = <&cpu_passive>;
 180                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 181                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 182                                 };
 183
 184                                 map1 {
 185                                         trip = <&cpu_active>;
 186                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 187                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 188                                 };
 189
 190                                 map2 {
 191                                         trip = <&cpu_hot>;
 192                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 193                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 194                                 };
 195                         };
 196                 };
 197         };
 198
 199         timer {
 200                 compatible = "arm,armv8-timer";
 201                 interrupt-parent = <&gic>;
 202                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 203                               IRQ_TYPE_LEVEL_HIGH)>,
 204                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 205                               IRQ_TYPE_LEVEL_HIGH)>,
 206                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 207                               IRQ_TYPE_LEVEL_HIGH)>,
 208                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 209                               IRQ_TYPE_LEVEL_HIGH)>;
 210         };
 211
 212         infracfg: infracfg@10000000 {
 213                 compatible = "mediatek,mt7622-infracfg",
 214                              "syscon";
 215                 reg = <0 0x10000000 0 0x1000>;
 216                 #clock-cells = <1>;
 217                 #reset-cells = <1>;
 218         };
 219
 220         pwrap: pwrap@10001000 {
 221                 compatible = "mediatek,mt7622-pwrap";
 222                 reg = <0 0x10001000 0 0x250>;
 223                 reg-names = "pwrap";
 224                 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
 225                 clock-names = "spi", "wrap";
 226                 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
 227                 reset-names = "pwrap";
 228                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 229                 status = "disabled";
 230         };
 231
 232         pericfg: pericfg@10002000 {
 233                 compatible = "mediatek,mt7622-pericfg",
 234                              "syscon";
 235                 reg = <0 0x10002000 0 0x1000>;
 236                 #clock-cells = <1>;
 237                 #reset-cells = <1>;
 238         };
 239
 240         scpsys: power-controller@10006000 {
 241                 compatible = "mediatek,mt7622-scpsys",
 242                              "syscon";
 243                 #power-domain-cells = <1>;
 244                 reg = <0 0x10006000 0 0x1000>;
 245                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 249                 infracfg = <&infracfg>;
 250                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 251                 clock-names = "hif_sel";
 252         };
 253
 254         cir: ir-receiver@10009000 {
 255                 compatible = "mediatek,mt7622-cir";
 256                 reg = <0 0x10009000 0 0x1000>;
 257                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
 258                 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
 259                          <&topckgen CLK_TOP_AXI_SEL>;
 260                 clock-names = "clk", "bus";
 261                 status = "disabled";
 262         };
 263
 264         sysirq: interrupt-controller@10200620 {
 265                 compatible = "mediatek,mt7622-sysirq",
 266                              "mediatek,mt6577-sysirq";
 267                 interrupt-controller;
 268                 #interrupt-cells = <3>;
 269                 interrupt-parent = <&gic>;
 270                 reg = <0 0x10200620 0 0x20>;
 271         };
 272
 273         efuse: efuse@10206000 {
 274                 compatible = "mediatek,mt7622-efuse",
 275                              "mediatek,efuse";
 276                 reg = <0 0x10206000 0 0x1000>;
 277                 #address-cells = <1>;
 278                 #size-cells = <1>;
 279
 280                 thermal_calibration: calib@198 {
 281                         reg = <0x198 0xc>;
 282                 };
 283         };
 284
 285         apmixedsys: clock-controller@10209000 {
 286                 compatible = "mediatek,mt7622-apmixedsys";
 287                 reg = <0 0x10209000 0 0x1000>;
 288                 #clock-cells = <1>;
 289         };
 290
 291         topckgen: clock-controller@10210000 {
 292                 compatible = "mediatek,mt7622-topckgen";
 293                 reg = <0 0x10210000 0 0x1000>;
 294                 #clock-cells = <1>;
 295         };
 296
 297         rng: rng@1020f000 {
 298                 compatible = "mediatek,mt7622-rng",
 299                              "mediatek,mt7623-rng";
 300                 reg = <0 0x1020f000 0 0x1000>;
 301                 clocks = <&infracfg CLK_INFRA_TRNG>;
 302                 clock-names = "rng";
 303         };
 304
 305         pio: pinctrl@10211000 {
 306                 compatible = "mediatek,mt7622-pinctrl";
 307                 reg = <0 0x10211000 0 0x1000>,
 308                       <0 0x10005000 0 0x1000>;
 309                 reg-names = "base", "eint";
 310                 gpio-controller;
 311                 #gpio-cells = <2>;
 312                 gpio-ranges = <&pio 0 0 103>;
 313                 interrupt-controller;
 314                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 315                 interrupt-parent = <&gic>;
 316                 #interrupt-cells = <2>;
 317         };
 318
 319         watchdog: watchdog@10212000 {
 320                 compatible = "mediatek,mt7622-wdt",
 321                              "mediatek,mt6589-wdt";
 322                 reg = <0 0x10212000 0 0x800>;
 323         };
 324
 325         rtc: rtc@10212800 {
 326                 compatible = "mediatek,mt7622-rtc",
 327                              "mediatek,soc-rtc";
 328                 reg = <0 0x10212800 0 0x200>;
 329                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 330                 clocks = <&topckgen CLK_TOP_RTC>;
 331                 clock-names = "rtc";
 332         };
 333
 334         gic: interrupt-controller@10300000 {
 335                 compatible = "arm,gic-400";
 336                 interrupt-controller;
 337                 #interrupt-cells = <3>;
 338                 interrupt-parent = <&gic>;
 339                 reg = <0 0x10310000 0 0x1000>,
 340                       <0 0x10320000 0 0x1000>,
 341                       <0 0x10340000 0 0x2000>,
 342                       <0 0x10360000 0 0x2000>;
 343         };
 344
 345         cci: cci@10390000 {
 346                 compatible = "arm,cci-400";
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349                 reg = <0 0x10390000 0 0x1000>;
 350                 ranges = <0 0 0x10390000 0x10000>;
 351
 352                 cci_control0: slave-if@1000 {
 353                         compatible = "arm,cci-400-ctrl-if";
 354                         interface-type = "ace-lite";
 355                         reg = <0x1000 0x1000>;
 356                 };
 357
 358                 cci_control1: slave-if@4000 {
 359                         compatible = "arm,cci-400-ctrl-if";
 360                         interface-type = "ace";
 361                         reg = <0x4000 0x1000>;
 362                 };
 363
 364                 cci_control2: slave-if@5000 {
 365                         compatible = "arm,cci-400-ctrl-if", "syscon";
 366                         interface-type = "ace";
 367                         reg = <0x5000 0x1000>;
 368                 };
 369
 370                 pmu@9000 {
 371                         compatible = "arm,cci-400-pmu,r1";
 372                         reg = <0x9000 0x5000>;
 373                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 374                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 375                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 376                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 377                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 378                 };
 379         };
 380
 381         auxadc: adc@11001000 {
 382                 compatible = "mediatek,mt7622-auxadc";
 383                 reg = <0 0x11001000 0 0x1000>;
 384                 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
 385                 clock-names = "main";
 386                 #io-channel-cells = <1>;
 387         };
 388
 389         uart0: serial@11002000 {
 390                 compatible = "mediatek,mt7622-uart",
 391                              "mediatek,mt6577-uart";
 392                 reg = <0 0x11002000 0 0x400>;
 393                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 394                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 395                          <&pericfg CLK_PERI_UART0_PD>;
 396                 clock-names = "baud", "bus";
 397                 status = "disabled";
 398         };
 399
 400         uart1: serial@11003000 {
 401                 compatible = "mediatek,mt7622-uart",
 402                              "mediatek,mt6577-uart";
 403                 reg = <0 0x11003000 0 0x400>;
 404                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 405                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 406                          <&pericfg CLK_PERI_UART1_PD>;
 407                 clock-names = "baud", "bus";
 408                 status = "disabled";
 409         };
 410
 411         uart2: serial@11004000 {
 412                 compatible = "mediatek,mt7622-uart",
 413                              "mediatek,mt6577-uart";
 414                 reg = <0 0x11004000 0 0x400>;
 415                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 416                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 417                          <&pericfg CLK_PERI_UART2_PD>;
 418                 clock-names = "baud", "bus";
 419                 status = "disabled";
 420         };
 421
 422         uart3: serial@11005000 {
 423                 compatible = "mediatek,mt7622-uart",
 424                              "mediatek,mt6577-uart";
 425                 reg = <0 0x11005000 0 0x400>;
 426                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 427                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 428                          <&pericfg CLK_PERI_UART3_PD>;
 429                 clock-names = "baud", "bus";
 430                 status = "disabled";
 431         };
 432
 433         pwm: pwm@11006000 {
 434                 compatible = "mediatek,mt7622-pwm";
 435                 reg = <0 0x11006000 0 0x1000>;
 436                 #pwm-cells = <2>;
 437                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 438                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 439                          <&pericfg CLK_PERI_PWM_PD>,
 440                          <&pericfg CLK_PERI_PWM1_PD>,
 441                          <&pericfg CLK_PERI_PWM2_PD>,
 442                          <&pericfg CLK_PERI_PWM3_PD>,
 443                          <&pericfg CLK_PERI_PWM4_PD>,
 444                          <&pericfg CLK_PERI_PWM5_PD>,
 445                          <&pericfg CLK_PERI_PWM6_PD>;
 446                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 447                               "pwm5", "pwm6";
 448                 status = "disabled";
 449         };
 450
 451         i2c0: i2c@11007000 {
 452                 compatible = "mediatek,mt7622-i2c";
 453                 reg = <0 0x11007000 0 0x90>,
 454                       <0 0x11000100 0 0x80>;
 455                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 456                 clock-div = <16>;
 457                 clocks = <&pericfg CLK_PERI_I2C0_PD>,
 458                          <&pericfg CLK_PERI_AP_DMA_PD>;
 459                 clock-names = "main", "dma";
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 status = "disabled";
 463         };
 464
 465         i2c1: i2c@11008000 {
 466                 compatible = "mediatek,mt7622-i2c";
 467                 reg = <0 0x11008000 0 0x90>,
 468                       <0 0x11000180 0 0x80>;
 469                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 470                 clock-div = <16>;
 471                 clocks = <&pericfg CLK_PERI_I2C1_PD>,
 472                          <&pericfg CLK_PERI_AP_DMA_PD>;
 473                 clock-names = "main", "dma";
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 status = "disabled";
 477         };
 478
 479         i2c2: i2c@11009000 {
 480                 compatible = "mediatek,mt7622-i2c";
 481                 reg = <0 0x11009000 0 0x90>,
 482                       <0 0x11000200 0 0x80>;
 483                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 484                 clock-div = <16>;
 485                 clocks = <&pericfg CLK_PERI_I2C2_PD>,
 486                          <&pericfg CLK_PERI_AP_DMA_PD>;
 487                 clock-names = "main", "dma";
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         spi0: spi@1100a000 {
 494                 compatible = "mediatek,mt7622-spi";
 495                 reg = <0 0x1100a000 0 0x100>;
 496                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 497                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 498                          <&topckgen CLK_TOP_SPI0_SEL>,
 499                          <&pericfg CLK_PERI_SPI0_PD>;
 500                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503                 status = "disabled";
 504         };
 505
 506         thermal: thermal@1100b000 {
 507                 #thermal-sensor-cells = <1>;
 508                 compatible = "mediatek,mt7622-thermal";
 509                 reg = <0 0x1100b000 0 0x1000>;
 510                 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
 511                 clocks = <&pericfg CLK_PERI_THERM_PD>,
 512                          <&pericfg CLK_PERI_AUXADC_PD>;
 513                 clock-names = "therm", "auxadc";
 514                 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
 515                 mediatek,auxadc = <&auxadc>;
 516                 mediatek,apmixedsys = <&apmixedsys>;
 517                 nvmem-cells = <&thermal_calibration>;
 518                 nvmem-cell-names = "calibration-data";
 519         };
 520
 521         btif: serial@1100c000 {
 522                 compatible = "mediatek,mt7622-btif",
 523                              "mediatek,mtk-btif";
 524                 reg = <0 0x1100c000 0 0x1000>;
 525                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
 526                 clocks = <&pericfg CLK_PERI_BTIF_PD>;
 527                 clock-names = "main";
 528                 reg-shift = <2>;
 529                 reg-io-width = <4>;
 530                 status = "disabled";
 531
 532                 bluetooth {
 533                         compatible = "mediatek,mt7622-bluetooth";
 534                         power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 535                         clocks = <&clk25m>;
 536                         clock-names = "ref";
 537                 };
 538         };
 539
 540         nandc: nfi@1100d000 {
 541                 compatible = "mediatek,mt7622-nfc";
 542                 reg = <0 0x1100D000 0 0x1000>;
 543                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 544                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 545                          <&pericfg CLK_PERI_SNFI_PD>;
 546                 clock-names = "nfi_clk", "pad_clk";
 547                 ecc-engine = <&bch>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         snfi: spi@1100d000 {
 554                 compatible = "mediatek,mt7622-snand";
 555                 reg = <0 0x1100d000 0 0x1000>;
 556                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 557                 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
 558                 clock-names = "nfi_clk", "pad_clk";
 559                 nand-ecc-engine = <&bch>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 status = "disabled";
 563         };
 564
 565         bch: ecc@1100e000 {
 566                 compatible = "mediatek,mt7622-ecc";
 567                 reg = <0 0x1100e000 0 0x1000>;
 568                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
 569                 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
 570                 clock-names = "nfiecc_clk";
 571                 status = "disabled";
 572         };
 573
 574         nor_flash: spi@11014000 {
 575                 compatible = "mediatek,mt7622-nor",
 576                              "mediatek,mt8173-nor";
 577                 reg = <0 0x11014000 0 0xe0>;
 578                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
 579                          <&topckgen CLK_TOP_FLASH_SEL>;
 580                 clock-names = "spi", "sf";
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         spi1: spi@11016000 {
 587                 compatible = "mediatek,mt7622-spi";
 588                 reg = <0 0x11016000 0 0x100>;
 589                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
 590                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 591                          <&topckgen CLK_TOP_SPI1_SEL>,
 592                          <&pericfg CLK_PERI_SPI1_PD>;
 593                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         uart4: serial@11019000 {
 600                 compatible = "mediatek,mt7622-uart",
 601                              "mediatek,mt6577-uart";
 602                 reg = <0 0x11019000 0 0x400>;
 603                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 604                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 605                          <&pericfg CLK_PERI_UART4_PD>;
 606                 clock-names = "baud", "bus";
 607                 status = "disabled";
 608         };
 609
 610         audsys: clock-controller@11220000 {
 611                 compatible = "mediatek,mt7622-audsys", "syscon";
 612                 reg = <0 0x11220000 0 0x2000>;
 613                 #clock-cells = <1>;
 614
 615                 afe: audio-controller {
 616                         compatible = "mediatek,mt7622-audio";
 617                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
 618                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 619                         interrupt-names = "afe", "asys";
 620
 621                         clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
 622                                  <&topckgen CLK_TOP_AUD1_SEL>,
 623                                  <&topckgen CLK_TOP_AUD2_SEL>,
 624                                  <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
 625                                  <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
 626                                  <&topckgen CLK_TOP_I2S0_MCK_SEL>,
 627                                  <&topckgen CLK_TOP_I2S1_MCK_SEL>,
 628                                  <&topckgen CLK_TOP_I2S2_MCK_SEL>,
 629                                  <&topckgen CLK_TOP_I2S3_MCK_SEL>,
 630                                  <&topckgen CLK_TOP_I2S0_MCK_DIV>,
 631                                  <&topckgen CLK_TOP_I2S1_MCK_DIV>,
 632                                  <&topckgen CLK_TOP_I2S2_MCK_DIV>,
 633                                  <&topckgen CLK_TOP_I2S3_MCK_DIV>,
 634                                  <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
 635                                  <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
 636                                  <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
 637                                  <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
 638                                  <&audsys CLK_AUDIO_I2SO1>,
 639                                  <&audsys CLK_AUDIO_I2SO2>,
 640                                  <&audsys CLK_AUDIO_I2SO3>,
 641                                  <&audsys CLK_AUDIO_I2SO4>,
 642                                  <&audsys CLK_AUDIO_I2SIN1>,
 643                                  <&audsys CLK_AUDIO_I2SIN2>,
 644                                  <&audsys CLK_AUDIO_I2SIN3>,
 645                                  <&audsys CLK_AUDIO_I2SIN4>,
 646                                  <&audsys CLK_AUDIO_ASRCO1>,
 647                                  <&audsys CLK_AUDIO_ASRCO2>,
 648                                  <&audsys CLK_AUDIO_ASRCO3>,
 649                                  <&audsys CLK_AUDIO_ASRCO4>,
 650                                  <&audsys CLK_AUDIO_AFE>,
 651                                  <&audsys CLK_AUDIO_AFE_CONN>,
 652                                  <&audsys CLK_AUDIO_A1SYS>,
 653                                  <&audsys CLK_AUDIO_A2SYS>;
 654
 655                         clock-names = "infra_sys_audio_clk",
 656                                       "top_audio_mux1_sel",
 657                                       "top_audio_mux2_sel",
 658                                       "top_audio_a1sys_hp",
 659                                       "top_audio_a2sys_hp",
 660                                       "i2s0_src_sel",
 661                                       "i2s1_src_sel",
 662                                       "i2s2_src_sel",
 663                                       "i2s3_src_sel",
 664                                       "i2s0_src_div",
 665                                       "i2s1_src_div",
 666                                       "i2s2_src_div",
 667                                       "i2s3_src_div",
 668                                       "i2s0_mclk_en",
 669                                       "i2s1_mclk_en",
 670                                       "i2s2_mclk_en",
 671                                       "i2s3_mclk_en",
 672                                       "i2so0_hop_ck",
 673                                       "i2so1_hop_ck",
 674                                       "i2so2_hop_ck",
 675                                       "i2so3_hop_ck",
 676                                       "i2si0_hop_ck",
 677                                       "i2si1_hop_ck",
 678                                       "i2si2_hop_ck",
 679                                       "i2si3_hop_ck",
 680                                       "asrc0_out_ck",
 681                                       "asrc1_out_ck",
 682                                       "asrc2_out_ck",
 683                                       "asrc3_out_ck",
 684                                       "audio_afe_pd",
 685                                       "audio_afe_conn_pd",
 686                                       "audio_a1sys_pd",
 687                                       "audio_a2sys_pd";
 688
 689                         assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 690                                           <&topckgen CLK_TOP_A2SYS_HP_SEL>,
 691                                           <&topckgen CLK_TOP_A1SYS_HP_DIV>,
 692                                           <&topckgen CLK_TOP_A2SYS_HP_DIV>;
 693                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
 694                                                  <&topckgen CLK_TOP_AUD2PLL>;
 695                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 696                 };
 697         };
 698
 699         mmc0: mmc@11230000 {
 700                 compatible = "mediatek,mt7622-mmc";
 701                 reg = <0 0x11230000 0 0x1000>;
 702                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 703                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 704                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 705                 clock-names = "source", "hclk";
 706                 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
 707                 reset-names = "hrst";
 708                 status = "disabled";
 709         };
 710
 711         mmc1: mmc@11240000 {
 712                 compatible = "mediatek,mt7622-mmc";
 713                 reg = <0 0x11240000 0 0x1000>;
 714                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 715                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 716                          <&topckgen CLK_TOP_AXI_SEL>;
 717                 clock-names = "source", "hclk";
 718                 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
 719                 reset-names = "hrst";
 720                 status = "disabled";
 721         };
 722
 723         wmac: wmac@18000000 {
 724                 compatible = "mediatek,mt7622-wmac";
 725                 reg = <0 0x18000000 0 0x100000>;
 726                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
 727
 728                 mediatek,infracfg = <&infracfg>;
 729                 status = "disabled";
 730
 731                 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 732         };
 733
 734         ssusbsys: clock-controller@1a000000 {
 735                 compatible = "mediatek,mt7622-ssusbsys";
 736                 reg = <0 0x1a000000 0 0x1000>;
 737                 #clock-cells = <1>;
 738                 #reset-cells = <1>;
 739         };
 740
 741         ssusb: usb@1a0c0000 {
 742                 compatible = "mediatek,mt7622-xhci",
 743                              "mediatek,mtk-xhci";
 744                 reg = <0 0x1a0c0000 0 0x01000>,
 745                       <0 0x1a0c4700 0 0x0100>;
 746                 reg-names = "mac", "ippc";
 747                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 748                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 749                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 750                          <&ssusbsys CLK_SSUSB_REF_EN>,
 751                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 752                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 753                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 754                 phys = <&u2port0 PHY_TYPE_USB2>,
 755                        <&u3port0 PHY_TYPE_USB3>,
 756                        <&u2port1 PHY_TYPE_USB2>;
 757
 758                 status = "disabled";
 759         };
 760
 761         u3phy: t-phy@1a0c4000 {
 762                 compatible = "mediatek,mt7622-tphy",
 763                              "mediatek,generic-tphy-v1";
 764                 reg = <0 0x1a0c4000 0 0x700>;
 765                 #address-cells = <2>;
 766                 #size-cells = <2>;
 767                 ranges;
 768                 status = "disabled";
 769
 770                 u2port0: usb-phy@1a0c4800 {
 771                         reg = <0 0x1a0c4800 0 0x0100>;
 772                         #phy-cells = <1>;
 773                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 774                         clock-names = "ref";
 775                 };
 776
 777                 u3port0: usb-phy@1a0c4900 {
 778                         reg = <0 0x1a0c4900 0 0x0700>;
 779                         #phy-cells = <1>;
 780                         clocks = <&clk25m>;
 781                         clock-names = "ref";
 782                 };
 783
 784                 u2port1: usb-phy@1a0c5000 {
 785                         reg = <0 0x1a0c5000 0 0x0100>;
 786                         #phy-cells = <1>;
 787                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 788                         clock-names = "ref";
 789                 };
 790         };
 791
 792         pciesys: clock-controller@1a100800 {
 793                 compatible = "mediatek,mt7622-pciesys";
 794                 reg = <0 0x1a100800 0 0x1000>;
 795                 #clock-cells = <1>;
 796                 #reset-cells = <1>;
 797         };
 798
 799         pciecfg: pciecfg@1a140000 {
 800                 compatible = "mediatek,generic-pciecfg", "syscon";
 801                 reg = <0 0x1a140000 0 0x1000>;
 802         };
 803
 804         pcie0: pcie@1a143000 {
 805                 compatible = "mediatek,mt7622-pcie";
 806                 device_type = "pci";
 807                 reg = <0 0x1a143000 0 0x1000>;
 808                 reg-names = "port0";
 809                 linux,pci-domain = <0>;
 810                 #address-cells = <3>;
 811                 #size-cells = <2>;
 812                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
 813                 interrupt-names = "pcie_irq";
 814                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 815                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 816                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 817                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 818                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 819                          <&pciesys CLK_PCIE_P0_PIPE_EN>;
 820                 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
 821                               "axi_ck0", "obff_ck0", "pipe_ck0";
 822
 823                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 824                 bus-range = <0x00 0xff>;
 825                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
 826                 status = "disabled";
 827
 828                 #interrupt-cells = <1>;
 829                 interrupt-map-mask = <0 0 0 7>;
 830                 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 831                                 <0 0 0 2 &pcie_intc0 1>,
 832                                 <0 0 0 3 &pcie_intc0 2>,
 833                                 <0 0 0 4 &pcie_intc0 3>;
 834                 pcie_intc0: interrupt-controller {
 835                         interrupt-controller;
 836                         #address-cells = <0>;
 837                         #interrupt-cells = <1>;
 838                 };
 839         };
 840
 841         pcie1: pcie@1a145000 {
 842                 compatible = "mediatek,mt7622-pcie";
 843                 device_type = "pci";
 844                 reg = <0 0x1a145000 0 0x1000>;
 845                 reg-names = "port1";
 846                 linux,pci-domain = <1>;
 847                 #address-cells = <3>;
 848                 #size-cells = <2>;
 849                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 850                 interrupt-names = "pcie_irq";
 851                 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
 852                          /* designer has connect RC1 with p0_ahb clock */
 853                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 854                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 855                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 856                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 857                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 858                 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
 859                               "axi_ck1", "obff_ck1", "pipe_ck1";
 860
 861                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 862                 bus-range = <0x00 0xff>;
 863                 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
 864                 status = "disabled";
 865
 866                 #interrupt-cells = <1>;
 867                 interrupt-map-mask = <0 0 0 7>;
 868                 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 869                                 <0 0 0 2 &pcie_intc1 1>,
 870                                 <0 0 0 3 &pcie_intc1 2>,
 871                                 <0 0 0 4 &pcie_intc1 3>;
 872                 pcie_intc1: interrupt-controller {
 873                         interrupt-controller;
 874                         #address-cells = <0>;
 875                         #interrupt-cells = <1>;
 876                 };
 877         };
 878
 879         sata: sata@1a200000 {
 880                 compatible = "mediatek,mt7622-ahci",
 881                              "mediatek,mtk-ahci";
 882                 reg = <0 0x1a200000 0 0x1100>;
 883                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 884                 interrupt-names = "hostc";
 885                 clocks = <&pciesys CLK_SATA_AHB_EN>,
 886                          <&pciesys CLK_SATA_AXI_EN>,
 887                          <&pciesys CLK_SATA_ASIC_EN>,
 888                          <&pciesys CLK_SATA_RBC_EN>,
 889                          <&pciesys CLK_SATA_PM_EN>;
 890                 clock-names = "ahb", "axi", "asic", "rbc", "pm";
 891                 phys = <&sata_port PHY_TYPE_SATA>;
 892                 phy-names = "sata-phy";
 893                 ports-implemented = <0x1>;
 894                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 895                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 896                          <&pciesys MT7622_SATA_PHY_SW_RST>,
 897                          <&pciesys MT7622_SATA_PHY_REG_RST>;
 898                 reset-names = "axi", "sw", "reg";
 899                 mediatek,phy-mode = <&pciesys>;
 900                 status = "disabled";
 901         };
 902
 903         sata_phy: t-phy@1a243000 {
 904                 compatible = "mediatek,mt7622-tphy",
 905                              "mediatek,generic-tphy-v1";
 906                 #address-cells = <2>;
 907                 #size-cells = <2>;
 908                 ranges;
 909                 status = "disabled";
 910
 911                 sata_port: sata-phy@1a243000 {
 912                         reg = <0 0x1a243000 0 0x0100>;
 913                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 914                         clock-names = "ref";
 915                         #phy-cells = <1>;
 916                 };
 917         };
 918
 919         hifsys: clock-controller@1af00000 {
 920                 compatible = "mediatek,mt7622-hifsys";
 921                 reg = <0 0x1af00000 0 0x70>;
 922                 #clock-cells = <1>;
 923         };
 924
 925         ethsys: clock-controller@1b000000 {
 926                 compatible = "mediatek,mt7622-ethsys",
 927                              "syscon";
 928                 reg = <0 0x1b000000 0 0x1000>;
 929                 #clock-cells = <1>;
 930                 #reset-cells = <1>;
 931         };
 932
 933         hsdma: dma-controller@1b007000 {
 934                 compatible = "mediatek,mt7622-hsdma";
 935                 reg = <0 0x1b007000 0 0x1000>;
 936                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
 937                 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
 938                 clock-names = "hsdma";
 939                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 940                 #dma-cells = <1>;
 941                 dma-requests = <3>;
 942         };
 943
 944         pcie_mirror: pcie-mirror@10000400 {
 945                 compatible = "mediatek,mt7622-pcie-mirror",
 946                              "syscon";
 947                 reg = <0 0x10000400 0 0x10>;
 948         };
 949
 950         wed0: wed@1020a000 {
 951                 compatible = "mediatek,mt7622-wed",
 952                              "syscon";
 953                 reg = <0 0x1020a000 0 0x1000>;
 954                 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
 955         };
 956
 957         wed1: wed@1020b000 {
 958                 compatible = "mediatek,mt7622-wed",
 959                              "syscon";
 960                 reg = <0 0x1020b000 0 0x1000>;
 961                 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
 962         };
 963
 964         eth: ethernet@1b100000 {
 965                 compatible = "mediatek,mt7622-eth";
 966                 reg = <0 0x1b100000 0 0x20000>;
 967                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 968                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 969                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 970                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 971                          <&ethsys CLK_ETH_ESW_EN>,
 972                          <&ethsys CLK_ETH_GP0_EN>,
 973                          <&ethsys CLK_ETH_GP1_EN>,
 974                          <&ethsys CLK_ETH_GP2_EN>,
 975                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 976                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 977                          <&sgmiisys CLK_SGMII_CDR_REF>,
 978                          <&sgmiisys CLK_SGMII_CDR_FB>,
 979                          <&topckgen CLK_TOP_SGMIIPLL>,
 980                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 981                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 982                               "sgmii_tx250m", "sgmii_rx250m",
 983                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 984                               "eth2pll";
 985                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 986                 mediatek,ethsys = <&ethsys>;
 987                 mediatek,sgmiisys = <&sgmiisys>;
 988                 cci-control-port = <&cci_control2>;
 989                 mediatek,wed = <&wed0>, <&wed1>;
 990                 mediatek,pcie-mirror = <&pcie_mirror>;
 991                 mediatek,hifsys = <&hifsys>;
 992                 dma-coherent;
 993                 #address-cells = <1>;
 994                 #size-cells = <0>;
 995                 status = "disabled";
 996         };
 997
 998         sgmiisys: sgmiisys@1b128000 {
 999                 compatible = "mediatek,mt7622-sgmiisys",
1000                              "syscon";
1001                 reg = <0 0x1b128000 0 0x3000>;
1002                 #clock-cells = <1>;
1003         };
1004 };