arch/arm64/boot/dts/mediatek/mt7622.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt7622-clk.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt7622-power.h>
  14 #include <dt-bindings/reset/mt7622-reset.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         compatible = "mediatek,mt7622";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpu_opp_table: opp-table {
  24                 compatible = "operating-points-v2";
  25                 opp-shared;
  26                 opp-300000000 {
  27                         opp-hz = /bits/ 64 <30000000>;
  28                         opp-microvolt = <950000>;
  29                 };
  30
  31                 opp-437500000 {
  32                         opp-hz = /bits/ 64 <437500000>;
  33                         opp-microvolt = <1000000>;
  34                 };
  35
  36                 opp-600000000 {
  37                         opp-hz = /bits/ 64 <600000000>;
  38                         opp-microvolt = <1050000>;
  39                 };
  40
  41                 opp-812500000 {
  42                         opp-hz = /bits/ 64 <812500000>;
  43                         opp-microvolt = <1100000>;
  44                 };
  45
  46                 opp-1025000000 {
  47                         opp-hz = /bits/ 64 <1025000000>;
  48                         opp-microvolt = <1150000>;
  49                 };
  50
  51                 opp-1137500000 {
  52                         opp-hz = /bits/ 64 <1137500000>;
  53                         opp-microvolt = <1200000>;
  54                 };
  55
  56                 opp-1262500000 {
  57                         opp-hz = /bits/ 64 <1262500000>;
  58                         opp-microvolt = <1250000>;
  59                 };
  60
  61                 opp-1350000000 {
  62                         opp-hz = /bits/ 64 <1350000000>;
  63                         opp-microvolt = <1310000>;
  64                 };
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x0 0x0>;
  75                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  76                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  77                         clock-names = "cpu", "intermediate";
  78                         operating-points-v2 = <&cpu_opp_table>;
  79                         #cooling-cells = <2>;
  80                         enable-method = "psci";
  81                         clock-frequency = <1300000000>;
  82                         cci-control-port = <&cci_control2>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53";
  88                         reg = <0x0 0x1>;
  89                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  90                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  91                         clock-names = "cpu", "intermediate";
  92                         operating-points-v2 = <&cpu_opp_table>;
  93                         #cooling-cells = <2>;
  94                         enable-method = "psci";
  95                         clock-frequency = <1300000000>;
  96                         cci-control-port = <&cci_control2>;
  97                 };
  98         };
  99
 100         pwrap_clk: dummy40m {
 101                 compatible = "fixed-clock";
 102                 clock-frequency = <40000000>;
 103                 #clock-cells = <0>;
 104         };
 105
 106         clk25m: oscillator {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <25000000>;
 110                 clock-output-names = "clkxtal";
 111         };
 112
 113         psci {
 114                 compatible  = "arm,psci-0.2";
 115                 method      = "smc";
 116         };
 117
 118         pmu {
 119                 compatible = "arm,cortex-a53-pmu";
 120                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 121                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 122                 interrupt-affinity = <&cpu0>, <&cpu1>;
 123         };
 124
 125         reserved-memory {
 126                 #address-cells = <2>;
 127                 #size-cells = <2>;
 128                 ranges;
 129
 130                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 131                 secmon_reserved: secmon@43000000 {
 132                         reg = <0 0x43000000 0 0x30000>;
 133                         no-map;
 134                 };
 135         };
 136
 137         thermal-zones {
 138                 cpu_thermal: cpu-thermal {
 139                         polling-delay-passive = <1000>;
 140                         polling-delay = <1000>;
 141
 142                         thermal-sensors = <&thermal 0>;
 143
 144                         trips {
 145                                 cpu_passive: cpu-passive {
 146                                         temperature = <47000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150
 151                                 cpu_active: cpu-active {
 152                                         temperature = <67000>;
 153                                         hysteresis = <2000>;
 154                                         type = "active";
 155                                 };
 156
 157                                 cpu_hot: cpu-hot {
 158                                         temperature = <87000>;
 159                                         hysteresis = <2000>;
 160                                         type = "hot";
 161                                 };
 162
 163                                 cpu-crit {
 164                                         temperature = <107000>;
 165                                         hysteresis = <2000>;
 166                                         type = "critical";
 167                                 };
 168                         };
 169
 170                         cooling-maps {
 171                                 map0 {
 172                                         trip = <&cpu_passive>;
 173                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 174                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 175                                 };
 176
 177                                 map1 {
 178                                         trip = <&cpu_active>;
 179                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 180                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 181                                 };
 182
 183                                 map2 {
 184                                         trip = <&cpu_hot>;
 185                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 186                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 187                                 };
 188                         };
 189                 };
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv8-timer";
 194                 interrupt-parent = <&gic>;
 195                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 196                               IRQ_TYPE_LEVEL_HIGH)>,
 197                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 198                               IRQ_TYPE_LEVEL_HIGH)>,
 199                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 200                               IRQ_TYPE_LEVEL_HIGH)>,
 201                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 202                               IRQ_TYPE_LEVEL_HIGH)>;
 203         };
 204
 205         infracfg: infracfg@10000000 {
 206                 compatible = "mediatek,mt7622-infracfg",
 207                              "syscon";
 208                 reg = <0 0x10000000 0 0x1000>;
 209                 #clock-cells = <1>;
 210                 #reset-cells = <1>;
 211         };
 212
 213         pwrap: pwrap@10001000 {
 214                 compatible = "mediatek,mt7622-pwrap";
 215                 reg = <0 0x10001000 0 0x250>;
 216                 reg-names = "pwrap";
 217                 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
 218                 clock-names = "spi", "wrap";
 219                 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
 220                 reset-names = "pwrap";
 221                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 222                 status = "disabled";
 223         };
 224
 225         pericfg: pericfg@10002000 {
 226                 compatible = "mediatek,mt7622-pericfg",
 227                              "syscon";
 228                 reg = <0 0x10002000 0 0x1000>;
 229                 #clock-cells = <1>;
 230                 #reset-cells = <1>;
 231         };
 232
 233         scpsys: scpsys@10006000 {
 234                 compatible = "mediatek,mt7622-scpsys",
 235                              "syscon";
 236                 #power-domain-cells = <1>;
 237                 reg = <0 0x10006000 0 0x1000>;
 238                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 239                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 240                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 241                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 242                 infracfg = <&infracfg>;
 243                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 244                 clock-names = "hif_sel";
 245         };
 246
 247         cir: cir@10009000 {
 248                 compatible = "mediatek,mt7622-cir";
 249                 reg = <0 0x10009000 0 0x1000>;
 250                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
 251                 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
 252                          <&topckgen CLK_TOP_AXI_SEL>;
 253                 clock-names = "clk", "bus";
 254                 status = "disabled";
 255         };
 256
 257         sysirq: interrupt-controller@10200620 {
 258                 compatible = "mediatek,mt7622-sysirq",
 259                              "mediatek,mt6577-sysirq";
 260                 interrupt-controller;
 261                 #interrupt-cells = <3>;
 262                 interrupt-parent = <&gic>;
 263                 reg = <0 0x10200620 0 0x20>;
 264         };
 265
 266         efuse: efuse@10206000 {
 267                 compatible = "mediatek,mt7622-efuse",
 268                              "mediatek,efuse";
 269                 reg = <0 0x10206000 0 0x1000>;
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272
 273                 thermal_calibration: calib@198 {
 274                         reg = <0x198 0xc>;
 275                 };
 276         };
 277
 278         apmixedsys: apmixedsys@10209000 {
 279                 compatible = "mediatek,mt7622-apmixedsys",
 280                              "syscon";
 281                 reg = <0 0x10209000 0 0x1000>;
 282                 #clock-cells = <1>;
 283         };
 284
 285         topckgen: topckgen@10210000 {
 286                 compatible = "mediatek,mt7622-topckgen",
 287                              "syscon";
 288                 reg = <0 0x10210000 0 0x1000>;
 289                 #clock-cells = <1>;
 290         };
 291
 292         rng: rng@1020f000 {
 293                 compatible = "mediatek,mt7622-rng",
 294                              "mediatek,mt7623-rng";
 295                 reg = <0 0x1020f000 0 0x1000>;
 296                 clocks = <&infracfg CLK_INFRA_TRNG>;
 297                 clock-names = "rng";
 298         };
 299
 300         pio: pinctrl@10211000 {
 301                 compatible = "mediatek,mt7622-pinctrl";
 302                 reg = <0 0x10211000 0 0x1000>,
 303                       <0 0x10005000 0 0x1000>;
 304                 reg-names = "base", "eint";
 305                 gpio-controller;
 306                 #gpio-cells = <2>;
 307                 gpio-ranges = <&pio 0 0 103>;
 308                 interrupt-controller;
 309                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 310                 interrupt-parent = <&gic>;
 311                 #interrupt-cells = <2>;
 312         };
 313
 314         watchdog: watchdog@10212000 {
 315                 compatible = "mediatek,mt7622-wdt",
 316                              "mediatek,mt6589-wdt";
 317                 reg = <0 0x10212000 0 0x800>;
 318         };
 319
 320         rtc: rtc@10212800 {
 321                 compatible = "mediatek,mt7622-rtc",
 322                              "mediatek,soc-rtc";
 323                 reg = <0 0x10212800 0 0x200>;
 324                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 325                 clocks = <&topckgen CLK_TOP_RTC>;
 326                 clock-names = "rtc";
 327         };
 328
 329         gic: interrupt-controller@10300000 {
 330                 compatible = "arm,gic-400";
 331                 interrupt-controller;
 332                 #interrupt-cells = <3>;
 333                 interrupt-parent = <&gic>;
 334                 reg = <0 0x10310000 0 0x1000>,
 335                       <0 0x10320000 0 0x1000>,
 336                       <0 0x10340000 0 0x2000>,
 337                       <0 0x10360000 0 0x2000>;
 338         };
 339
 340         cci: cci@10390000 {
 341                 compatible = "arm,cci-400";
 342                 #address-cells = <1>;
 343                 #size-cells = <1>;
 344                 reg = <0 0x10390000 0 0x1000>;
 345                 ranges = <0 0 0x10390000 0x10000>;
 346
 347                 cci_control0: slave-if@1000 {
 348                         compatible = "arm,cci-400-ctrl-if";
 349                         interface-type = "ace-lite";
 350                         reg = <0x1000 0x1000>;
 351                 };
 352
 353                 cci_control1: slave-if@4000 {
 354                         compatible = "arm,cci-400-ctrl-if";
 355                         interface-type = "ace";
 356                         reg = <0x4000 0x1000>;
 357                 };
 358
 359                 cci_control2: slave-if@5000 {
 360                         compatible = "arm,cci-400-ctrl-if";
 361                         interface-type = "ace";
 362                         reg = <0x5000 0x1000>;
 363                 };
 364
 365                 pmu@9000 {
 366                         compatible = "arm,cci-400-pmu,r1";
 367                         reg = <0x9000 0x5000>;
 368                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 369                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 370                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 372                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 373                 };
 374         };
 375
 376         auxadc: adc@11001000 {
 377                 compatible = "mediatek,mt7622-auxadc";
 378                 reg = <0 0x11001000 0 0x1000>;
 379                 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
 380                 clock-names = "main";
 381                 #io-channel-cells = <1>;
 382         };
 383
 384         uart0: serial@11002000 {
 385                 compatible = "mediatek,mt7622-uart",
 386                              "mediatek,mt6577-uart";
 387                 reg = <0 0x11002000 0 0x400>;
 388                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 389                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 390                          <&pericfg CLK_PERI_UART0_PD>;
 391                 clock-names = "baud", "bus";
 392                 status = "disabled";
 393         };
 394
 395         uart1: serial@11003000 {
 396                 compatible = "mediatek,mt7622-uart",
 397                              "mediatek,mt6577-uart";
 398                 reg = <0 0x11003000 0 0x400>;
 399                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 400                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 401                          <&pericfg CLK_PERI_UART1_PD>;
 402                 clock-names = "baud", "bus";
 403                 status = "disabled";
 404         };
 405
 406         uart2: serial@11004000 {
 407                 compatible = "mediatek,mt7622-uart",
 408                              "mediatek,mt6577-uart";
 409                 reg = <0 0x11004000 0 0x400>;
 410                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 411                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 412                          <&pericfg CLK_PERI_UART2_PD>;
 413                 clock-names = "baud", "bus";
 414                 status = "disabled";
 415         };
 416
 417         uart3: serial@11005000 {
 418                 compatible = "mediatek,mt7622-uart",
 419                              "mediatek,mt6577-uart";
 420                 reg = <0 0x11005000 0 0x400>;
 421                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 422                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 423                          <&pericfg CLK_PERI_UART3_PD>;
 424                 clock-names = "baud", "bus";
 425                 status = "disabled";
 426         };
 427
 428         pwm: pwm@11006000 {
 429                 compatible = "mediatek,mt7622-pwm";
 430                 reg = <0 0x11006000 0 0x1000>;
 431                 #pwm-cells = <2>;
 432                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 433                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 434                          <&pericfg CLK_PERI_PWM_PD>,
 435                          <&pericfg CLK_PERI_PWM1_PD>,
 436                          <&pericfg CLK_PERI_PWM2_PD>,
 437                          <&pericfg CLK_PERI_PWM3_PD>,
 438                          <&pericfg CLK_PERI_PWM4_PD>,
 439                          <&pericfg CLK_PERI_PWM5_PD>,
 440                          <&pericfg CLK_PERI_PWM6_PD>;
 441                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 442                               "pwm5", "pwm6";
 443                 status = "disabled";
 444         };
 445
 446         i2c0: i2c@11007000 {
 447                 compatible = "mediatek,mt7622-i2c";
 448                 reg = <0 0x11007000 0 0x90>,
 449                       <0 0x11000100 0 0x80>;
 450                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 451                 clock-div = <16>;
 452                 clocks = <&pericfg CLK_PERI_I2C0_PD>,
 453                          <&pericfg CLK_PERI_AP_DMA_PD>;
 454                 clock-names = "main", "dma";
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 status = "disabled";
 458         };
 459
 460         i2c1: i2c@11008000 {
 461                 compatible = "mediatek,mt7622-i2c";
 462                 reg = <0 0x11008000 0 0x90>,
 463                       <0 0x11000180 0 0x80>;
 464                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 465                 clock-div = <16>;
 466                 clocks = <&pericfg CLK_PERI_I2C1_PD>,
 467                          <&pericfg CLK_PERI_AP_DMA_PD>;
 468                 clock-names = "main", "dma";
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 status = "disabled";
 472         };
 473
 474         i2c2: i2c@11009000 {
 475                 compatible = "mediatek,mt7622-i2c";
 476                 reg = <0 0x11009000 0 0x90>,
 477                       <0 0x11000200 0 0x80>;
 478                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 479                 clock-div = <16>;
 480                 clocks = <&pericfg CLK_PERI_I2C2_PD>,
 481                          <&pericfg CLK_PERI_AP_DMA_PD>;
 482                 clock-names = "main", "dma";
 483                 #address-cells = <1>;
 484                 #size-cells = <0>;
 485                 status = "disabled";
 486         };
 487
 488         spi0: spi@1100a000 {
 489                 compatible = "mediatek,mt7622-spi";
 490                 reg = <0 0x1100a000 0 0x100>;
 491                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 492                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 493                          <&topckgen CLK_TOP_SPI0_SEL>,
 494                          <&pericfg CLK_PERI_SPI0_PD>;
 495                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 496                 #address-cells = <1>;
 497                 #size-cells = <0>;
 498                 status = "disabled";
 499         };
 500
 501         thermal: thermal@1100b000 {
 502                 #thermal-sensor-cells = <1>;
 503                 compatible = "mediatek,mt7622-thermal";
 504                 reg = <0 0x1100b000 0 0x1000>;
 505                 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
 506                 clocks = <&pericfg CLK_PERI_THERM_PD>,
 507                          <&pericfg CLK_PERI_AUXADC_PD>;
 508                 clock-names = "therm", "auxadc";
 509                 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
 510                 reset-names = "therm";
 511                 mediatek,auxadc = <&auxadc>;
 512                 mediatek,apmixedsys = <&apmixedsys>;
 513                 nvmem-cells = <&thermal_calibration>;
 514                 nvmem-cell-names = "calibration-data";
 515         };
 516
 517         btif: serial@1100c000 {
 518                 compatible = "mediatek,mt7622-btif",
 519                              "mediatek,mtk-btif";
 520                 reg = <0 0x1100c000 0 0x1000>;
 521                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
 522                 clocks = <&pericfg CLK_PERI_BTIF_PD>;
 523                 clock-names = "main";
 524                 reg-shift = <2>;
 525                 reg-io-width = <4>;
 526                 status = "disabled";
 527
 528                 bluetooth {
 529                         compatible = "mediatek,mt7622-bluetooth";
 530                         power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 531                         clocks = <&clk25m>;
 532                         clock-names = "ref";
 533                 };
 534         };
 535
 536         nandc: nfi@1100d000 {
 537                 compatible = "mediatek,mt7622-nfc";
 538                 reg = <0 0x1100D000 0 0x1000>;
 539                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 540                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 541                          <&pericfg CLK_PERI_SNFI_PD>;
 542                 clock-names = "nfi_clk", "pad_clk";
 543                 ecc-engine = <&bch>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 status = "disabled";
 547         };
 548
 549         bch: ecc@1100e000 {
 550                 compatible = "mediatek,mt7622-ecc";
 551                 reg = <0 0x1100e000 0 0x1000>;
 552                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
 553                 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
 554                 clock-names = "nfiecc_clk";
 555                 status = "disabled";
 556         };
 557
 558         nor_flash: spi@11014000 {
 559                 compatible = "mediatek,mt7622-nor",
 560                              "mediatek,mt8173-nor";
 561                 reg = <0 0x11014000 0 0xe0>;
 562                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
 563                          <&topckgen CLK_TOP_FLASH_SEL>;
 564                 clock-names = "spi", "sf";
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         spi1: spi@11016000 {
 571                 compatible = "mediatek,mt7622-spi";
 572                 reg = <0 0x11016000 0 0x100>;
 573                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
 574                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 575                          <&topckgen CLK_TOP_SPI1_SEL>,
 576                          <&pericfg CLK_PERI_SPI1_PD>;
 577                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         uart4: serial@11019000 {
 584                 compatible = "mediatek,mt7622-uart",
 585                              "mediatek,mt6577-uart";
 586                 reg = <0 0x11019000 0 0x400>;
 587                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 588                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 589                          <&pericfg CLK_PERI_UART4_PD>;
 590                 clock-names = "baud", "bus";
 591                 status = "disabled";
 592         };
 593
 594         audsys: clock-controller@11220000 {
 595                 compatible = "mediatek,mt7622-audsys", "syscon";
 596                 reg = <0 0x11220000 0 0x2000>;
 597                 #clock-cells = <1>;
 598
 599                 afe: audio-controller {
 600                         compatible = "mediatek,mt7622-audio";
 601                         interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
 602                                       <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 603                         interrupt-names = "afe", "asys";
 604
 605                         clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
 606                                  <&topckgen CLK_TOP_AUD1_SEL>,
 607                                  <&topckgen CLK_TOP_AUD2_SEL>,
 608                                  <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
 609                                  <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
 610                                  <&topckgen CLK_TOP_I2S0_MCK_SEL>,
 611                                  <&topckgen CLK_TOP_I2S1_MCK_SEL>,
 612                                  <&topckgen CLK_TOP_I2S2_MCK_SEL>,
 613                                  <&topckgen CLK_TOP_I2S3_MCK_SEL>,
 614                                  <&topckgen CLK_TOP_I2S0_MCK_DIV>,
 615                                  <&topckgen CLK_TOP_I2S1_MCK_DIV>,
 616                                  <&topckgen CLK_TOP_I2S2_MCK_DIV>,
 617                                  <&topckgen CLK_TOP_I2S3_MCK_DIV>,
 618                                  <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
 619                                  <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
 620                                  <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
 621                                  <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
 622                                  <&audsys CLK_AUDIO_I2SO1>,
 623                                  <&audsys CLK_AUDIO_I2SO2>,
 624                                  <&audsys CLK_AUDIO_I2SO3>,
 625                                  <&audsys CLK_AUDIO_I2SO4>,
 626                                  <&audsys CLK_AUDIO_I2SIN1>,
 627                                  <&audsys CLK_AUDIO_I2SIN2>,
 628                                  <&audsys CLK_AUDIO_I2SIN3>,
 629                                  <&audsys CLK_AUDIO_I2SIN4>,
 630                                  <&audsys CLK_AUDIO_ASRCO1>,
 631                                  <&audsys CLK_AUDIO_ASRCO2>,
 632                                  <&audsys CLK_AUDIO_ASRCO3>,
 633                                  <&audsys CLK_AUDIO_ASRCO4>,
 634                                  <&audsys CLK_AUDIO_AFE>,
 635                                  <&audsys CLK_AUDIO_AFE_CONN>,
 636                                  <&audsys CLK_AUDIO_A1SYS>,
 637                                  <&audsys CLK_AUDIO_A2SYS>;
 638
 639                         clock-names = "infra_sys_audio_clk",
 640                                       "top_audio_mux1_sel",
 641                                       "top_audio_mux2_sel",
 642                                       "top_audio_a1sys_hp",
 643                                       "top_audio_a2sys_hp",
 644                                       "i2s0_src_sel",
 645                                       "i2s1_src_sel",
 646                                       "i2s2_src_sel",
 647                                       "i2s3_src_sel",
 648                                       "i2s0_src_div",
 649                                       "i2s1_src_div",
 650                                       "i2s2_src_div",
 651                                       "i2s3_src_div",
 652                                       "i2s0_mclk_en",
 653                                       "i2s1_mclk_en",
 654                                       "i2s2_mclk_en",
 655                                       "i2s3_mclk_en",
 656                                       "i2so0_hop_ck",
 657                                       "i2so1_hop_ck",
 658                                       "i2so2_hop_ck",
 659                                       "i2so3_hop_ck",
 660                                       "i2si0_hop_ck",
 661                                       "i2si1_hop_ck",
 662                                       "i2si2_hop_ck",
 663                                       "i2si3_hop_ck",
 664                                       "asrc0_out_ck",
 665                                       "asrc1_out_ck",
 666                                       "asrc2_out_ck",
 667                                       "asrc3_out_ck",
 668                                       "audio_afe_pd",
 669                                       "audio_afe_conn_pd",
 670                                       "audio_a1sys_pd",
 671                                       "audio_a2sys_pd";
 672
 673                         assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 674                                           <&topckgen CLK_TOP_A2SYS_HP_SEL>,
 675                                           <&topckgen CLK_TOP_A1SYS_HP_DIV>,
 676                                           <&topckgen CLK_TOP_A2SYS_HP_DIV>;
 677                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
 678                                                  <&topckgen CLK_TOP_AUD2PLL>;
 679                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 680                 };
 681         };
 682
 683         mmc0: mmc@11230000 {
 684                 compatible = "mediatek,mt7622-mmc";
 685                 reg = <0 0x11230000 0 0x1000>;
 686                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 687                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 688                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 689                 clock-names = "source", "hclk";
 690                 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
 691                 reset-names = "hrst";
 692                 status = "disabled";
 693         };
 694
 695         mmc1: mmc@11240000 {
 696                 compatible = "mediatek,mt7622-mmc";
 697                 reg = <0 0x11240000 0 0x1000>;
 698                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 699                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 700                          <&topckgen CLK_TOP_AXI_SEL>;
 701                 clock-names = "source", "hclk";
 702                 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
 703                 reset-names = "hrst";
 704                 status = "disabled";
 705         };
 706
 707         ssusbsys: ssusbsys@1a000000 {
 708                 compatible = "mediatek,mt7622-ssusbsys",
 709                              "syscon";
 710                 reg = <0 0x1a000000 0 0x1000>;
 711                 #clock-cells = <1>;
 712                 #reset-cells = <1>;
 713         };
 714
 715         ssusb: usb@1a0c0000 {
 716                 compatible = "mediatek,mt7622-xhci",
 717                              "mediatek,mtk-xhci";
 718                 reg = <0 0x1a0c0000 0 0x01000>,
 719                       <0 0x1a0c4700 0 0x0100>;
 720                 reg-names = "mac", "ippc";
 721                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 722                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 723                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 724                          <&ssusbsys CLK_SSUSB_REF_EN>,
 725                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 726                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 727                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 728                 phys = <&u2port0 PHY_TYPE_USB2>,
 729                        <&u3port0 PHY_TYPE_USB3>,
 730                        <&u2port1 PHY_TYPE_USB2>;
 731
 732                 status = "disabled";
 733         };
 734
 735         u3phy: usb-phy@1a0c4000 {
 736                 compatible = "mediatek,mt7622-u3phy",
 737                              "mediatek,generic-tphy-v1";
 738                 reg = <0 0x1a0c4000 0 0x700>;
 739                 #address-cells = <2>;
 740                 #size-cells = <2>;
 741                 ranges;
 742                 status = "disabled";
 743
 744                 u2port0: usb-phy@1a0c4800 {
 745                         reg = <0 0x1a0c4800 0 0x0100>;
 746                         #phy-cells = <1>;
 747                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 748                         clock-names = "ref";
 749                 };
 750
 751                 u3port0: usb-phy@1a0c4900 {
 752                         reg = <0 0x1a0c4900 0 0x0700>;
 753                         #phy-cells = <1>;
 754                         clocks = <&clk25m>;
 755                         clock-names = "ref";
 756                 };
 757
 758                 u2port1: usb-phy@1a0c5000 {
 759                         reg = <0 0x1a0c5000 0 0x0100>;
 760                         #phy-cells = <1>;
 761                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 762                         clock-names = "ref";
 763                 };
 764         };
 765
 766         pciesys: pciesys@1a100800 {
 767                 compatible = "mediatek,mt7622-pciesys",
 768                              "syscon";
 769                 reg = <0 0x1a100800 0 0x1000>;
 770                 #clock-cells = <1>;
 771                 #reset-cells = <1>;
 772         };
 773
 774         pcie: pcie@1a140000 {
 775                 compatible = "mediatek,mt7622-pcie";
 776                 device_type = "pci";
 777                 reg = <0 0x1a140000 0 0x1000>,
 778                       <0 0x1a143000 0 0x1000>,
 779                       <0 0x1a145000 0 0x1000>;
 780                 reg-names = "subsys", "port0", "port1";
 781                 #address-cells = <3>;
 782                 #size-cells = <2>;
 783                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 784                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 785                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 786                          <&pciesys CLK_PCIE_P1_MAC_EN>,
 787                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 788                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 789                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 790                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 791                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 792                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 793                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 794                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 795                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
 796                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 797                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 798                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 799                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 800                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 801                 bus-range = <0x00 0xff>;
 802                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 803                 status = "disabled";
 804
 805                 pcie0: pcie@0,0 {
 806                         reg = <0x0000 0 0 0 0>;
 807                         #address-cells = <3>;
 808                         #size-cells = <2>;
 809                         #interrupt-cells = <1>;
 810                         ranges;
 811                         status = "disabled";
 812
 813                         interrupt-map-mask = <0 0 0 7>;
 814                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 815                                         <0 0 0 2 &pcie_intc0 1>,
 816                                         <0 0 0 3 &pcie_intc0 2>,
 817                                         <0 0 0 4 &pcie_intc0 3>;
 818                         pcie_intc0: interrupt-controller {
 819                                 interrupt-controller;
 820                                 #address-cells = <0>;
 821                                 #interrupt-cells = <1>;
 822                         };
 823                 };
 824
 825                 pcie1: pcie@1,0 {
 826                         reg = <0x0800 0 0 0 0>;
 827                         #address-cells = <3>;
 828                         #size-cells = <2>;
 829                         #interrupt-cells = <1>;
 830                         ranges;
 831                         status = "disabled";
 832
 833                         interrupt-map-mask = <0 0 0 7>;
 834                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 835                                         <0 0 0 2 &pcie_intc1 1>,
 836                                         <0 0 0 3 &pcie_intc1 2>,
 837                                         <0 0 0 4 &pcie_intc1 3>;
 838                         pcie_intc1: interrupt-controller {
 839                                 interrupt-controller;
 840                                 #address-cells = <0>;
 841                                 #interrupt-cells = <1>;
 842                         };
 843                 };
 844         };
 845
 846         sata: sata@1a200000 {
 847                 compatible = "mediatek,mt7622-ahci",
 848                              "mediatek,mtk-ahci";
 849                 reg = <0 0x1a200000 0 0x1100>;
 850                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 851                 interrupt-names = "hostc";
 852                 clocks = <&pciesys CLK_SATA_AHB_EN>,
 853                          <&pciesys CLK_SATA_AXI_EN>,
 854                          <&pciesys CLK_SATA_ASIC_EN>,
 855                          <&pciesys CLK_SATA_RBC_EN>,
 856                          <&pciesys CLK_SATA_PM_EN>;
 857                 clock-names = "ahb", "axi", "asic", "rbc", "pm";
 858                 phys = <&sata_port PHY_TYPE_SATA>;
 859                 phy-names = "sata-phy";
 860                 ports-implemented = <0x1>;
 861                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 862                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 863                          <&pciesys MT7622_SATA_PHY_SW_RST>,
 864                          <&pciesys MT7622_SATA_PHY_REG_RST>;
 865                 reset-names = "axi", "sw", "reg";
 866                 mediatek,phy-mode = <&pciesys>;
 867                 status = "disabled";
 868         };
 869
 870         sata_phy: sata-phy@1a243000 {
 871                 compatible = "mediatek,generic-tphy-v1";
 872                 #address-cells = <2>;
 873                 #size-cells = <2>;
 874                 ranges;
 875                 status = "disabled";
 876
 877                 sata_port: sata-phy@1a243000 {
 878                         reg = <0 0x1a243000 0 0x0100>;
 879                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 880                         clock-names = "ref";
 881                         #phy-cells = <1>;
 882                 };
 883         };
 884
 885         ethsys: syscon@1b000000 {
 886                 compatible = "mediatek,mt7622-ethsys",
 887                              "syscon";
 888                 reg = <0 0x1b000000 0 0x1000>;
 889                 #clock-cells = <1>;
 890                 #reset-cells = <1>;
 891         };
 892
 893         hsdma: dma-controller@1b007000 {
 894                 compatible = "mediatek,mt7622-hsdma";
 895                 reg = <0 0x1b007000 0 0x1000>;
 896                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
 897                 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
 898                 clock-names = "hsdma";
 899                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 900                 #dma-cells = <1>;
 901         };
 902
 903         eth: ethernet@1b100000 {
 904                 compatible = "mediatek,mt7622-eth",
 905                              "mediatek,mt2701-eth",
 906                              "syscon";
 907                 reg = <0 0x1b100000 0 0x20000>;
 908                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 909                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 910                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 911                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 912                          <&ethsys CLK_ETH_ESW_EN>,
 913                          <&ethsys CLK_ETH_GP0_EN>,
 914                          <&ethsys CLK_ETH_GP1_EN>,
 915                          <&ethsys CLK_ETH_GP2_EN>,
 916                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 917                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 918                          <&sgmiisys CLK_SGMII_CDR_REF>,
 919                          <&sgmiisys CLK_SGMII_CDR_FB>,
 920                          <&topckgen CLK_TOP_SGMIIPLL>,
 921                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 922                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 923                               "sgmii_tx250m", "sgmii_rx250m",
 924                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 925                               "eth2pll";
 926                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 927                 mediatek,ethsys = <&ethsys>;
 928                 mediatek,sgmiisys = <&sgmiisys>;
 929                 #address-cells = <1>;
 930                 #size-cells = <0>;
 931                 status = "disabled";
 932         };
 933
 934         sgmiisys: sgmiisys@1b128000 {
 935                 compatible = "mediatek,mt7622-sgmiisys",
 936                              "syscon";
 937                 reg = <0 0x1b128000 0 0x3000>;
 938                 #clock-cells = <1>;
 939         };
 940 };