arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43
  44                 key-factory {
  45                         label = "factory";
  46                         linux,code = <BTN_0>;
  47                         gpios = <&pio 0 0>;
  48                 };
  49
  50                 key-wps {
  51                         label = "wps";
  52                         linux,code = <KEY_WPS_BUTTON>;
  53                         gpios = <&pio 102 0>;
  54                 };
  55         };
  56
  57         memory@40000000 {
  58                 reg = <0 0x40000000 0 0x20000000>;
  59                 device_type = "memory";
  60         };
  61
  62         reg_1p8v: regulator-1p8v {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "fixed-1.8V";
  65                 regulator-min-microvolt = <1800000>;
  66                 regulator-max-microvolt = <1800000>;
  67                 regulator-always-on;
  68         };
  69
  70         reg_3p3v: regulator-3p3v {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "fixed-3.3V";
  73                 regulator-min-microvolt = <3300000>;
  74                 regulator-max-microvolt = <3300000>;
  75                 regulator-boot-on;
  76                 regulator-always-on;
  77         };
  78
  79         reg_5v: regulator-5v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "fixed-5V";
  82                 regulator-min-microvolt = <5000000>;
  83                 regulator-max-microvolt = <5000000>;
  84                 regulator-boot-on;
  85                 regulator-always-on;
  86         };
  87 };
  88
  89 &bch {
  90         status = "disabled";
  91 };
  92
  93 &btif {
  94         status = "okay";
  95 };
  96
  97 &cir {
  98         pinctrl-names = "default";
  99         pinctrl-0 = <&irrx_pins>;
 100         status = "okay";
 101 };
 102
 103 &eth {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&eth_pins>;
 106         status = "okay";
 107
 108         gmac0: mac@0 {
 109                 compatible = "mediatek,eth-mac";
 110                 reg = <0>;
 111                 phy-mode = "2500base-x";
 112
 113                 fixed-link {
 114                         speed = <2500>;
 115                         full-duplex;
 116                         pause;
 117                 };
 118         };
 119
 120         mdio-bus {
 121                 #address-cells = <1>;
 122                 #size-cells = <0>;
 123
 124                 switch@0 {
 125                         compatible = "mediatek,mt7531";
 126                         reg = <0>;
 127                         reset-gpios = <&pio 54 0>;
 128
 129                         ports {
 130                                 #address-cells = <1>;
 131                                 #size-cells = <0>;
 132
 133                                 port@0 {
 134                                         reg = <0>;
 135                                         label = "lan0";
 136                                 };
 137
 138                                 port@1 {
 139                                         reg = <1>;
 140                                         label = "lan1";
 141                                 };
 142
 143                                 port@2 {
 144                                         reg = <2>;
 145                                         label = "lan2";
 146                                 };
 147
 148                                 port@3 {
 149                                         reg = <3>;
 150                                         label = "lan3";
 151                                 };
 152
 153                                 port@4 {
 154                                         reg = <4>;
 155                                         label = "wan";
 156                                 };
 157
 158                                 port@6 {
 159                                         reg = <6>;
 160                                         label = "cpu";
 161                                         ethernet = <&gmac0>;
 162                                         phy-mode = "2500base-x";
 163
 164                                         fixed-link {
 165                                                 speed = <2500>;
 166                                                 full-duplex;
 167                                                 pause;
 168                                         };
 169                                 };
 170                         };
 171                 };
 172
 173         };
 174 };
 175
 176 &i2c1 {
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&i2c1_pins>;
 179         status = "okay";
 180 };
 181
 182 &i2c2 {
 183         pinctrl-names = "default";
 184         pinctrl-0 = <&i2c2_pins>;
 185         status = "okay";
 186 };
 187
 188 &mmc0 {
 189         pinctrl-names = "default", "state_uhs";
 190         pinctrl-0 = <&emmc_pins_default>;
 191         pinctrl-1 = <&emmc_pins_uhs>;
 192         status = "okay";
 193         bus-width = <8>;
 194         max-frequency = <50000000>;
 195         cap-mmc-highspeed;
 196         mmc-hs200-1_8v;
 197         vmmc-supply = <&reg_3p3v>;
 198         vqmmc-supply = <&reg_1p8v>;
 199         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 200         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 201         non-removable;
 202 };
 203
 204 &mmc1 {
 205         pinctrl-names = "default", "state_uhs";
 206         pinctrl-0 = <&sd0_pins_default>;
 207         pinctrl-1 = <&sd0_pins_uhs>;
 208         status = "okay";
 209         bus-width = <4>;
 210         max-frequency = <50000000>;
 211         cap-sd-highspeed;
 212         r_smpl = <1>;
 213         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 214         vmmc-supply = <&reg_3p3v>;
 215         vqmmc-supply = <&reg_3p3v>;
 216         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 217         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 218 };
 219
 220 &nandc {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&parallel_nand_pins>;
 223         status = "disabled";
 224 };
 225
 226 &nor_flash {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&spi_nor_pins>;
 229         status = "disabled";
 230
 231         flash@0 {
 232                 compatible = "jedec,spi-nor";
 233                 reg = <0>;
 234         };
 235 };
 236
 237 &pcie0 {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pcie0_pins>;
 240         status = "okay";
 241 };
 242
 243 &pio {
 244         /* eMMC is shared pin with parallel NAND */
 245         emmc_pins_default: emmc-pins-default {
 246                 mux {
 247                         function = "emmc", "emmc_rst";
 248                         groups = "emmc";
 249                 };
 250
 251                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 252                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 253                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 254                  */
 255                 conf-cmd-dat {
 256                         pins = "NDL0", "NDL1", "NDL2",
 257                                "NDL3", "NDL4", "NDL5",
 258                                "NDL6", "NDL7", "NRB";
 259                         input-enable;
 260                         bias-pull-up;
 261                 };
 262
 263                 conf-clk {
 264                         pins = "NCLE";
 265                         bias-pull-down;
 266                 };
 267         };
 268
 269         emmc_pins_uhs: emmc-pins-uhs {
 270                 mux {
 271                         function = "emmc";
 272                         groups = "emmc";
 273                 };
 274
 275                 conf-cmd-dat {
 276                         pins = "NDL0", "NDL1", "NDL2",
 277                                "NDL3", "NDL4", "NDL5",
 278                                "NDL6", "NDL7", "NRB";
 279                         input-enable;
 280                         drive-strength = <4>;
 281                         bias-pull-up;
 282                 };
 283
 284                 conf-clk {
 285                         pins = "NCLE";
 286                         drive-strength = <4>;
 287                         bias-pull-down;
 288                 };
 289         };
 290
 291         eth_pins: eth-pins {
 292                 mux {
 293                         function = "eth";
 294                         groups = "mdc_mdio", "rgmii_via_gmac2";
 295                 };
 296         };
 297
 298         i2c1_pins: i2c1-pins {
 299                 mux {
 300                         function = "i2c";
 301                         groups = "i2c1_0";
 302                 };
 303         };
 304
 305         i2c2_pins: i2c2-pins {
 306                 mux {
 307                         function = "i2c";
 308                         groups = "i2c2_0";
 309                 };
 310         };
 311
 312         i2s1_pins: i2s1-pins {
 313                 mux {
 314                         function = "i2s";
 315                         groups =  "i2s_out_mclk_bclk_ws",
 316                                   "i2s1_in_data",
 317                                   "i2s1_out_data";
 318                 };
 319
 320                 conf {
 321                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 322                                "I2S_WS", "I2S_MCLK";
 323                         drive-strength = <12>;
 324                         bias-pull-down;
 325                 };
 326         };
 327
 328         irrx_pins: irrx-pins {
 329                 mux {
 330                         function = "ir";
 331                         groups = "ir_1_rx";
 332                 };
 333         };
 334
 335         irtx_pins: irtx-pins {
 336                 mux {
 337                         function = "ir";
 338                         groups = "ir_1_tx";
 339                 };
 340         };
 341
 342         /* Parallel nand is shared pin with eMMC */
 343         parallel_nand_pins: parallel-nand-pins {
 344                 mux {
 345                         function = "flash";
 346                         groups = "par_nand";
 347                 };
 348         };
 349
 350         pcie0_pins: pcie0-pins {
 351                 mux {
 352                         function = "pcie";
 353                         groups = "pcie0_pad_perst",
 354                                  "pcie0_1_waken",
 355                                  "pcie0_1_clkreq";
 356                 };
 357         };
 358
 359         pcie1_pins: pcie1-pins {
 360                 mux {
 361                         function = "pcie";
 362                         groups = "pcie1_pad_perst",
 363                                  "pcie1_0_waken",
 364                                  "pcie1_0_clkreq";
 365                 };
 366         };
 367
 368         pmic_bus_pins: pmic-bus-pins {
 369                 mux {
 370                         function = "pmic";
 371                         groups = "pmic_bus";
 372                 };
 373         };
 374
 375         pwm7_pins: pwm1-2-pins {
 376                 mux {
 377                         function = "pwm";
 378                         groups = "pwm_ch7_2";
 379                 };
 380         };
 381
 382         wled_pins: wled-pins {
 383                 mux {
 384                         function = "led";
 385                         groups = "wled";
 386                 };
 387         };
 388
 389         sd0_pins_default: sd0-pins-default {
 390                 mux {
 391                         function = "sd";
 392                         groups = "sd_0";
 393                 };
 394
 395                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 396                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 397                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 398                  */
 399                 conf-cmd-data {
 400                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 401                                "I2S2_IN","I2S4_OUT";
 402                         input-enable;
 403                         drive-strength = <8>;
 404                         bias-pull-up;
 405                 };
 406                 conf-clk {
 407                         pins = "I2S3_OUT";
 408                         drive-strength = <12>;
 409                         bias-pull-down;
 410                 };
 411                 conf-cd {
 412                         pins = "TXD3";
 413                         bias-pull-up;
 414                 };
 415         };
 416
 417         sd0_pins_uhs: sd0-pins-uhs {
 418                 mux {
 419                         function = "sd";
 420                         groups = "sd_0";
 421                 };
 422
 423                 conf-cmd-data {
 424                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 425                                "I2S2_IN","I2S4_OUT";
 426                         input-enable;
 427                         bias-pull-up;
 428                 };
 429
 430                 conf-clk {
 431                         pins = "I2S3_OUT";
 432                         bias-pull-down;
 433                 };
 434         };
 435
 436         /* Serial NAND is shared pin with SPI-NOR */
 437         serial_nand_pins: serial-nand-pins {
 438                 mux {
 439                         function = "flash";
 440                         groups = "snfi";
 441                 };
 442         };
 443
 444         spic0_pins: spic0-pins {
 445                 mux {
 446                         function = "spi";
 447                         groups = "spic0_0";
 448                 };
 449         };
 450
 451         spic1_pins: spic1-pins {
 452                 mux {
 453                         function = "spi";
 454                         groups = "spic1_0";
 455                 };
 456         };
 457
 458         /* SPI-NOR is shared pin with serial NAND */
 459         spi_nor_pins: spi-nor-pins {
 460                 mux {
 461                         function = "flash";
 462                         groups = "spi_nor";
 463                 };
 464         };
 465
 466         /* serial NAND is shared pin with SPI-NOR */
 467         serial_nand_pins: serial-nand-pins {
 468                 mux {
 469                         function = "flash";
 470                         groups = "snfi";
 471                 };
 472         };
 473
 474         uart0_pins: uart0-pins {
 475                 mux {
 476                         function = "uart";
 477                         groups = "uart0_0_tx_rx" ;
 478                 };
 479         };
 480
 481         uart2_pins: uart2-pins {
 482                 mux {
 483                         function = "uart";
 484                         groups = "uart2_1_tx_rx" ;
 485                 };
 486         };
 487
 488         watchdog_pins: watchdog-pins {
 489                 mux {
 490                         function = "watchdog";
 491                         groups = "watchdog";
 492                 };
 493         };
 494
 495         wmac_pins: wmac-pins {
 496                 mux {
 497                         function = "antsel";
 498                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
 499                                  "antsel4", "antsel5", "antsel6", "antsel7",
 500                                  "antsel8", "antsel9", "antsel12", "antsel13",
 501                                  "antsel14", "antsel15", "antsel16", "antsel17";
 502                 };
 503         };
 504 };
 505
 506 &pwm {
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&pwm7_pins>;
 509         status = "okay";
 510 };
 511
 512 &pwrap {
 513         pinctrl-names = "default";
 514         pinctrl-0 = <&pmic_bus_pins>;
 515
 516         status = "okay";
 517 };
 518
 519 &sata {
 520         status = "okay";
 521 };
 522
 523 &sata_phy {
 524         status = "okay";
 525 };
 526
 527 &spi0 {
 528         pinctrl-names = "default";
 529         pinctrl-0 = <&spic0_pins>;
 530         status = "okay";
 531 };
 532
 533 &spi1 {
 534         pinctrl-names = "default";
 535         pinctrl-0 = <&spic1_pins>;
 536         status = "okay";
 537 };
 538
 539 &ssusb {
 540         vusb33-supply = <&reg_3p3v>;
 541         vbus-supply = <&reg_5v>;
 542         status = "okay";
 543 };
 544
 545 &u3phy {
 546         status = "okay";
 547 };
 548
 549 &uart0 {
 550         pinctrl-names = "default";
 551         pinctrl-0 = <&uart0_pins>;
 552         status = "okay";
 553 };
 554
 555 &uart2 {
 556         pinctrl-names = "default";
 557         pinctrl-0 = <&uart2_pins>;
 558         status = "okay";
 559 };
 560
 561 &watchdog {
 562         pinctrl-names = "default";
 563         pinctrl-0 = <&watchdog_pins>;
 564         status = "okay";
 565 };
 566
 567 &wmac {
 568         pinctrl-names = "default";
 569         pinctrl-0 = <&wmac_pins>;
 570         status = "okay";
 571 };