2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "MediaTek MT7622 RFB1 board";
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
27 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
43 compatible = "gpio-keys";
53 linux,code = <KEY_WPS_BUTTON>;
59 reg = <0 0x40000000 0 0x20000000>;
62 reg_1p8v: regulator-1p8v {
63 compatible = "regulator-fixed";
64 regulator-name = "fixed-1.8V";
65 regulator-min-microvolt = <1800000>;
66 regulator-max-microvolt = <1800000>;
70 reg_3p3v: regulator-3p3v {
71 compatible = "regulator-fixed";
72 regulator-name = "fixed-3.3V";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
79 reg_5v: regulator-5v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-5V";
82 regulator-min-microvolt = <5000000>;
83 regulator-max-microvolt = <5000000>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&irrx_pins>;
104 pinctrl-names = "default";
105 pinctrl-0 = <ð_pins>;
109 compatible = "mediatek,eth-mac";
111 phy-mode = "2500base-x";
121 #address-cells = <1>;
125 compatible = "mediatek,mt7531";
127 reset-gpios = <&pio 54 0>;
130 #address-cells = <1>;
162 phy-mode = "2500base-x";
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c1_pins>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&i2c2_pins>;
189 pinctrl-names = "default", "state_uhs";
190 pinctrl-0 = <&emmc_pins_default>;
191 pinctrl-1 = <&emmc_pins_uhs>;
194 max-frequency = <50000000>;
197 vmmc-supply = <®_3p3v>;
198 vqmmc-supply = <®_1p8v>;
199 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
200 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
205 pinctrl-names = "default", "state_uhs";
206 pinctrl-0 = <&sd0_pins_default>;
207 pinctrl-1 = <&sd0_pins_uhs>;
210 max-frequency = <50000000>;
212 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
213 vmmc-supply = <®_3p3v>;
214 vqmmc-supply = <®_3p3v>;
215 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
216 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
220 pinctrl-names = "default";
221 pinctrl-0 = <¶llel_nand_pins>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&spi_nor_pins>;
231 compatible = "jedec,spi-nor";
237 pinctrl-names = "default";
238 pinctrl-0 = <&pcie0_pins>;
243 /* eMMC is shared pin with parallel NAND */
244 emmc_pins_default: emmc-pins-default {
246 function = "emmc", "emmc_rst";
250 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
251 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
252 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
255 pins = "NDL0", "NDL1", "NDL2",
256 "NDL3", "NDL4", "NDL5",
257 "NDL6", "NDL7", "NRB";
268 emmc_pins_uhs: emmc-pins-uhs {
275 pins = "NDL0", "NDL1", "NDL2",
276 "NDL3", "NDL4", "NDL5",
277 "NDL6", "NDL7", "NRB";
279 drive-strength = <4>;
285 drive-strength = <4>;
293 groups = "mdc_mdio", "rgmii_via_gmac2";
297 i2c1_pins: i2c1-pins {
304 i2c2_pins: i2c2-pins {
311 i2s1_pins: i2s1-pins {
314 groups = "i2s_out_mclk_bclk_ws",
320 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
321 "I2S_WS", "I2S_MCLK";
322 drive-strength = <12>;
327 irrx_pins: irrx-pins {
334 irtx_pins: irtx-pins {
341 /* Parallel nand is shared pin with eMMC */
342 parallel_nand_pins: parallel-nand-pins {
349 pcie0_pins: pcie0-pins {
352 groups = "pcie0_pad_perst",
358 pcie1_pins: pcie1-pins {
361 groups = "pcie1_pad_perst",
367 pmic_bus_pins: pmic-bus-pins {
374 pwm7_pins: pwm1-2-pins {
377 groups = "pwm_ch7_2";
381 wled_pins: wled-pins {
388 sd0_pins_default: sd0-pins-default {
394 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
395 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
396 * DAT2, DAT3, CMD, CLK for SD respectively.
399 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
400 "I2S2_IN","I2S4_OUT";
402 drive-strength = <8>;
407 drive-strength = <12>;
416 sd0_pins_uhs: sd0-pins-uhs {
423 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
424 "I2S2_IN","I2S4_OUT";
435 /* Serial NAND is shared pin with SPI-NOR */
436 serial_nand_pins: serial-nand-pins {
443 spic0_pins: spic0-pins {
450 spic1_pins: spic1-pins {
457 /* SPI-NOR is shared pin with serial NAND */
458 spi_nor_pins: spi-nor-pins {
465 /* serial NAND is shared pin with SPI-NOR */
466 serial_nand_pins: serial-nand-pins {
473 uart0_pins: uart0-pins {
476 groups = "uart0_0_tx_rx" ;
480 uart2_pins: uart2-pins {
483 groups = "uart2_1_tx_rx" ;
487 watchdog_pins: watchdog-pins {
489 function = "watchdog";
494 wmac_pins: wmac-pins {
497 groups = "antsel0", "antsel1", "antsel2", "antsel3",
498 "antsel4", "antsel5", "antsel6", "antsel7",
499 "antsel8", "antsel9", "antsel12", "antsel13",
500 "antsel14", "antsel15", "antsel16", "antsel17";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pwm7_pins>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pmic_bus_pins>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&spic0_pins>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&spic1_pins>;
539 vusb33-supply = <®_3p3v>;
540 vbus-supply = <®_5v>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&uart0_pins>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&uart2_pins>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&watchdog_pins>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&wmac_pins>;