2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
27 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
43 compatible = "gpio-keys";
48 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_WPS_BUTTON>;
54 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
59 compatible = "gpio-leds";
62 label = "bpi-r64:pio:green";
63 color = <LED_COLOR_ID_GREEN>;
64 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
65 default-state = "off";
69 label = "bpi-r64:pio:red";
70 color = <LED_COLOR_ID_RED>;
71 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
72 default-state = "off";
77 reg = <0 0x40000000 0 0x40000000>;
80 reg_1p8v: regulator-1p8v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-1.8V";
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <1800000>;
88 reg_3p3v: regulator-3p3v {
89 compatible = "regulator-fixed";
90 regulator-name = "fixed-3.3V";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
97 reg_5v: regulator-5v {
98 compatible = "regulator-fixed";
99 regulator-name = "fixed-5V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&irrx_pins>;
124 compatible = "mediatek,eth-mac";
126 phy-mode = "2500base-x";
136 compatible = "mediatek,eth-mac";
148 #address-cells = <1>;
152 compatible = "mediatek,mt7531";
154 interrupt-controller;
155 #interrupt-cells = <1>;
156 interrupt-parent = <&pio>;
157 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
158 reset-gpios = <&pio 54 0>;
161 #address-cells = <1>;
193 phy-mode = "2500base-x";
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c1_pins>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&i2c2_pins>;
220 pinctrl-names = "default", "state_uhs";
221 pinctrl-0 = <&emmc_pins_default>;
222 pinctrl-1 = <&emmc_pins_uhs>;
225 max-frequency = <50000000>;
228 vmmc-supply = <®_3p3v>;
229 vqmmc-supply = <®_1p8v>;
230 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
231 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
236 pinctrl-names = "default", "state_uhs";
237 pinctrl-0 = <&sd0_pins_default>;
238 pinctrl-1 = <&sd0_pins_uhs>;
241 max-frequency = <50000000>;
243 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
244 vmmc-supply = <®_3p3v>;
245 vqmmc-supply = <®_3p3v>;
246 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
247 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
251 pinctrl-names = "default";
252 pinctrl-0 = <¶llel_nand_pins>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&serial_nand_pins>;
265 compatible = "spi-nand";
267 spi-tx-bus-width = <4>;
268 spi-rx-bus-width = <4>;
269 nand-ecc-engine = <&snfi>;
271 compatible = "fixed-partitions";
272 #address-cells = <1>;
283 reg = <0x80000 0x200000>;
287 ubi: partition@280000 {
289 reg = <0x280000 0x7d80000>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pcie0_pins>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pcie1_pins>;
308 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
309 * SATA functions. i.e. output-high: PCIe, output-low: SATA
313 gpios = <90 GPIO_ACTIVE_HIGH>;
317 /* eMMC is shared pin with parallel NAND */
318 emmc_pins_default: emmc-pins-default {
320 function = "emmc", "emmc_rst";
324 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
325 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
326 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
329 pins = "NDL0", "NDL1", "NDL2",
330 "NDL3", "NDL4", "NDL5",
331 "NDL6", "NDL7", "NRB";
342 emmc_pins_uhs: emmc-pins-uhs {
349 pins = "NDL0", "NDL1", "NDL2",
350 "NDL3", "NDL4", "NDL5",
351 "NDL6", "NDL7", "NRB";
353 drive-strength = <4>;
359 drive-strength = <4>;
367 groups = "mdc_mdio", "rgmii_via_gmac2";
371 i2c1_pins: i2c1-pins {
378 i2c2_pins: i2c2-pins {
385 i2s1_pins: i2s1-pins {
388 groups = "i2s_out_mclk_bclk_ws",
394 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
395 "I2S_WS", "I2S_MCLK";
396 drive-strength = <12>;
401 irrx_pins: irrx-pins {
408 irtx_pins: irtx-pins {
415 /* Parallel nand is shared pin with eMMC */
416 parallel_nand_pins: parallel-nand-pins {
423 pcie0_pins: pcie0-pins {
426 groups = "pcie0_pad_perst",
432 pcie1_pins: pcie1-pins {
435 groups = "pcie1_pad_perst",
441 pmic_bus_pins: pmic-bus-pins {
451 groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
452 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
453 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
454 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
455 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
456 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
460 wled_pins: wled-pins {
467 sd0_pins_default: sd0-pins-default {
473 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
474 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
475 * DAT2, DAT3, CMD, CLK for SD respectively.
478 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
479 "I2S2_IN","I2S4_OUT";
481 drive-strength = <8>;
486 drive-strength = <12>;
495 sd0_pins_uhs: sd0-pins-uhs {
502 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
503 "I2S2_IN","I2S4_OUT";
514 /* Serial NAND is shared pin with SPI-NOR */
515 serial_nand_pins: serial-nand-pins {
522 spic0_pins: spic0-pins {
529 spic1_pins: spic1-pins {
536 /* SPI-NOR is shared pin with serial NAND */
537 spi_nor_pins: spi-nor-pins {
544 /* serial NAND is shared pin with SPI-NOR */
545 serial_nand_pins: serial-nand-pins {
552 uart0_pins: uart0-pins {
555 groups = "uart0_0_tx_rx" ;
559 uart2_pins: uart2-pins {
562 groups = "uart2_1_tx_rx" ;
566 watchdog_pins: watchdog-pins {
568 function = "watchdog";
575 pinctrl-names = "default";
576 pinctrl-0 = <&pwm_pins>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pmic_bus_pins>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&spic0_pins>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&spic1_pins>;
607 vusb33-supply = <®_3p3v>;
608 vbus-supply = <®_5v>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart0_pins>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&uart2_pins>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&watchdog_pins>;