arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "Bananapi BPI-R64";
  17         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  53                 };
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 green {
  60                         label = "bpi-r64:pio:green";
  61                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  62                         default-state = "off";
  63                 };
  64
  65                 red {
  66                         label = "bpi-r64:pio:red";
  67                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  68                         default-state = "off";
  69                 };
  70         };
  71
  72         memory@40000000 {
  73                 reg = <0 0x40000000 0 0x40000000>;
  74                 device_type = "memory";
  75         };
  76
  77         reg_1p8v: regulator-1p8v {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "fixed-1.8V";
  80                 regulator-min-microvolt = <1800000>;
  81                 regulator-max-microvolt = <1800000>;
  82                 regulator-always-on;
  83         };
  84
  85         reg_3p3v: regulator-3p3v {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "fixed-3.3V";
  88                 regulator-min-microvolt = <3300000>;
  89                 regulator-max-microvolt = <3300000>;
  90                 regulator-boot-on;
  91                 regulator-always-on;
  92         };
  93
  94         reg_5v: regulator-5v {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "fixed-5V";
  97                 regulator-min-microvolt = <5000000>;
  98                 regulator-max-microvolt = <5000000>;
  99                 regulator-boot-on;
 100                 regulator-always-on;
 101         };
 102 };
 103
 104 &bch {
 105         status = "disabled";
 106 };
 107
 108 &btif {
 109         status = "okay";
 110 };
 111
 112 &cir {
 113         pinctrl-names = "default";
 114         pinctrl-0 = <&irrx_pins>;
 115         status = "okay";
 116 };
 117
 118 &eth {
 119         status = "okay";
 120         gmac0: mac@0 {
 121                 compatible = "mediatek,eth-mac";
 122                 reg = <0>;
 123                 phy-mode = "2500base-x";
 124
 125                 fixed-link {
 126                         speed = <2500>;
 127                         full-duplex;
 128                         pause;
 129                 };
 130         };
 131
 132         gmac1: mac@1 {
 133                 compatible = "mediatek,eth-mac";
 134                 reg = <1>;
 135                 phy-mode = "rgmii";
 136
 137                 fixed-link {
 138                         speed = <1000>;
 139                         full-duplex;
 140                         pause;
 141                 };
 142         };
 143
 144         mdio: mdio-bus {
 145                 #address-cells = <1>;
 146                 #size-cells = <0>;
 147         };
 148 };
 149
 150 &i2c1 {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&i2c1_pins>;
 153         status = "okay";
 154 };
 155
 156 &i2c2 {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&i2c2_pins>;
 159         status = "okay";
 160 };
 161
 162 &mmc0 {
 163         pinctrl-names = "default", "state_uhs";
 164         pinctrl-0 = <&emmc_pins_default>;
 165         pinctrl-1 = <&emmc_pins_uhs>;
 166         status = "okay";
 167         bus-width = <8>;
 168         max-frequency = <50000000>;
 169         cap-mmc-highspeed;
 170         mmc-hs200-1_8v;
 171         vmmc-supply = <&reg_3p3v>;
 172         vqmmc-supply = <&reg_1p8v>;
 173         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 174         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 175         non-removable;
 176 };
 177
 178 &mmc1 {
 179         pinctrl-names = "default", "state_uhs";
 180         pinctrl-0 = <&sd0_pins_default>;
 181         pinctrl-1 = <&sd0_pins_uhs>;
 182         status = "okay";
 183         bus-width = <4>;
 184         max-frequency = <50000000>;
 185         cap-sd-highspeed;
 186         r_smpl = <1>;
 187         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 188         vmmc-supply = <&reg_3p3v>;
 189         vqmmc-supply = <&reg_3p3v>;
 190         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 191         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 192 };
 193
 194 &nandc {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&parallel_nand_pins>;
 197         status = "disabled";
 198 };
 199
 200 &nor_flash {
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&spi_nor_pins>;
 203         status = "disabled";
 204
 205         flash@0 {
 206                 compatible = "jedec,spi-nor";
 207                 reg = <0>;
 208         };
 209 };
 210
 211 &pcie {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 214         status = "okay";
 215
 216         pcie@0,0 {
 217                 status = "okay";
 218         };
 219
 220         pcie@1,0 {
 221                 status = "okay";
 222         };
 223 };
 224
 225 &pio {
 226         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 227          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 228          */
 229         asm_sel {
 230                 gpio-hog;
 231                 gpios = <90 GPIO_ACTIVE_HIGH>;
 232                 output-high;
 233         };
 234
 235         /* eMMC is shared pin with parallel NAND */
 236         emmc_pins_default: emmc-pins-default {
 237                 mux {
 238                         function = "emmc", "emmc_rst";
 239                         groups = "emmc";
 240                 };
 241
 242                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 243                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 244                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 245                  */
 246                 conf-cmd-dat {
 247                         pins = "NDL0", "NDL1", "NDL2",
 248                                "NDL3", "NDL4", "NDL5",
 249                                "NDL6", "NDL7", "NRB";
 250                         input-enable;
 251                         bias-pull-up;
 252                 };
 253
 254                 conf-clk {
 255                         pins = "NCLE";
 256                         bias-pull-down;
 257                 };
 258         };
 259
 260         emmc_pins_uhs: emmc-pins-uhs {
 261                 mux {
 262                         function = "emmc";
 263                         groups = "emmc";
 264                 };
 265
 266                 conf-cmd-dat {
 267                         pins = "NDL0", "NDL1", "NDL2",
 268                                "NDL3", "NDL4", "NDL5",
 269                                "NDL6", "NDL7", "NRB";
 270                         input-enable;
 271                         drive-strength = <4>;
 272                         bias-pull-up;
 273                 };
 274
 275                 conf-clk {
 276                         pins = "NCLE";
 277                         drive-strength = <4>;
 278                         bias-pull-down;
 279                 };
 280         };
 281
 282         eth_pins: eth-pins {
 283                 mux {
 284                         function = "eth";
 285                         groups = "mdc_mdio", "rgmii_via_gmac2";
 286                 };
 287         };
 288
 289         i2c1_pins: i2c1-pins {
 290                 mux {
 291                         function = "i2c";
 292                         groups =  "i2c1_0";
 293                 };
 294         };
 295
 296         i2c2_pins: i2c2-pins {
 297                 mux {
 298                         function = "i2c";
 299                         groups =  "i2c2_0";
 300                 };
 301         };
 302
 303         i2s1_pins: i2s1-pins {
 304                 mux {
 305                         function = "i2s";
 306                         groups =  "i2s_out_mclk_bclk_ws",
 307                                   "i2s1_in_data",
 308                                   "i2s1_out_data";
 309                 };
 310
 311                 conf {
 312                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 313                                "I2S_WS", "I2S_MCLK";
 314                         drive-strength = <12>;
 315                         bias-pull-down;
 316                 };
 317         };
 318
 319         irrx_pins: irrx-pins {
 320                 mux {
 321                         function = "ir";
 322                         groups =  "ir_1_rx";
 323                 };
 324         };
 325
 326         irtx_pins: irtx-pins {
 327                 mux {
 328                         function = "ir";
 329                         groups =  "ir_1_tx";
 330                 };
 331         };
 332
 333         /* Parallel nand is shared pin with eMMC */
 334         parallel_nand_pins: parallel-nand-pins {
 335                 mux {
 336                         function = "flash";
 337                         groups = "par_nand";
 338                 };
 339         };
 340
 341         pcie0_pins: pcie0-pins {
 342                 mux {
 343                         function = "pcie";
 344                         groups = "pcie0_pad_perst",
 345                                  "pcie0_1_waken",
 346                                  "pcie0_1_clkreq";
 347                 };
 348         };
 349
 350         pcie1_pins: pcie1-pins {
 351                 mux {
 352                         function = "pcie";
 353                         groups = "pcie1_pad_perst",
 354                                  "pcie1_0_waken",
 355                                  "pcie1_0_clkreq";
 356                 };
 357         };
 358
 359         pmic_bus_pins: pmic-bus-pins {
 360                 mux {
 361                         function = "pmic";
 362                         groups = "pmic_bus";
 363                 };
 364         };
 365
 366         pwm7_pins: pwm1-2-pins {
 367                 mux {
 368                         function = "pwm";
 369                         groups = "pwm_ch7_2";
 370                 };
 371         };
 372
 373         wled_pins: wled-pins {
 374                 mux {
 375                         function = "led";
 376                         groups = "wled";
 377                 };
 378         };
 379
 380         sd0_pins_default: sd0-pins-default {
 381                 mux {
 382                         function = "sd";
 383                         groups = "sd_0";
 384                 };
 385
 386                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 387                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 388                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 389                  */
 390                 conf-cmd-data {
 391                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 392                                "I2S2_IN","I2S4_OUT";
 393                         input-enable;
 394                         drive-strength = <8>;
 395                         bias-pull-up;
 396                 };
 397                 conf-clk {
 398                         pins = "I2S3_OUT";
 399                         drive-strength = <12>;
 400                         bias-pull-down;
 401                 };
 402                 conf-cd {
 403                         pins = "TXD3";
 404                         bias-pull-up;
 405                 };
 406         };
 407
 408         sd0_pins_uhs: sd0-pins-uhs {
 409                 mux {
 410                         function = "sd";
 411                         groups = "sd_0";
 412                 };
 413
 414                 conf-cmd-data {
 415                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 416                                "I2S2_IN","I2S4_OUT";
 417                         input-enable;
 418                         bias-pull-up;
 419                 };
 420
 421                 conf-clk {
 422                         pins = "I2S3_OUT";
 423                         bias-pull-down;
 424                 };
 425         };
 426
 427         /* Serial NAND is shared pin with SPI-NOR */
 428         serial_nand_pins: serial-nand-pins {
 429                 mux {
 430                         function = "flash";
 431                         groups = "snfi";
 432                 };
 433         };
 434
 435         spic0_pins: spic0-pins {
 436                 mux {
 437                         function = "spi";
 438                         groups = "spic0_0";
 439                 };
 440         };
 441
 442         spic1_pins: spic1-pins {
 443                 mux {
 444                         function = "spi";
 445                         groups = "spic1_0";
 446                 };
 447         };
 448
 449         /* SPI-NOR is shared pin with serial NAND */
 450         spi_nor_pins: spi-nor-pins {
 451                 mux {
 452                         function = "flash";
 453                         groups = "spi_nor";
 454                 };
 455         };
 456
 457         /* serial NAND is shared pin with SPI-NOR */
 458         serial_nand_pins: serial-nand-pins {
 459                 mux {
 460                         function = "flash";
 461                         groups = "snfi";
 462                 };
 463         };
 464
 465         uart0_pins: uart0-pins {
 466                 mux {
 467                         function = "uart";
 468                         groups = "uart0_0_tx_rx" ;
 469                 };
 470         };
 471
 472         uart2_pins: uart2-pins {
 473                 mux {
 474                         function = "uart";
 475                         groups = "uart2_1_tx_rx" ;
 476                 };
 477         };
 478
 479         watchdog_pins: watchdog-pins {
 480                 mux {
 481                         function = "watchdog";
 482                         groups = "watchdog";
 483                 };
 484         };
 485 };
 486
 487 &pwm {
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&pwm7_pins>;
 490         status = "okay";
 491 };
 492
 493 &pwrap {
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&pmic_bus_pins>;
 496
 497         status = "okay";
 498 };
 499
 500 &sata {
 501         status = "disable";
 502 };
 503
 504 &sata_phy {
 505         status = "disable";
 506 };
 507
 508 &spi0 {
 509         pinctrl-names = "default";
 510         pinctrl-0 = <&spic0_pins>;
 511         status = "okay";
 512 };
 513
 514 &spi1 {
 515         pinctrl-names = "default";
 516         pinctrl-0 = <&spic1_pins>;
 517         status = "okay";
 518 };
 519
 520 &ssusb {
 521         vusb33-supply = <&reg_3p3v>;
 522         vbus-supply = <&reg_5v>;
 523         status = "okay";
 524 };
 525
 526 &u3phy {
 527         status = "okay";
 528 };
 529
 530 &uart0 {
 531         pinctrl-names = "default";
 532         pinctrl-0 = <&uart0_pins>;
 533         status = "okay";
 534 };
 535
 536 &uart2 {
 537         pinctrl-names = "default";
 538         pinctrl-0 = <&uart2_pins>;
 539         status = "okay";
 540 };
 541
 542 &watchdog {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&watchdog_pins>;
 545         status = "okay";
 546 };