arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/leds/common.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "Bananapi BPI-R64";
  18         chassis-type = "embedded";
  19         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  20
  21         aliases {
  22                 serial0 = &uart0;
  23         };
  24
  25         chosen {
  26                 stdout-path = "serial0:115200n8";
  27                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  28         };
  29
  30         cpus {
  31                 cpu@0 {
  32                         proc-supply = <&mt6380_vcpu_reg>;
  33                         sram-supply = <&mt6380_vm_reg>;
  34                 };
  35
  36                 cpu@1 {
  37                         proc-supply = <&mt6380_vcpu_reg>;
  38                         sram-supply = <&mt6380_vm_reg>;
  39                 };
  40         };
  41
  42         gpio-keys {
  43                 compatible = "gpio-keys";
  44
  45                 factory-key {
  46                         label = "factory";
  47                         linux,code = <BTN_0>;
  48                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  49                 };
  50
  51                 wps-key {
  52                         label = "wps";
  53                         linux,code = <KEY_WPS_BUTTON>;
  54                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  55                 };
  56         };
  57
  58         leds {
  59                 compatible = "gpio-leds";
  60
  61                 led-0 {
  62                         label = "bpi-r64:pio:green";
  63                         color = <LED_COLOR_ID_GREEN>;
  64                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  65                         default-state = "off";
  66                 };
  67
  68                 led-1 {
  69                         label = "bpi-r64:pio:red";
  70                         color = <LED_COLOR_ID_RED>;
  71                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  72                         default-state = "off";
  73                 };
  74         };
  75
  76         memory@40000000 {
  77                 reg = <0 0x40000000 0 0x40000000>;
  78         };
  79
  80         reg_1p8v: regulator-1p8v {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "fixed-1.8V";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <1800000>;
  85                 regulator-always-on;
  86         };
  87
  88         reg_3p3v: regulator-3p3v {
  89                 compatible = "regulator-fixed";
  90                 regulator-name = "fixed-3.3V";
  91                 regulator-min-microvolt = <3300000>;
  92                 regulator-max-microvolt = <3300000>;
  93                 regulator-boot-on;
  94                 regulator-always-on;
  95         };
  96
  97         reg_5v: regulator-5v {
  98                 compatible = "regulator-fixed";
  99                 regulator-name = "fixed-5V";
 100                 regulator-min-microvolt = <5000000>;
 101                 regulator-max-microvolt = <5000000>;
 102                 regulator-boot-on;
 103                 regulator-always-on;
 104         };
 105 };
 106
 107 &bch {
 108         status = "disabled";
 109 };
 110
 111 &btif {
 112         status = "okay";
 113 };
 114
 115 &cir {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&irrx_pins>;
 118         status = "okay";
 119 };
 120
 121 &eth {
 122         status = "okay";
 123         gmac0: mac@0 {
 124                 compatible = "mediatek,eth-mac";
 125                 reg = <0>;
 126                 phy-mode = "2500base-x";
 127
 128                 fixed-link {
 129                         speed = <2500>;
 130                         full-duplex;
 131                         pause;
 132                 };
 133         };
 134
 135         gmac1: mac@1 {
 136                 compatible = "mediatek,eth-mac";
 137                 reg = <1>;
 138                 phy-mode = "rgmii";
 139
 140                 fixed-link {
 141                         speed = <1000>;
 142                         full-duplex;
 143                         pause;
 144                 };
 145         };
 146
 147         mdio: mdio-bus {
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150
 151                 switch@0 {
 152                         compatible = "mediatek,mt7531";
 153                         reg = <0>;
 154                         interrupt-controller;
 155                         #interrupt-cells = <1>;
 156                         interrupt-parent = <&pio>;
 157                         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 158                         reset-gpios = <&pio 54 0>;
 159
 160                         ports {
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163
 164                                 port@0 {
 165                                         reg = <0>;
 166                                         label = "wan";
 167                                 };
 168
 169                                 port@1 {
 170                                         reg = <1>;
 171                                         label = "lan0";
 172                                 };
 173
 174                                 port@2 {
 175                                         reg = <2>;
 176                                         label = "lan1";
 177                                 };
 178
 179                                 port@3 {
 180                                         reg = <3>;
 181                                         label = "lan2";
 182                                 };
 183
 184                                 port@4 {
 185                                         reg = <4>;
 186                                         label = "lan3";
 187                                 };
 188
 189                                 port@6 {
 190                                         reg = <6>;
 191                                         label = "cpu";
 192                                         ethernet = <&gmac0>;
 193                                         phy-mode = "2500base-x";
 194
 195                                         fixed-link {
 196                                                 speed = <2500>;
 197                                                 full-duplex;
 198                                                 pause;
 199                                         };
 200                                 };
 201                         };
 202                 };
 203
 204         };
 205 };
 206
 207 &i2c1 {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&i2c1_pins>;
 210         status = "okay";
 211 };
 212
 213 &i2c2 {
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&i2c2_pins>;
 216         status = "okay";
 217 };
 218
 219 &mmc0 {
 220         pinctrl-names = "default", "state_uhs";
 221         pinctrl-0 = <&emmc_pins_default>;
 222         pinctrl-1 = <&emmc_pins_uhs>;
 223         status = "okay";
 224         bus-width = <8>;
 225         max-frequency = <50000000>;
 226         cap-mmc-highspeed;
 227         mmc-hs200-1_8v;
 228         vmmc-supply = <&reg_3p3v>;
 229         vqmmc-supply = <&reg_1p8v>;
 230         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 231         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 232         non-removable;
 233 };
 234
 235 &mmc1 {
 236         pinctrl-names = "default", "state_uhs";
 237         pinctrl-0 = <&sd0_pins_default>;
 238         pinctrl-1 = <&sd0_pins_uhs>;
 239         status = "okay";
 240         bus-width = <4>;
 241         max-frequency = <50000000>;
 242         cap-sd-highspeed;
 243         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 244         vmmc-supply = <&reg_3p3v>;
 245         vqmmc-supply = <&reg_3p3v>;
 246         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 247         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 248 };
 249
 250 &nandc {
 251         pinctrl-names = "default";
 252         pinctrl-0 = <&parallel_nand_pins>;
 253         status = "disabled";
 254 };
 255
 256 &bch {
 257         status = "okay";
 258 };
 259
 260 &snfi {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&serial_nand_pins>;
 263         status = "okay";
 264         flash@0 {
 265                 compatible = "spi-nand";
 266                 reg = <0>;
 267                 spi-tx-bus-width = <4>;
 268                 spi-rx-bus-width = <4>;
 269                 nand-ecc-engine = <&snfi>;
 270                 partitions {
 271                         compatible = "fixed-partitions";
 272                         #address-cells = <1>;
 273                         #size-cells = <1>;
 274
 275                         partition@0 {
 276                                 label = "bl2";
 277                                 reg = <0x0 0x80000>;
 278                                 read-only;
 279                         };
 280
 281                         partition@80000 {
 282                                 label = "fip";
 283                                 reg = <0x80000 0x200000>;
 284                                 read-only;
 285                         };
 286
 287                         ubi: partition@280000 {
 288                                 label = "ubi";
 289                                 reg = <0x280000 0x7d80000>;
 290                         };
 291                 };
 292         };
 293 };
 294
 295 &pcie0 {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pcie0_pins>;
 298         status = "okay";
 299 };
 300
 301 &pcie1 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pcie1_pins>;
 304         status = "okay";
 305 };
 306
 307 &pio {
 308         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 309          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 310          */
 311         asm_sel {
 312                 gpio-hog;
 313                 gpios = <90 GPIO_ACTIVE_HIGH>;
 314                 output-high;
 315         };
 316
 317         /* eMMC is shared pin with parallel NAND */
 318         emmc_pins_default: emmc-pins-default {
 319                 mux {
 320                         function = "emmc", "emmc_rst";
 321                         groups = "emmc";
 322                 };
 323
 324                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 325                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 326                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 327                  */
 328                 conf-cmd-dat {
 329                         pins = "NDL0", "NDL1", "NDL2",
 330                                "NDL3", "NDL4", "NDL5",
 331                                "NDL6", "NDL7", "NRB";
 332                         input-enable;
 333                         bias-pull-up;
 334                 };
 335
 336                 conf-clk {
 337                         pins = "NCLE";
 338                         bias-pull-down;
 339                 };
 340         };
 341
 342         emmc_pins_uhs: emmc-pins-uhs {
 343                 mux {
 344                         function = "emmc";
 345                         groups = "emmc";
 346                 };
 347
 348                 conf-cmd-dat {
 349                         pins = "NDL0", "NDL1", "NDL2",
 350                                "NDL3", "NDL4", "NDL5",
 351                                "NDL6", "NDL7", "NRB";
 352                         input-enable;
 353                         drive-strength = <4>;
 354                         bias-pull-up;
 355                 };
 356
 357                 conf-clk {
 358                         pins = "NCLE";
 359                         drive-strength = <4>;
 360                         bias-pull-down;
 361                 };
 362         };
 363
 364         eth_pins: eth-pins {
 365                 mux {
 366                         function = "eth";
 367                         groups = "mdc_mdio", "rgmii_via_gmac2";
 368                 };
 369         };
 370
 371         i2c1_pins: i2c1-pins {
 372                 mux {
 373                         function = "i2c";
 374                         groups = "i2c1_0";
 375                 };
 376         };
 377
 378         i2c2_pins: i2c2-pins {
 379                 mux {
 380                         function = "i2c";
 381                         groups = "i2c2_0";
 382                 };
 383         };
 384
 385         i2s1_pins: i2s1-pins {
 386                 mux {
 387                         function = "i2s";
 388                         groups = "i2s_out_mclk_bclk_ws",
 389                                  "i2s1_in_data",
 390                                  "i2s1_out_data";
 391                 };
 392
 393                 conf {
 394                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 395                                "I2S_WS", "I2S_MCLK";
 396                         drive-strength = <12>;
 397                         bias-pull-down;
 398                 };
 399         };
 400
 401         irrx_pins: irrx-pins {
 402                 mux {
 403                         function = "ir";
 404                         groups = "ir_1_rx";
 405                 };
 406         };
 407
 408         irtx_pins: irtx-pins {
 409                 mux {
 410                         function = "ir";
 411                         groups = "ir_1_tx";
 412                 };
 413         };
 414
 415         /* Parallel nand is shared pin with eMMC */
 416         parallel_nand_pins: parallel-nand-pins {
 417                 mux {
 418                         function = "flash";
 419                         groups = "par_nand";
 420                 };
 421         };
 422
 423         pcie0_pins: pcie0-pins {
 424                 mux {
 425                         function = "pcie";
 426                         groups = "pcie0_pad_perst",
 427                                  "pcie0_1_waken",
 428                                  "pcie0_1_clkreq";
 429                 };
 430         };
 431
 432         pcie1_pins: pcie1-pins {
 433                 mux {
 434                         function = "pcie";
 435                         groups = "pcie1_pad_perst",
 436                                  "pcie1_0_waken",
 437                                  "pcie1_0_clkreq";
 438                 };
 439         };
 440
 441         pmic_bus_pins: pmic-bus-pins {
 442                 mux {
 443                         function = "pmic";
 444                         groups = "pmic_bus";
 445                 };
 446         };
 447
 448         pwm_pins: pwm-pins {
 449                 mux {
 450                         function = "pwm";
 451                         groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
 452                                  "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
 453                                  "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
 454                                  "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
 455                                  "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
 456                                  "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
 457                 };
 458         };
 459
 460         wled_pins: wled-pins {
 461                 mux {
 462                         function = "led";
 463                         groups = "wled";
 464                 };
 465         };
 466
 467         sd0_pins_default: sd0-pins-default {
 468                 mux {
 469                         function = "sd";
 470                         groups = "sd_0";
 471                 };
 472
 473                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 474                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 475                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 476                  */
 477                 conf-cmd-data {
 478                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 479                                "I2S2_IN","I2S4_OUT";
 480                         input-enable;
 481                         drive-strength = <8>;
 482                         bias-pull-up;
 483                 };
 484                 conf-clk {
 485                         pins = "I2S3_OUT";
 486                         drive-strength = <12>;
 487                         bias-pull-down;
 488                 };
 489                 conf-cd {
 490                         pins = "TXD3";
 491                         bias-pull-up;
 492                 };
 493         };
 494
 495         sd0_pins_uhs: sd0-pins-uhs {
 496                 mux {
 497                         function = "sd";
 498                         groups = "sd_0";
 499                 };
 500
 501                 conf-cmd-data {
 502                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 503                                "I2S2_IN","I2S4_OUT";
 504                         input-enable;
 505                         bias-pull-up;
 506                 };
 507
 508                 conf-clk {
 509                         pins = "I2S3_OUT";
 510                         bias-pull-down;
 511                 };
 512         };
 513
 514         /* Serial NAND is shared pin with SPI-NOR */
 515         serial_nand_pins: serial-nand-pins {
 516                 mux {
 517                         function = "flash";
 518                         groups = "snfi";
 519                 };
 520         };
 521
 522         spic0_pins: spic0-pins {
 523                 mux {
 524                         function = "spi";
 525                         groups = "spic0_0";
 526                 };
 527         };
 528
 529         spic1_pins: spic1-pins {
 530                 mux {
 531                         function = "spi";
 532                         groups = "spic1_0";
 533                 };
 534         };
 535
 536         /* SPI-NOR is shared pin with serial NAND */
 537         spi_nor_pins: spi-nor-pins {
 538                 mux {
 539                         function = "flash";
 540                         groups = "spi_nor";
 541                 };
 542         };
 543
 544         /* serial NAND is shared pin with SPI-NOR */
 545         serial_nand_pins: serial-nand-pins {
 546                 mux {
 547                         function = "flash";
 548                         groups = "snfi";
 549                 };
 550         };
 551
 552         uart0_pins: uart0-pins {
 553                 mux {
 554                         function = "uart";
 555                         groups = "uart0_0_tx_rx" ;
 556                 };
 557         };
 558
 559         uart2_pins: uart2-pins {
 560                 mux {
 561                         function = "uart";
 562                         groups = "uart2_1_tx_rx" ;
 563                 };
 564         };
 565
 566         watchdog_pins: watchdog-pins {
 567                 mux {
 568                         function = "watchdog";
 569                         groups = "watchdog";
 570                 };
 571         };
 572 };
 573
 574 &pwm {
 575         pinctrl-names = "default";
 576         pinctrl-0 = <&pwm_pins>;
 577         status = "okay";
 578 };
 579
 580 &pwrap {
 581         pinctrl-names = "default";
 582         pinctrl-0 = <&pmic_bus_pins>;
 583
 584         status = "okay";
 585 };
 586
 587 &sata {
 588         status = "disabled";
 589 };
 590
 591 &sata_phy {
 592         status = "disabled";
 593 };
 594
 595 &spi0 {
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&spic0_pins>;
 598         status = "okay";
 599 };
 600
 601 &spi1 {
 602         pinctrl-names = "default";
 603         pinctrl-0 = <&spic1_pins>;
 604 };
 605
 606 &ssusb {
 607         vusb33-supply = <&reg_3p3v>;
 608         vbus-supply = <&reg_5v>;
 609         status = "okay";
 610 };
 611
 612 &u3phy {
 613         status = "okay";
 614 };
 615
 616 &uart0 {
 617         pinctrl-names = "default";
 618         pinctrl-0 = <&uart0_pins>;
 619         status = "okay";
 620 };
 621
 622 &uart2 {
 623         pinctrl-names = "default";
 624         pinctrl-0 = <&uart2_pins>;
 625 };
 626
 627 &watchdog {
 628         pinctrl-names = "default";
 629         pinctrl-0 = <&watchdog_pins>;
 630         status = "okay";
 631 };
 632
 633 &wmac {
 634         status = "okay";
 635 };