arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/leds/common.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "Bananapi BPI-R64";
  18         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43
  44                 factory-key {
  45                         label = "factory";
  46                         linux,code = <BTN_0>;
  47                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  48                 };
  49
  50                 wps-key {
  51                         label = "wps";
  52                         linux,code = <KEY_WPS_BUTTON>;
  53                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  54                 };
  55         };
  56
  57         leds {
  58                 compatible = "gpio-leds";
  59
  60                 led-0 {
  61                         label = "bpi-r64:pio:green";
  62                         color = <LED_COLOR_ID_GREEN>;
  63                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  64                         default-state = "off";
  65                 };
  66
  67                 led-1 {
  68                         label = "bpi-r64:pio:red";
  69                         color = <LED_COLOR_ID_RED>;
  70                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  71                         default-state = "off";
  72                 };
  73         };
  74
  75         memory@40000000 {
  76                 reg = <0 0x40000000 0 0x40000000>;
  77                 device_type = "memory";
  78         };
  79
  80         reg_1p8v: regulator-1p8v {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "fixed-1.8V";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <1800000>;
  85                 regulator-always-on;
  86         };
  87
  88         reg_3p3v: regulator-3p3v {
  89                 compatible = "regulator-fixed";
  90                 regulator-name = "fixed-3.3V";
  91                 regulator-min-microvolt = <3300000>;
  92                 regulator-max-microvolt = <3300000>;
  93                 regulator-boot-on;
  94                 regulator-always-on;
  95         };
  96
  97         reg_5v: regulator-5v {
  98                 compatible = "regulator-fixed";
  99                 regulator-name = "fixed-5V";
 100                 regulator-min-microvolt = <5000000>;
 101                 regulator-max-microvolt = <5000000>;
 102                 regulator-boot-on;
 103                 regulator-always-on;
 104         };
 105 };
 106
 107 &bch {
 108         status = "disabled";
 109 };
 110
 111 &btif {
 112         status = "okay";
 113 };
 114
 115 &cir {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&irrx_pins>;
 118         status = "okay";
 119 };
 120
 121 &eth {
 122         status = "okay";
 123         gmac0: mac@0 {
 124                 compatible = "mediatek,eth-mac";
 125                 reg = <0>;
 126                 phy-mode = "2500base-x";
 127
 128                 fixed-link {
 129                         speed = <2500>;
 130                         full-duplex;
 131                         pause;
 132                 };
 133         };
 134
 135         gmac1: mac@1 {
 136                 compatible = "mediatek,eth-mac";
 137                 reg = <1>;
 138                 phy-mode = "rgmii";
 139
 140                 fixed-link {
 141                         speed = <1000>;
 142                         full-duplex;
 143                         pause;
 144                 };
 145         };
 146
 147         mdio: mdio-bus {
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150
 151                 switch@0 {
 152                         compatible = "mediatek,mt7531";
 153                         reg = <0>;
 154                         reset-gpios = <&pio 54 0>;
 155
 156                         ports {
 157                                 #address-cells = <1>;
 158                                 #size-cells = <0>;
 159
 160                                 port@0 {
 161                                         reg = <0>;
 162                                         label = "wan";
 163                                 };
 164
 165                                 port@1 {
 166                                         reg = <1>;
 167                                         label = "lan0";
 168                                 };
 169
 170                                 port@2 {
 171                                         reg = <2>;
 172                                         label = "lan1";
 173                                 };
 174
 175                                 port@3 {
 176                                         reg = <3>;
 177                                         label = "lan2";
 178                                 };
 179
 180                                 port@4 {
 181                                         reg = <4>;
 182                                         label = "lan3";
 183                                 };
 184
 185                                 port@6 {
 186                                         reg = <6>;
 187                                         label = "cpu";
 188                                         ethernet = <&gmac0>;
 189                                         phy-mode = "2500base-x";
 190
 191                                         fixed-link {
 192                                                 speed = <2500>;
 193                                                 full-duplex;
 194                                                 pause;
 195                                         };
 196                                 };
 197                         };
 198                 };
 199
 200         };
 201 };
 202
 203 &i2c1 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&i2c1_pins>;
 206         status = "okay";
 207 };
 208
 209 &i2c2 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&i2c2_pins>;
 212         status = "okay";
 213 };
 214
 215 &mmc0 {
 216         pinctrl-names = "default", "state_uhs";
 217         pinctrl-0 = <&emmc_pins_default>;
 218         pinctrl-1 = <&emmc_pins_uhs>;
 219         status = "okay";
 220         bus-width = <8>;
 221         max-frequency = <50000000>;
 222         cap-mmc-highspeed;
 223         mmc-hs200-1_8v;
 224         vmmc-supply = <&reg_3p3v>;
 225         vqmmc-supply = <&reg_1p8v>;
 226         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 227         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 228         non-removable;
 229 };
 230
 231 &mmc1 {
 232         pinctrl-names = "default", "state_uhs";
 233         pinctrl-0 = <&sd0_pins_default>;
 234         pinctrl-1 = <&sd0_pins_uhs>;
 235         status = "okay";
 236         bus-width = <4>;
 237         max-frequency = <50000000>;
 238         cap-sd-highspeed;
 239         r_smpl = <1>;
 240         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 241         vmmc-supply = <&reg_3p3v>;
 242         vqmmc-supply = <&reg_3p3v>;
 243         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 244         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 245 };
 246
 247 &nandc {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&parallel_nand_pins>;
 250         status = "disabled";
 251 };
 252
 253 &nor_flash {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&spi_nor_pins>;
 256         status = "disabled";
 257
 258         flash@0 {
 259                 compatible = "jedec,spi-nor";
 260                 reg = <0>;
 261         };
 262 };
 263
 264 &pcie0 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pcie0_pins>;
 267         status = "okay";
 268 };
 269
 270 &pcie1 {
 271         pinctrl-names = "default";
 272         pinctrl-0 = <&pcie1_pins>;
 273         status = "okay";
 274 };
 275
 276 &pio {
 277         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 278          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 279          */
 280         asm_sel {
 281                 gpio-hog;
 282                 gpios = <90 GPIO_ACTIVE_HIGH>;
 283                 output-high;
 284         };
 285
 286         /* eMMC is shared pin with parallel NAND */
 287         emmc_pins_default: emmc-pins-default {
 288                 mux {
 289                         function = "emmc", "emmc_rst";
 290                         groups = "emmc";
 291                 };
 292
 293                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 294                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 295                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 296                  */
 297                 conf-cmd-dat {
 298                         pins = "NDL0", "NDL1", "NDL2",
 299                                "NDL3", "NDL4", "NDL5",
 300                                "NDL6", "NDL7", "NRB";
 301                         input-enable;
 302                         bias-pull-up;
 303                 };
 304
 305                 conf-clk {
 306                         pins = "NCLE";
 307                         bias-pull-down;
 308                 };
 309         };
 310
 311         emmc_pins_uhs: emmc-pins-uhs {
 312                 mux {
 313                         function = "emmc";
 314                         groups = "emmc";
 315                 };
 316
 317                 conf-cmd-dat {
 318                         pins = "NDL0", "NDL1", "NDL2",
 319                                "NDL3", "NDL4", "NDL5",
 320                                "NDL6", "NDL7", "NRB";
 321                         input-enable;
 322                         drive-strength = <4>;
 323                         bias-pull-up;
 324                 };
 325
 326                 conf-clk {
 327                         pins = "NCLE";
 328                         drive-strength = <4>;
 329                         bias-pull-down;
 330                 };
 331         };
 332
 333         eth_pins: eth-pins {
 334                 mux {
 335                         function = "eth";
 336                         groups = "mdc_mdio", "rgmii_via_gmac2";
 337                 };
 338         };
 339
 340         i2c1_pins: i2c1-pins {
 341                 mux {
 342                         function = "i2c";
 343                         groups = "i2c1_0";
 344                 };
 345         };
 346
 347         i2c2_pins: i2c2-pins {
 348                 mux {
 349                         function = "i2c";
 350                         groups = "i2c2_0";
 351                 };
 352         };
 353
 354         i2s1_pins: i2s1-pins {
 355                 mux {
 356                         function = "i2s";
 357                         groups =  "i2s_out_mclk_bclk_ws",
 358                                   "i2s1_in_data",
 359                                   "i2s1_out_data";
 360                 };
 361
 362                 conf {
 363                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 364                                "I2S_WS", "I2S_MCLK";
 365                         drive-strength = <12>;
 366                         bias-pull-down;
 367                 };
 368         };
 369
 370         irrx_pins: irrx-pins {
 371                 mux {
 372                         function = "ir";
 373                         groups = "ir_1_rx";
 374                 };
 375         };
 376
 377         irtx_pins: irtx-pins {
 378                 mux {
 379                         function = "ir";
 380                         groups = "ir_1_tx";
 381                 };
 382         };
 383
 384         /* Parallel nand is shared pin with eMMC */
 385         parallel_nand_pins: parallel-nand-pins {
 386                 mux {
 387                         function = "flash";
 388                         groups = "par_nand";
 389                 };
 390         };
 391
 392         pcie0_pins: pcie0-pins {
 393                 mux {
 394                         function = "pcie";
 395                         groups = "pcie0_pad_perst",
 396                                  "pcie0_1_waken",
 397                                  "pcie0_1_clkreq";
 398                 };
 399         };
 400
 401         pcie1_pins: pcie1-pins {
 402                 mux {
 403                         function = "pcie";
 404                         groups = "pcie1_pad_perst",
 405                                  "pcie1_0_waken",
 406                                  "pcie1_0_clkreq";
 407                 };
 408         };
 409
 410         pmic_bus_pins: pmic-bus-pins {
 411                 mux {
 412                         function = "pmic";
 413                         groups = "pmic_bus";
 414                 };
 415         };
 416
 417         pwm_pins: pwm-pins {
 418                 mux {
 419                         function = "pwm";
 420                         groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
 421                                  "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
 422                                  "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
 423                                  "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
 424                                  "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
 425                                  "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
 426                 };
 427         };
 428
 429         wled_pins: wled-pins {
 430                 mux {
 431                         function = "led";
 432                         groups = "wled";
 433                 };
 434         };
 435
 436         sd0_pins_default: sd0-pins-default {
 437                 mux {
 438                         function = "sd";
 439                         groups = "sd_0";
 440                 };
 441
 442                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 443                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 444                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 445                  */
 446                 conf-cmd-data {
 447                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 448                                "I2S2_IN","I2S4_OUT";
 449                         input-enable;
 450                         drive-strength = <8>;
 451                         bias-pull-up;
 452                 };
 453                 conf-clk {
 454                         pins = "I2S3_OUT";
 455                         drive-strength = <12>;
 456                         bias-pull-down;
 457                 };
 458                 conf-cd {
 459                         pins = "TXD3";
 460                         bias-pull-up;
 461                 };
 462         };
 463
 464         sd0_pins_uhs: sd0-pins-uhs {
 465                 mux {
 466                         function = "sd";
 467                         groups = "sd_0";
 468                 };
 469
 470                 conf-cmd-data {
 471                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 472                                "I2S2_IN","I2S4_OUT";
 473                         input-enable;
 474                         bias-pull-up;
 475                 };
 476
 477                 conf-clk {
 478                         pins = "I2S3_OUT";
 479                         bias-pull-down;
 480                 };
 481         };
 482
 483         /* Serial NAND is shared pin with SPI-NOR */
 484         serial_nand_pins: serial-nand-pins {
 485                 mux {
 486                         function = "flash";
 487                         groups = "snfi";
 488                 };
 489         };
 490
 491         spic0_pins: spic0-pins {
 492                 mux {
 493                         function = "spi";
 494                         groups = "spic0_0";
 495                 };
 496         };
 497
 498         spic1_pins: spic1-pins {
 499                 mux {
 500                         function = "spi";
 501                         groups = "spic1_0";
 502                 };
 503         };
 504
 505         /* SPI-NOR is shared pin with serial NAND */
 506         spi_nor_pins: spi-nor-pins {
 507                 mux {
 508                         function = "flash";
 509                         groups = "spi_nor";
 510                 };
 511         };
 512
 513         /* serial NAND is shared pin with SPI-NOR */
 514         serial_nand_pins: serial-nand-pins {
 515                 mux {
 516                         function = "flash";
 517                         groups = "snfi";
 518                 };
 519         };
 520
 521         uart0_pins: uart0-pins {
 522                 mux {
 523                         function = "uart";
 524                         groups = "uart0_0_tx_rx" ;
 525                 };
 526         };
 527
 528         uart2_pins: uart2-pins {
 529                 mux {
 530                         function = "uart";
 531                         groups = "uart2_1_tx_rx" ;
 532                 };
 533         };
 534
 535         watchdog_pins: watchdog-pins {
 536                 mux {
 537                         function = "watchdog";
 538                         groups = "watchdog";
 539                 };
 540         };
 541 };
 542
 543 &pwm {
 544         pinctrl-names = "default";
 545         pinctrl-0 = <&pwm_pins>;
 546         status = "okay";
 547 };
 548
 549 &pwrap {
 550         pinctrl-names = "default";
 551         pinctrl-0 = <&pmic_bus_pins>;
 552
 553         status = "okay";
 554 };
 555
 556 &sata {
 557         status = "disable";
 558 };
 559
 560 &sata_phy {
 561         status = "disable";
 562 };
 563
 564 &spi0 {
 565         pinctrl-names = "default";
 566         pinctrl-0 = <&spic0_pins>;
 567         status = "okay";
 568 };
 569
 570 &spi1 {
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&spic1_pins>;
 573 };
 574
 575 &ssusb {
 576         vusb33-supply = <&reg_3p3v>;
 577         vbus-supply = <&reg_5v>;
 578         status = "okay";
 579 };
 580
 581 &u3phy {
 582         status = "okay";
 583 };
 584
 585 &uart0 {
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&uart0_pins>;
 588         status = "okay";
 589 };
 590
 591 &uart2 {
 592         pinctrl-names = "default";
 593         pinctrl-0 = <&uart2_pins>;
 594 };
 595
 596 &watchdog {
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&watchdog_pins>;
 599         status = "okay";
 600 };
 601
 602 &wmac {
 603         status = "okay";
 604 };