1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: Mars.C <mars.cheng@mediatek.com>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "mediatek,mt6755";
12 interrupt-parent = <&sysirq>;
17 compatible = "arm,psci-0.2";
27 compatible = "arm,cortex-a53";
28 enable-method = "psci";
34 compatible = "arm,cortex-a53";
35 enable-method = "psci";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
48 compatible = "arm,cortex-a53";
49 enable-method = "psci";
55 compatible = "arm,cortex-a53";
56 enable-method = "psci";
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
69 compatible = "arm,cortex-a53";
70 enable-method = "psci";
76 compatible = "arm,cortex-a53";
77 enable-method = "psci";
83 compatible = "fixed-clock";
84 clock-frequency = <26000000>;
89 compatible = "arm,armv8-timer";
90 interrupt-parent = <&gic>;
91 interrupts = <GIC_PPI 13
92 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
94 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
96 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
98 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
101 sysirq: intpol-controller@10200620 {
102 compatible = "mediatek,mt6755-sysirq",
103 "mediatek,mt6577-sysirq";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 interrupt-parent = <&gic>;
107 reg = <0 0x10200620 0 0x20>;
110 gic: interrupt-controller@10231000 {
111 compatible = "arm,gic-400";
112 #interrupt-cells = <3>;
113 interrupt-parent = <&gic>;
114 interrupt-controller;
115 reg = <0 0x10231000 0 0x1000>,
116 <0 0x10232000 0 0x2000>,
117 <0 0x10234000 0 0x2000>,
118 <0 0x10236000 0 0x2000>;
121 uart0: serial@11002000 {
122 compatible = "mediatek,mt6755-uart",
123 "mediatek,mt6577-uart";
124 reg = <0 0x11002000 0 0x400>;
125 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
126 clocks = <&uart_clk>;
130 uart1: serial@11003000 {
131 compatible = "mediatek,mt6755-uart",
132 "mediatek,mt6577-uart";
133 reg = <0 0x11003000 0 0x400>;
134 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
135 clocks = <&uart_clk>;