arch/arm64/boot/dts/mediatek/mt2712e.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: YT Shen <yt.shen@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt2712-clk.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/memory/mt2712-larb-port.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt2712-power.h>
  14 #include "mt2712-pinfunc.h"
  15
  16 / {
  17         compatible = "mediatek,mt2712";
  18         interrupt-parent = <&sysirq>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cluster0_opp: opp-table-0 {
  23                 compatible = "operating-points-v2";
  24                 opp-shared;
  25                 opp00 {
  26                         opp-hz = /bits/ 64 <598000000>;
  27                         opp-microvolt = <1000000>;
  28                 };
  29                 opp01 {
  30                         opp-hz = /bits/ 64 <702000000>;
  31                         opp-microvolt = <1000000>;
  32                 };
  33                 opp02 {
  34                         opp-hz = /bits/ 64 <793000000>;
  35                         opp-microvolt = <1000000>;
  36                 };
  37         };
  38
  39         cluster1_opp: opp-table-1 {
  40                 compatible = "operating-points-v2";
  41                 opp-shared;
  42                 opp00 {
  43                         opp-hz = /bits/ 64 <598000000>;
  44                         opp-microvolt = <1000000>;
  45                 };
  46                 opp01 {
  47                         opp-hz = /bits/ 64 <702000000>;
  48                         opp-microvolt = <1000000>;
  49                 };
  50                 opp02 {
  51                         opp-hz = /bits/ 64 <793000000>;
  52                         opp-microvolt = <1000000>;
  53                 };
  54                 opp03 {
  55                         opp-hz = /bits/ 64 <897000000>;
  56                         opp-microvolt = <1000000>;
  57                 };
  58                 opp04 {
  59                         opp-hz = /bits/ 64 <1001000000>;
  60                         opp-microvolt = <1000000>;
  61                 };
  62         };
  63
  64         cpus {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67
  68                 cpu-map {
  69                         cluster0 {
  70                                 core0 {
  71                                         cpu = <&cpu0>;
  72                                 };
  73                                 core1 {
  74                                         cpu = <&cpu1>;
  75                                 };
  76                         };
  77
  78                         cluster1 {
  79                                 core0 {
  80                                         cpu = <&cpu2>;
  81                                 };
  82                         };
  83                 };
  84
  85                 cpu0: cpu@0 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a35";
  88                         reg = <0x000>;
  89                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
  90                                 <&topckgen CLK_TOP_F_MP0_PLL1>;
  91                         clock-names = "cpu", "intermediate";
  92                         proc-supply = <&cpus_fixed_vproc0>;
  93                         operating-points-v2 = <&cluster0_opp>;
  94                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  95                 };
  96
  97                 cpu1: cpu@1 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a35";
 100                         reg = <0x001>;
 101                         enable-method = "psci";
 102                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
 103                                 <&topckgen CLK_TOP_F_MP0_PLL1>;
 104                         clock-names = "cpu", "intermediate";
 105                         proc-supply = <&cpus_fixed_vproc0>;
 106                         operating-points-v2 = <&cluster0_opp>;
 107                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 108                 };
 109
 110                 cpu2: cpu@200 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a72";
 113                         reg = <0x200>;
 114                         enable-method = "psci";
 115                         clocks = <&mcucfg CLK_MCU_MP2_SEL>,
 116                                 <&topckgen CLK_TOP_F_BIG_PLL1>;
 117                         clock-names = "cpu", "intermediate";
 118                         proc-supply = <&cpus_fixed_vproc1>;
 119                         operating-points-v2 = <&cluster1_opp>;
 120                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 121                 };
 122
 123                 idle-states {
 124                         entry-method = "psci";
 125
 126                         CPU_SLEEP_0: cpu-sleep-0 {
 127                                 compatible = "arm,idle-state";
 128                                 local-timer-stop;
 129                                 entry-latency-us = <100>;
 130                                 exit-latency-us = <80>;
 131                                 min-residency-us = <2000>;
 132                                 arm,psci-suspend-param = <0x0010000>;
 133                         };
 134
 135                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 136                                 compatible = "arm,idle-state";
 137                                 local-timer-stop;
 138                                 entry-latency-us = <350>;
 139                                 exit-latency-us = <80>;
 140                                 min-residency-us = <3000>;
 141                                 arm,psci-suspend-param = <0x1010000>;
 142                         };
 143                 };
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-0.2";
 148                 method = "smc";
 149         };
 150
 151         baud_clk: dummy26m {
 152                 compatible = "fixed-clock";
 153                 clock-frequency = <26000000>;
 154                 #clock-cells = <0>;
 155         };
 156
 157         sys_clk: dummyclk {
 158                 compatible = "fixed-clock";
 159                 clock-frequency = <26000000>;
 160                 #clock-cells = <0>;
 161         };
 162
 163         clk26m: oscillator-26m {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 clock-frequency = <26000000>;
 167                 clock-output-names = "clk26m";
 168         };
 169
 170         clk32k: oscillator-32k {
 171                 compatible = "fixed-clock";
 172                 #clock-cells = <0>;
 173                 clock-frequency = <32768>;
 174                 clock-output-names = "clk32k";
 175         };
 176
 177         clkfpc: oscillator-50m {
 178                 compatible = "fixed-clock";
 179                 #clock-cells = <0>;
 180                 clock-frequency = <50000000>;
 181                 clock-output-names = "clkfpc";
 182         };
 183
 184         clkaud_ext_i_0: oscillator-aud0 {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency = <6500000>;
 188                 clock-output-names = "clkaud_ext_i_0";
 189         };
 190
 191         clkaud_ext_i_1: oscillator-aud1 {
 192                 compatible = "fixed-clock";
 193                 #clock-cells = <0>;
 194                 clock-frequency = <196608000>;
 195                 clock-output-names = "clkaud_ext_i_1";
 196         };
 197
 198         clkaud_ext_i_2: oscillator-aud2 {
 199                 compatible = "fixed-clock";
 200                 #clock-cells = <0>;
 201                 clock-frequency = <180633600>;
 202                 clock-output-names = "clkaud_ext_i_2";
 203         };
 204
 205         clki2si0_mck_i: oscillator-i2s0 {
 206                 compatible = "fixed-clock";
 207                 #clock-cells = <0>;
 208                 clock-frequency = <30000000>;
 209                 clock-output-names = "clki2si0_mck_i";
 210         };
 211
 212         clki2si1_mck_i: oscillator-i2s1 {
 213                 compatible = "fixed-clock";
 214                 #clock-cells = <0>;
 215                 clock-frequency = <30000000>;
 216                 clock-output-names = "clki2si1_mck_i";
 217         };
 218
 219         clki2si2_mck_i: oscillator-i2s2 {
 220                 compatible = "fixed-clock";
 221                 #clock-cells = <0>;
 222                 clock-frequency = <30000000>;
 223                 clock-output-names = "clki2si2_mck_i";
 224         };
 225
 226         clktdmin_mclk_i: oscillator-mclk {
 227                 compatible = "fixed-clock";
 228                 #clock-cells = <0>;
 229                 clock-frequency = <30000000>;
 230                 clock-output-names = "clktdmin_mclk_i";
 231         };
 232
 233         timer {
 234                 compatible = "arm,armv8-timer";
 235                 interrupt-parent = <&gic>;
 236                 interrupts = <GIC_PPI 13
 237                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 238                              <GIC_PPI 14
 239                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 240                              <GIC_PPI 11
 241                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>,
 242                              <GIC_PPI 10
 243                               (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
 244         };
 245
 246         topckgen: syscon@10000000 {
 247                 compatible = "mediatek,mt2712-topckgen", "syscon";
 248                 reg = <0 0x10000000 0 0x1000>;
 249                 #clock-cells = <1>;
 250         };
 251
 252         infracfg: clock-controller@10001000 {
 253                 compatible = "mediatek,mt2712-infracfg", "syscon";
 254                 reg = <0 0x10001000 0 0x1000>;
 255                 #clock-cells = <1>;
 256                 #reset-cells = <1>;
 257         };
 258
 259         pericfg: syscon@10003000 {
 260                 compatible = "mediatek,mt2712-pericfg", "syscon";
 261                 reg = <0 0x10003000 0 0x1000>;
 262                 #clock-cells = <1>;
 263         };
 264
 265         syscfg_pctl_a: syscfg_pctl_a@10005000 {
 266                 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
 267                 reg = <0 0x10005000 0 0x1000>;
 268         };
 269
 270         pio: pinctrl@1000b000 {
 271                 compatible = "mediatek,mt2712-pinctrl";
 272                 reg = <0 0x1000b000 0 0x1000>;
 273                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 274                 pins-are-numbered;
 275                 gpio-controller;
 276                 #gpio-cells = <2>;
 277                 interrupt-controller;
 278                 #interrupt-cells = <2>;
 279                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 280         };
 281
 282         scpsys: power-controller@10006000 {
 283                 compatible = "mediatek,mt2712-scpsys", "syscon";
 284                 #power-domain-cells = <1>;
 285                 reg = <0 0x10006000 0 0x1000>;
 286                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 287                          <&topckgen CLK_TOP_MFG_SEL>,
 288                          <&topckgen CLK_TOP_VENC_SEL>,
 289                          <&topckgen CLK_TOP_JPGDEC_SEL>,
 290                          <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 291                          <&topckgen CLK_TOP_VDEC_SEL>;
 292                 clock-names = "mm", "mfg", "venc",
 293                         "jpgdec", "audio", "vdec";
 294                 infracfg = <&infracfg>;
 295         };
 296
 297         uart5: serial@1000f000 {
 298                 compatible = "mediatek,mt2712-uart",
 299                              "mediatek,mt6577-uart";
 300                 reg = <0 0x1000f000 0 0x400>;
 301                 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
 302                 clocks = <&baud_clk>, <&sys_clk>;
 303                 clock-names = "baud", "bus";
 304                 dmas = <&apdma 10
 305                         &apdma 11>;
 306                 dma-names = "tx", "rx";
 307                 status = "disabled";
 308         };
 309
 310         rtc: rtc@10011000 {
 311                 compatible = "mediatek,mt2712-rtc";
 312                 reg = <0 0x10011000 0 0x1000>;
 313                 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>;
 314         };
 315
 316         spis1: spi@10013000 {
 317                 compatible = "mediatek,mt2712-spi-slave";
 318                 reg = <0 0x10013000 0 0x100>;
 319                 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
 320                 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
 321                 clock-names = "spi";
 322                 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
 323                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
 324                 status = "disabled";
 325         };
 326
 327         iommu0: iommu@10205000 {
 328                 compatible = "mediatek,mt2712-m4u";
 329                 reg = <0 0x10205000 0 0x1000>;
 330                 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
 331                 clocks = <&infracfg CLK_INFRA_M4U>;
 332                 clock-names = "bclk";
 333                 mediatek,infracfg = <&infracfg>;
 334                 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
 335                                  <&larb3>, <&larb6>;
 336                 #iommu-cells = <1>;
 337         };
 338
 339         apmixedsys: syscon@10209000 {
 340                 compatible = "mediatek,mt2712-apmixedsys", "syscon";
 341                 reg = <0 0x10209000 0 0x1000>;
 342                 #clock-cells = <1>;
 343         };
 344
 345         iommu1: iommu@1020a000 {
 346                 compatible = "mediatek,mt2712-m4u";
 347                 reg = <0 0x1020a000 0 0x1000>;
 348                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 349                 clocks = <&infracfg CLK_INFRA_M4U>;
 350                 clock-names = "bclk";
 351                 mediatek,infracfg = <&infracfg>;
 352                 mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
 353                 #iommu-cells = <1>;
 354         };
 355
 356         mcucfg: syscon@10220000 {
 357                 compatible = "mediatek,mt2712-mcucfg", "syscon";
 358                 reg = <0 0x10220000 0 0x1000>;
 359                 #clock-cells = <1>;
 360         };
 361
 362         sysirq: interrupt-controller@10220a80 {
 363                 compatible = "mediatek,mt2712-sysirq",
 364                              "mediatek,mt6577-sysirq";
 365                 interrupt-controller;
 366                 #interrupt-cells = <3>;
 367                 interrupt-parent = <&gic>;
 368                 reg = <0 0x10220a80 0 0x40>;
 369         };
 370
 371         gic: interrupt-controller@10510000 {
 372                 compatible = "arm,gic-400";
 373                 #interrupt-cells = <3>;
 374                 interrupt-parent = <&gic>;
 375                 interrupt-controller;
 376                 reg = <0 0x10510000 0 0x10000>,
 377                       <0 0x10520000 0 0x20000>,
 378                       <0 0x10540000 0 0x20000>,
 379                       <0 0x10560000 0 0x20000>;
 380                 interrupts = <GIC_PPI 9
 381                          (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>;
 382         };
 383
 384         apdma: dma-controller@11000400 {
 385                 compatible = "mediatek,mt2712-uart-dma",
 386                              "mediatek,mt6577-uart-dma";
 387                 reg = <0 0x11000400 0 0x80>,
 388                       <0 0x11000480 0 0x80>,
 389                       <0 0x11000500 0 0x80>,
 390                       <0 0x11000580 0 0x80>,
 391                       <0 0x11000600 0 0x80>,
 392                       <0 0x11000680 0 0x80>,
 393                       <0 0x11000700 0 0x80>,
 394                       <0 0x11000780 0 0x80>,
 395                       <0 0x11000800 0 0x80>,
 396                       <0 0x11000880 0 0x80>,
 397                       <0 0x11000900 0 0x80>,
 398                       <0 0x11000980 0 0x80>;
 399                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
 400                              <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 401                              <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
 402                              <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
 403                              <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
 404                              <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
 405                              <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
 406                              <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
 407                              <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
 408                              <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
 409                              <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
 410                              <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
 411                 dma-requests = <12>;
 412                 clocks = <&pericfg CLK_PERI_AP_DMA>;
 413                 clock-names = "apdma";
 414                 #dma-cells = <1>;
 415         };
 416
 417         auxadc: adc@11001000 {
 418                 compatible = "mediatek,mt2712-auxadc";
 419                 reg = <0 0x11001000 0 0x1000>;
 420                 clocks = <&pericfg CLK_PERI_AUXADC>;
 421                 clock-names = "main";
 422                 #io-channel-cells = <1>;
 423                 status = "disabled";
 424         };
 425
 426         uart0: serial@11002000 {
 427                 compatible = "mediatek,mt2712-uart",
 428                              "mediatek,mt6577-uart";
 429                 reg = <0 0x11002000 0 0x400>;
 430                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 431                 clocks = <&baud_clk>, <&sys_clk>;
 432                 clock-names = "baud", "bus";
 433                 dmas = <&apdma 0
 434                         &apdma 1>;
 435                 dma-names = "tx", "rx";
 436                 status = "disabled";
 437         };
 438
 439         uart1: serial@11003000 {
 440                 compatible = "mediatek,mt2712-uart",
 441                              "mediatek,mt6577-uart";
 442                 reg = <0 0x11003000 0 0x400>;
 443                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 444                 clocks = <&baud_clk>, <&sys_clk>;
 445                 clock-names = "baud", "bus";
 446                 dmas = <&apdma 2
 447                         &apdma 3>;
 448                 dma-names = "tx", "rx";
 449                 status = "disabled";
 450         };
 451
 452         uart2: serial@11004000 {
 453                 compatible = "mediatek,mt2712-uart",
 454                              "mediatek,mt6577-uart";
 455                 reg = <0 0x11004000 0 0x400>;
 456                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 457                 clocks = <&baud_clk>, <&sys_clk>;
 458                 clock-names = "baud", "bus";
 459                 dmas = <&apdma 4
 460                         &apdma 5>;
 461                 dma-names = "tx", "rx";
 462                 status = "disabled";
 463         };
 464
 465         uart3: serial@11005000 {
 466                 compatible = "mediatek,mt2712-uart",
 467                              "mediatek,mt6577-uart";
 468                 reg = <0 0x11005000 0 0x400>;
 469                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 470                 clocks = <&baud_clk>, <&sys_clk>;
 471                 clock-names = "baud", "bus";
 472                 dmas = <&apdma 6
 473                         &apdma 7>;
 474                 dma-names = "tx", "rx";
 475                 status = "disabled";
 476         };
 477
 478         pwm: pwm@11006000 {
 479                 compatible = "mediatek,mt2712-pwm";
 480                 reg = <0 0x11006000 0 0x1000>;
 481                 #pwm-cells = <2>;
 482                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 483                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 484                          <&pericfg CLK_PERI_PWM>,
 485                          <&pericfg CLK_PERI_PWM0>,
 486                          <&pericfg CLK_PERI_PWM1>,
 487                          <&pericfg CLK_PERI_PWM2>,
 488                          <&pericfg CLK_PERI_PWM3>,
 489                          <&pericfg CLK_PERI_PWM4>,
 490                          <&pericfg CLK_PERI_PWM5>,
 491                          <&pericfg CLK_PERI_PWM6>,
 492                          <&pericfg CLK_PERI_PWM7>;
 493                 clock-names = "top",
 494                               "main",
 495                               "pwm1",
 496                               "pwm2",
 497                               "pwm3",
 498                               "pwm4",
 499                               "pwm5",
 500                               "pwm6",
 501                               "pwm7",
 502                               "pwm8";
 503                 status = "disabled";
 504         };
 505
 506         i2c0: i2c@11007000 {
 507                 compatible = "mediatek,mt2712-i2c";
 508                 reg = <0 0x11007000 0 0x90>,
 509                       <0 0x11000180 0 0x80>;
 510                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 511                 clock-div = <4>;
 512                 clocks = <&pericfg CLK_PERI_I2C0>,
 513                          <&pericfg CLK_PERI_AP_DMA>;
 514                 clock-names = "main",
 515                               "dma";
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 status = "disabled";
 519         };
 520
 521         i2c1: i2c@11008000 {
 522                 compatible = "mediatek,mt2712-i2c";
 523                 reg = <0 0x11008000 0 0x90>,
 524                       <0 0x11000200 0 0x80>;
 525                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 526                 clock-div = <4>;
 527                 clocks = <&pericfg CLK_PERI_I2C1>,
 528                          <&pericfg CLK_PERI_AP_DMA>;
 529                 clock-names = "main",
 530                               "dma";
 531                 #address-cells = <1>;
 532                 #size-cells = <0>;
 533                 status = "disabled";
 534         };
 535
 536         i2c2: i2c@11009000 {
 537                 compatible = "mediatek,mt2712-i2c";
 538                 reg = <0 0x11009000 0 0x90>,
 539                       <0 0x11000280 0 0x80>;
 540                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 541                 clock-div = <4>;
 542                 clocks = <&pericfg CLK_PERI_I2C2>,
 543                          <&pericfg CLK_PERI_AP_DMA>;
 544                 clock-names = "main",
 545                               "dma";
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         spi0: spi@1100a000 {
 552                 compatible = "mediatek,mt2712-spi";
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 reg = <0 0x1100a000 0 0x100>;
 556                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 557                 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 558                          <&topckgen CLK_TOP_SPI_SEL>,
 559                          <&pericfg CLK_PERI_SPI0>;
 560                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 561                 status = "disabled";
 562         };
 563
 564         nandc: nfi@1100e000 {
 565                 compatible = "mediatek,mt2712-nfc";
 566                 reg = <0 0x1100e000 0 0x1000>;
 567                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 568                 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
 569                 clock-names = "nfi_clk", "pad_clk";
 570                 ecc-engine = <&bch>;
 571                 #address-cells = <1>;
 572                 #size-cells = <0>;
 573                 status = "disabled";
 574         };
 575
 576         bch: ecc@1100f000 {
 577                 compatible = "mediatek,mt2712-ecc";
 578                 reg = <0 0x1100f000 0 0x1000>;
 579                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
 580                 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
 581                 clock-names = "nfiecc_clk";
 582                 status = "disabled";
 583         };
 584
 585         i2c3: i2c@11010000 {
 586                 compatible = "mediatek,mt2712-i2c";
 587                 reg = <0 0x11010000 0 0x90>,
 588                       <0 0x11000300 0 0x80>;
 589                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 590                 clock-div = <4>;
 591                 clocks = <&pericfg CLK_PERI_I2C3>,
 592                          <&pericfg CLK_PERI_AP_DMA>;
 593                 clock-names = "main",
 594                               "dma";
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 status = "disabled";
 598         };
 599
 600         i2c4: i2c@11011000 {
 601                 compatible = "mediatek,mt2712-i2c";
 602                 reg = <0 0x11011000 0 0x90>,
 603                       <0 0x11000380 0 0x80>;
 604                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
 605                 clock-div = <4>;
 606                 clocks = <&pericfg CLK_PERI_I2C4>,
 607                          <&pericfg CLK_PERI_AP_DMA>;
 608                 clock-names = "main",
 609                               "dma";
 610                 #address-cells = <1>;
 611                 #size-cells = <0>;
 612                 status = "disabled";
 613         };
 614
 615         i2c5: i2c@11013000 {
 616                 compatible = "mediatek,mt2712-i2c";
 617                 reg = <0 0x11013000 0 0x90>,
 618                       <0 0x11000100 0 0x80>;
 619                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
 620                 clock-div = <4>;
 621                 clocks = <&pericfg CLK_PERI_I2C5>,
 622                          <&pericfg CLK_PERI_AP_DMA>;
 623                 clock-names = "main",
 624                               "dma";
 625                 #address-cells = <1>;
 626                 #size-cells = <0>;
 627                 status = "disabled";
 628         };
 629
 630         spi2: spi@11015000 {
 631                 compatible = "mediatek,mt2712-spi";
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 reg = <0 0x11015000 0 0x100>;
 635                 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
 636                 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 637                          <&topckgen CLK_TOP_SPI_SEL>,
 638                          <&pericfg CLK_PERI_SPI2>;
 639                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 640                 status = "disabled";
 641         };
 642
 643         spi3: spi@11016000 {
 644                 compatible = "mediatek,mt2712-spi";
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 reg = <0 0x11016000 0 0x100>;
 648                 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
 649                 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 650                          <&topckgen CLK_TOP_SPI_SEL>,
 651                          <&pericfg CLK_PERI_SPI3>;
 652                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 653                 status = "disabled";
 654         };
 655
 656         spi4: spi@10012000 {
 657                 compatible = "mediatek,mt2712-spi";
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 reg = <0 0x10012000 0 0x100>;
 661                 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>;
 662                 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 663                          <&topckgen CLK_TOP_SPI_SEL>,
 664                          <&infracfg CLK_INFRA_AO_SPI0>;
 665                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 666                 status = "disabled";
 667         };
 668
 669         spi5: spi@11018000 {
 670                 compatible = "mediatek,mt2712-spi";
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 reg = <0 0x11018000 0 0x100>;
 674                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
 675                 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
 676                          <&topckgen CLK_TOP_SPI_SEL>,
 677                          <&pericfg CLK_PERI_SPI5>;
 678                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 679                 status = "disabled";
 680         };
 681
 682         uart4: serial@11019000 {
 683                 compatible = "mediatek,mt2712-uart",
 684                              "mediatek,mt6577-uart";
 685                 reg = <0 0x11019000 0 0x400>;
 686                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
 687                 clocks = <&baud_clk>, <&sys_clk>;
 688                 clock-names = "baud", "bus";
 689                 dmas = <&apdma 8
 690                         &apdma 9>;
 691                 dma-names = "tx", "rx";
 692                 status = "disabled";
 693         };
 694
 695         stmmac_axi_setup: stmmac-axi-config {
 696                 snps,wr_osr_lmt = <0x7>;
 697                 snps,rd_osr_lmt = <0x7>;
 698                 snps,blen = <0 0 0 0 16 8 4>;
 699         };
 700
 701         mtl_rx_setup: rx-queues-config {
 702                 snps,rx-queues-to-use = <1>;
 703                 snps,rx-sched-sp;
 704                 queue0 {
 705                         snps,dcb-algorithm;
 706                         snps,map-to-dma-channel = <0x0>;
 707                         snps,priority = <0x0>;
 708                 };
 709         };
 710
 711         mtl_tx_setup: tx-queues-config {
 712                 snps,tx-queues-to-use = <3>;
 713                 snps,tx-sched-wrr;
 714                 queue0 {
 715                         snps,weight = <0x10>;
 716                         snps,dcb-algorithm;
 717                         snps,priority = <0x0>;
 718                 };
 719                 queue1 {
 720                         snps,weight = <0x11>;
 721                         snps,dcb-algorithm;
 722                         snps,priority = <0x1>;
 723                 };
 724                 queue2 {
 725                         snps,weight = <0x12>;
 726                         snps,dcb-algorithm;
 727                         snps,priority = <0x2>;
 728                 };
 729         };
 730
 731         eth: ethernet@1101c000 {
 732                 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
 733                 reg = <0 0x1101c000 0 0x1300>;
 734                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
 735                 interrupt-names = "macirq";
 736                 mac-address = [00 55 7b b5 7d f7];
 737                 clock-names = "axi",
 738                               "apb",
 739                               "mac_main",
 740                               "ptp_ref",
 741                               "rmii_internal";
 742                 clocks = <&pericfg CLK_PERI_GMAC>,
 743                          <&pericfg CLK_PERI_GMAC_PCLK>,
 744                          <&topckgen CLK_TOP_ETHER_125M_SEL>,
 745                          <&topckgen CLK_TOP_ETHER_50M_SEL>,
 746                          <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
 747                 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
 748                                   <&topckgen CLK_TOP_ETHER_50M_SEL>,
 749                                   <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
 750                 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
 751                                          <&topckgen CLK_TOP_APLL1_D3>,
 752                                          <&topckgen CLK_TOP_ETHERPLL_50M>;
 753                 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
 754                 mediatek,pericfg = <&pericfg>;
 755                 snps,axi-config = <&stmmac_axi_setup>;
 756                 snps,mtl-rx-config = <&mtl_rx_setup>;
 757                 snps,mtl-tx-config = <&mtl_tx_setup>;
 758                 snps,txpbl = <1>;
 759                 snps,rxpbl = <1>;
 760                 snps,clk-csr = <0>;
 761                 status = "disabled";
 762         };
 763
 764         mmc0: mmc@11230000 {
 765                 compatible = "mediatek,mt2712-mmc";
 766                 reg = <0 0x11230000 0 0x1000>;
 767                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 768                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 769                          <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>,
 770                          <&pericfg CLK_PERI_MSDC30_0_QTR_EN>,
 771                          <&pericfg CLK_PERI_MSDC50_0_EN>;
 772                 clock-names = "source", "hclk", "bus_clk", "source_cg";
 773                 status = "disabled";
 774         };
 775
 776         mmc1: mmc@11240000 {
 777                 compatible = "mediatek,mt2712-mmc";
 778                 reg = <0 0x11240000 0 0x1000>;
 779                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 780                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 781                          <&topckgen CLK_TOP_AXI_SEL>,
 782                          <&pericfg CLK_PERI_MSDC30_1_EN>;
 783                 clock-names = "source", "hclk", "source_cg";
 784                 status = "disabled";
 785         };
 786
 787         mmc2: mmc@11250000 {
 788                 compatible = "mediatek,mt2712-mmc";
 789                 reg = <0 0x11250000 0 0x1000>;
 790                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 791                 clocks = <&pericfg CLK_PERI_MSDC30_2>,
 792                          <&topckgen CLK_TOP_AXI_SEL>,
 793                          <&pericfg CLK_PERI_MSDC30_2_EN>;
 794                 clock-names = "source", "hclk", "source_cg";
 795                 status = "disabled";
 796         };
 797
 798         ssusb: usb@11271000 {
 799                 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
 800                 reg = <0 0x11271000 0 0x3000>,
 801                       <0 0x11280700 0 0x0100>;
 802                 reg-names = "mac", "ippc";
 803                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
 804                 phys = <&u2port0 PHY_TYPE_USB2>,
 805                        <&u2port1 PHY_TYPE_USB2>;
 806                 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
 807                 clocks = <&topckgen CLK_TOP_USB30_SEL>;
 808                 clock-names = "sys_ck";
 809                 mediatek,syscon-wakeup = <&pericfg 0x510 2>;
 810                 #address-cells = <2>;
 811                 #size-cells = <2>;
 812                 ranges;
 813                 status = "disabled";
 814
 815                 usb_host0: usb@11270000 {
 816                         compatible = "mediatek,mt2712-xhci",
 817                                      "mediatek,mtk-xhci";
 818                         reg = <0 0x11270000 0 0x1000>;
 819                         reg-names = "mac";
 820                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>;
 821                         power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>;
 822                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 823                         clock-names = "sys_ck", "ref_ck";
 824                         status = "disabled";
 825                 };
 826         };
 827
 828         u3phy0: t-phy@11290000 {
 829                 compatible = "mediatek,mt2712-tphy",
 830                              "mediatek,generic-tphy-v2";
 831                 #address-cells = <1>;
 832                 #size-cells = <1>;
 833                 ranges = <0 0 0x11290000 0x9000>;
 834                 status = "okay";
 835
 836                 u2port0: usb-phy@0 {
 837                         reg = <0x0 0x700>;
 838                         clocks = <&clk26m>;
 839                         clock-names = "ref";
 840                         #phy-cells = <1>;
 841                         status = "okay";
 842                 };
 843
 844                 u2port1: usb-phy@8000 {
 845                         reg = <0x8000 0x700>;
 846                         clocks = <&clk26m>;
 847                         clock-names = "ref";
 848                         #phy-cells = <1>;
 849                         status = "okay";
 850                 };
 851
 852                 u3port0: usb-phy@8700 {
 853                         reg = <0x8700 0x900>;
 854                         clocks = <&clk26m>;
 855                         clock-names = "ref";
 856                         #phy-cells = <1>;
 857                         status = "okay";
 858                 };
 859         };
 860
 861         ssusb1: usb@112c1000 {
 862                 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3";
 863                 reg = <0 0x112c1000 0 0x3000>,
 864                       <0 0x112d0700 0 0x0100>;
 865                 reg-names = "mac", "ippc";
 866                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>;
 867                 phys = <&u2port2 PHY_TYPE_USB2>,
 868                        <&u2port3 PHY_TYPE_USB2>,
 869                        <&u3port1 PHY_TYPE_USB3>;
 870                 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
 871                 clocks = <&topckgen CLK_TOP_USB30_SEL>;
 872                 clock-names = "sys_ck";
 873                 mediatek,syscon-wakeup = <&pericfg 0x514 2>;
 874                 #address-cells = <2>;
 875                 #size-cells = <2>;
 876                 ranges;
 877                 status = "disabled";
 878
 879                 usb_host1: usb@112c0000 {
 880                         compatible = "mediatek,mt2712-xhci",
 881                                      "mediatek,mtk-xhci";
 882                         reg = <0 0x112c0000 0 0x1000>;
 883                         reg-names = "mac";
 884                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
 885                         power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>;
 886                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 887                         clock-names = "sys_ck", "ref_ck";
 888                         status = "disabled";
 889                 };
 890         };
 891
 892         u3phy1: t-phy@112e0000 {
 893                 compatible = "mediatek,mt2712-tphy",
 894                              "mediatek,generic-tphy-v2";
 895                 #address-cells = <1>;
 896                 #size-cells = <1>;
 897                 ranges = <0 0 0x112e0000 0x9000>;
 898                 status = "okay";
 899
 900                 u2port2: usb-phy@0 {
 901                         reg = <0x0 0x700>;
 902                         clocks = <&clk26m>;
 903                         clock-names = "ref";
 904                         #phy-cells = <1>;
 905                         status = "okay";
 906                 };
 907
 908                 u2port3: usb-phy@8000 {
 909                         reg = <0x8000 0x700>;
 910                         clocks = <&clk26m>;
 911                         clock-names = "ref";
 912                         #phy-cells = <1>;
 913                         status = "okay";
 914                 };
 915
 916                 u3port1: usb-phy@8700 {
 917                         reg = <0x8700 0x900>;
 918                         clocks = <&clk26m>;
 919                         clock-names = "ref";
 920                         #phy-cells = <1>;
 921                         status = "okay";
 922                 };
 923         };
 924
 925         pcie1: pcie@112ff000 {
 926                 compatible = "mediatek,mt2712-pcie";
 927                 device_type = "pci";
 928                 reg = <0 0x112ff000 0 0x1000>;
 929                 reg-names = "port1";
 930                 linux,pci-domain = <1>;
 931                 #address-cells = <3>;
 932                 #size-cells = <2>;
 933                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 934                 interrupt-names = "pcie_irq";
 935                 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
 936                          <&pericfg CLK_PERI_PCIE1>;
 937                 clock-names = "sys_ck1", "ahb_ck1";
 938                 phys = <&u3port1 PHY_TYPE_PCIE>;
 939                 phy-names = "pcie-phy1";
 940                 bus-range = <0x00 0xff>;
 941                 ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;
 942                 status = "disabled";
 943
 944                 #interrupt-cells = <1>;
 945                 interrupt-map-mask = <0 0 0 7>;
 946                 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 947                                 <0 0 0 2 &pcie_intc1 1>,
 948                                 <0 0 0 3 &pcie_intc1 2>,
 949                                 <0 0 0 4 &pcie_intc1 3>;
 950                 pcie_intc1: interrupt-controller {
 951                         interrupt-controller;
 952                         #address-cells = <0>;
 953                         #interrupt-cells = <1>;
 954                 };
 955         };
 956
 957         pcie0: pcie@11700000 {
 958                 compatible = "mediatek,mt2712-pcie";
 959                 device_type = "pci";
 960                 reg = <0 0x11700000 0 0x1000>;
 961                 reg-names = "port0";
 962                 linux,pci-domain = <0>;
 963                 #address-cells = <3>;
 964                 #size-cells = <2>;
 965                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 966                 interrupt-names = "pcie_irq";
 967                 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
 968                          <&pericfg CLK_PERI_PCIE0>;
 969                 clock-names = "sys_ck0", "ahb_ck0";
 970                 phys = <&u3port0 PHY_TYPE_PCIE>;
 971                 phy-names = "pcie-phy0";
 972                 bus-range = <0x00 0xff>;
 973                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 974                 status = "disabled";
 975
 976                 #interrupt-cells = <1>;
 977                 interrupt-map-mask = <0 0 0 7>;
 978                 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 979                                 <0 0 0 2 &pcie_intc0 1>,
 980                                 <0 0 0 3 &pcie_intc0 2>,
 981                                 <0 0 0 4 &pcie_intc0 3>;
 982                 pcie_intc0: interrupt-controller {
 983                         interrupt-controller;
 984                         #address-cells = <0>;
 985                         #interrupt-cells = <1>;
 986                 };
 987         };
 988
 989         mfgcfg: syscon@13000000 {
 990                 compatible = "mediatek,mt2712-mfgcfg", "syscon";
 991                 reg = <0 0x13000000 0 0x1000>;
 992                 #clock-cells = <1>;
 993         };
 994
 995         mmsys: syscon@14000000 {
 996                 compatible = "mediatek,mt2712-mmsys", "syscon";
 997                 reg = <0 0x14000000 0 0x1000>;
 998                 #clock-cells = <1>;
 999         };
1000
1001         larb0: larb@14021000 {
1002                 compatible = "mediatek,mt2712-smi-larb";
1003                 reg = <0 0x14021000 0 0x1000>;
1004                 mediatek,smi = <&smi_common0>;
1005                 mediatek,larb-id = <0>;
1006                 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1007                 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1008                          <&mmsys CLK_MM_SMI_LARB0>;
1009                 clock-names = "apb", "smi";
1010         };
1011
1012         smi_common0: smi@14022000 {
1013                 compatible = "mediatek,mt2712-smi-common";
1014                 reg = <0 0x14022000 0 0x1000>;
1015                 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1016                 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1017                          <&mmsys CLK_MM_SMI_COMMON>;
1018                 clock-names = "apb", "smi";
1019         };
1020
1021         larb4: larb@14027000 {
1022                 compatible = "mediatek,mt2712-smi-larb";
1023                 reg = <0 0x14027000 0 0x1000>;
1024                 mediatek,smi = <&smi_common1>;
1025                 mediatek,larb-id = <4>;
1026                 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1027                 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1028                          <&mmsys CLK_MM_SMI_LARB4>;
1029                 clock-names = "apb", "smi";
1030         };
1031
1032         larb5: larb@14030000 {
1033                 compatible = "mediatek,mt2712-smi-larb";
1034                 reg = <0 0x14030000 0 0x1000>;
1035                 mediatek,smi = <&smi_common1>;
1036                 mediatek,larb-id = <5>;
1037                 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1038                 clocks = <&mmsys CLK_MM_SMI_LARB5>,
1039                          <&mmsys CLK_MM_SMI_LARB5>;
1040                 clock-names = "apb", "smi";
1041         };
1042
1043         smi_common1: smi@14031000 {
1044                 compatible = "mediatek,mt2712-smi-common";
1045                 reg = <0 0x14031000 0 0x1000>;
1046                 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1047                 clocks = <&mmsys CLK_MM_SMI_COMMON1>,
1048                          <&mmsys CLK_MM_SMI_COMMON1>;
1049                 clock-names = "apb", "smi";
1050         };
1051
1052         larb7: larb@14032000 {
1053                 compatible = "mediatek,mt2712-smi-larb";
1054                 reg = <0 0x14032000 0 0x1000>;
1055                 mediatek,smi = <&smi_common1>;
1056                 mediatek,larb-id = <7>;
1057                 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>;
1058                 clocks = <&mmsys CLK_MM_SMI_LARB7>,
1059                          <&mmsys CLK_MM_SMI_LARB7>;
1060                 clock-names = "apb", "smi";
1061         };
1062
1063         imgsys: syscon@15000000 {
1064                 compatible = "mediatek,mt2712-imgsys", "syscon";
1065                 reg = <0 0x15000000 0 0x1000>;
1066                 #clock-cells = <1>;
1067         };
1068
1069         larb2: larb@15001000 {
1070                 compatible = "mediatek,mt2712-smi-larb";
1071                 reg = <0 0x15001000 0 0x1000>;
1072                 mediatek,smi = <&smi_common0>;
1073                 mediatek,larb-id = <2>;
1074                 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>;
1075                 clocks = <&imgsys CLK_IMG_SMI_LARB2>,
1076                          <&imgsys CLK_IMG_SMI_LARB2>;
1077                 clock-names = "apb", "smi";
1078         };
1079
1080         bdpsys: syscon@15010000 {
1081                 compatible = "mediatek,mt2712-bdpsys", "syscon";
1082                 reg = <0 0x15010000 0 0x1000>;
1083                 #clock-cells = <1>;
1084         };
1085
1086         vdecsys: syscon@16000000 {
1087                 compatible = "mediatek,mt2712-vdecsys", "syscon";
1088                 reg = <0 0x16000000 0 0x1000>;
1089                 #clock-cells = <1>;
1090         };
1091
1092         larb1: larb@16010000 {
1093                 compatible = "mediatek,mt2712-smi-larb";
1094                 reg = <0 0x16010000 0 0x1000>;
1095                 mediatek,smi = <&smi_common0>;
1096                 mediatek,larb-id = <1>;
1097                 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>;
1098                 clocks = <&vdecsys CLK_VDEC_CKEN>,
1099                          <&vdecsys CLK_VDEC_LARB1_CKEN>;
1100                 clock-names = "apb", "smi";
1101         };
1102
1103         vencsys: syscon@18000000 {
1104                 compatible = "mediatek,mt2712-vencsys", "syscon";
1105                 reg = <0 0x18000000 0 0x1000>;
1106                 #clock-cells = <1>;
1107         };
1108
1109         larb3: larb@18001000 {
1110                 compatible = "mediatek,mt2712-smi-larb";
1111                 reg = <0 0x18001000 0 0x1000>;
1112                 mediatek,smi = <&smi_common0>;
1113                 mediatek,larb-id = <3>;
1114                 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1115                 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1116                          <&vencsys CLK_VENC_VENC>;
1117                 clock-names = "apb", "smi";
1118         };
1119
1120         larb6: larb@18002000 {
1121                 compatible = "mediatek,mt2712-smi-larb";
1122                 reg = <0 0x18002000 0 0x1000>;
1123                 mediatek,smi = <&smi_common0>;
1124                 mediatek,larb-id = <6>;
1125                 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>;
1126                 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>,
1127                          <&vencsys CLK_VENC_VENC>;
1128                 clock-names = "apb", "smi";
1129         };
1130
1131         jpgdecsys: syscon@19000000 {
1132                 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
1133                 reg = <0 0x19000000 0 0x1000>;
1134                 #clock-cells = <1>;
1135         };
1136 };
1137