1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2019 Marvell International Ltd.
5 * Device tree for the CN9130-DB board.
10 #include <dt-bindings/gpio/gpio.h>
14 stdout-path = "serial0:115200n8";
21 ethernet0 = &cp0_eth0;
22 ethernet1 = &cp0_eth1;
23 ethernet2 = &cp0_eth2;
29 device_type = "memory";
30 reg = <0x0 0x0 0x0 0x80000000>;
33 ap0_reg_sd_vccq: ap0_sd_vccq@0 {
34 compatible = "regulator-gpio";
35 regulator-name = "ap0_sd_vccq";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <3300000>;
38 gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
39 states = <1800000 0x1 3300000 0x0>;
42 cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
43 compatible = "regulator-fixed";
44 regulator-name = "cp0-xhci0-vbus";
45 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>;
48 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
51 cp0_usb3_0_phy0: cp0_usb3_phy@0 {
52 compatible = "usb-nop-xceiv";
53 vcc-supply = <&cp0_reg_usb3_vbus0>;
56 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
57 compatible = "regulator-fixed";
58 regulator-name = "cp0-xhci1-vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
62 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
65 cp0_usb3_0_phy1: cp0_usb3_phy@1 {
66 compatible = "usb-nop-xceiv";
67 vcc-supply = <&cp0_reg_usb3_vbus1>;
70 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
71 compatible = "regulator-gpio";
72 regulator-name = "cp0_sd_vccq";
73 regulator-min-microvolt = <1800000>;
74 regulator-max-microvolt = <3300000>;
75 gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
80 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
81 compatible = "regulator-fixed";
82 regulator-name = "cp0_sd_vcc";
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
90 cp0_sfp_eth0: sfp-eth@0 {
91 compatible = "sff,sfp";
92 i2c-bus = <&cp0_sfpp0_i2c>;
93 los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
94 mod-def0-gpios = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
95 tx-disable-gpios = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
96 tx-fault-gpios = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
98 * SFP cages are unconnected on early PCBs because of an the I2C
99 * lanes not being connected. Prevent the port for being
100 * unusable by disabling the SFP node.
110 /* on-board eMMC - U9 */
112 pinctrl-names = "default";
114 vqmmc-supply = <&ap0_reg_sd_vccq>;
126 /* SLM-1521-V2, CON9 */
129 phy-mode = "10gbase-r";
130 /* Generic PHY, providing serdes lanes */
131 phys = <&cp0_comphy4 0>;
132 managed = "in-band-status";
133 sfp = <&cp0_sfp_eth0>;
140 phy-mode = "rgmii-id";
147 phy-mode = "rgmii-id";
160 pinctrl-names = "default";
161 pinctrl-0 = <&cp0_i2c0_pins>;
162 clock-frequency = <100000>;
165 expander0: pca953x@21 {
166 compatible = "nxp,pca9555";
167 pinctrl-names = "default";
176 compatible = "atmel,24c64";
183 compatible = "atmel,24c64";
191 clock-frequency = <100000>;
193 /* SLM-1521-V2 - U3 */
194 i2c-mux@72 { /* verify address - depends on dpr */
195 compatible = "nxp,pca9544";
196 #address-cells = <1>;
199 cp0_sfpp0_i2c: i2c@0 {
200 #address-cells = <1>;
206 #address-cells = <1>;
210 cp0_module_expander1: pca9555@21 {
211 compatible = "nxp,pca9555";
212 pinctrl-names = "default";
225 phy0: ethernet-phy@0 {
229 phy1: ethernet-phy@1 {
235 &cp0_nand_controller {
237 pinctrl-names = "default";
238 pinctrl-0 = <&nand_pins &nand_rb>;
242 label = "main-storage";
244 nand-ecc-mode = "hw";
246 nand-ecc-strength = <8>;
247 nand-ecc-step-size = <512>;
250 compatible = "fixed-partitions";
251 #address-cells = <1>;
260 reg = <0x200000 0xe00000>;
263 label = "Filesystem";
264 reg = <0x1000000 0x3f000000>;
270 /* SLM-1521-V2, CON6 */
275 /* Generic PHY, providing serdes lanes */
276 phys = <&cp0_comphy0 0
285 /* SLM-1521-V2, CON2 */
288 /* Generic PHY, providing serdes lanes */
289 phys = <&cp0_comphy5 1>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&cp0_sdhci_pins
300 cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
302 vqmmc-supply = <&cp0_reg_sd_vccq>;
303 vmmc-supply = <&cp0_reg_sd_vcc>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&cp0_spi1_pins>;
311 reg = <0x700680 0x50>;
314 #address-cells = <0x1>;
316 compatible = "jedec,spi-nor";
318 /* On-board MUX does not allow higher frequencies */
319 spi-max-frequency = <40000000>;
322 compatible = "fixed-partitions";
323 #address-cells = <1>;
328 reg = <0x0 0x200000>;
332 label = "Filesystem-0";
333 reg = <0x200000 0xe00000>;
340 cp0_pinctrl: pinctrl {
341 compatible = "marvell,cp115-standalone-pinctrl";
343 cp0_i2c0_pins: cp0-i2c-pins-0 {
344 marvell,pins = "mpp37", "mpp38";
345 marvell,function = "i2c0";
347 cp0_i2c1_pins: cp0-i2c-pins-1 {
348 marvell,pins = "mpp35", "mpp36";
349 marvell,function = "i2c1";
351 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
352 marvell,pins = "mpp0", "mpp1", "mpp2",
353 "mpp3", "mpp4", "mpp5",
354 "mpp6", "mpp7", "mpp8",
355 "mpp9", "mpp10", "mpp11";
356 marvell,function = "ge0";
358 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
359 marvell,pins = "mpp44", "mpp45", "mpp46",
360 "mpp47", "mpp48", "mpp49",
361 "mpp50", "mpp51", "mpp52",
362 "mpp53", "mpp54", "mpp55";
363 marvell,function = "ge1";
365 cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
366 marvell,pins = "mpp43";
367 marvell,function = "gpio";
369 cp0_sdhci_pins: cp0-sdhi-pins-0 {
370 marvell,pins = "mpp56", "mpp57", "mpp58",
371 "mpp59", "mpp60", "mpp61";
372 marvell,function = "sdio";
374 cp0_spi1_pins: cp0-spi-pins-1 {
375 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
376 marvell,function = "spi1";
378 nand_pins: nand-pins {
379 marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
380 "mpp19", "mpp20", "mpp21", "mpp22",
381 "mpp23", "mpp24", "mpp25", "mpp26",
383 marvell,function = "dev";
386 marvell,pins = "mpp13";
387 marvell,function = "nf";
398 usb-phy = <&cp0_usb3_0_phy0>;
406 usb-phy = <&cp0_usb3_0_phy1>;